UCC3952A-1 [TI]
SINGLE-CELL LITHIUM-LON BATTERY PROTECTION IC; 单节锂- LON电池保护IC
| 型号： | UCC3952A-1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE-CELL LITHIUM-LON BATTERY PROTECTION IC |
| 文件： | 总9页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢉ ꢀꢁꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢊ
ꢋꢌ ꢍꢎ ꢏ ꢐꢑꢁꢐꢏ ꢏ ꢏ ꢌꢒ ꢓꢌ ꢀꢔꢑꢌ ꢕ ꢍ ꢖꢆꢒ ꢒꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐ ꢁꢒ ꢌꢕ ꢍ ꢌ ꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
D
Protects Sensitive Lithium-Ion Cells From
Overcharging and Over-Discharging
GSH PACKAGE
(TOP VIEW)
D
Dedicated for One-Cell Applications
D
Integrated Low-Impedance MOSFET Switch
and Sense Resistor
NC
NC
PACK+
CBPS
18
17
1
16
15
D
Precision Trimmed Overcharge and
Overdischarge Voltage Limits
2
3
4
5
6
14 NC
BNEG
BNEG
BNEG
D
D
D
D
D
Extremely Low Power Drain
3.5-A Current Capacity
13 PACK−
12 PACK−
Overcurrent and Short-Circuit Protection
Reverse Charger Protection
Thermal Protection
PACK−
PACK−
11
10
BNEG
BNEG
7
9
8
description
The UCC3952A is a monolithic BiCMOS lithium−ion battery protection circuit designed to enhance the useful
operating life of a one-cell rechargeable battery pack. Cell protection features include internally trimmed charge
and discharge voltage limits, discharge current limit with a delayed shutdown, and an ultra-low-current sleep
mode state when the cell is discharged. Additional features include an on-chip MOSFET for reduced external
component count and a charge pump for reduced power losses while charging or discharging a low-cell-voltage
battery pack. This protection circuit requires one external capacitor and can operate and safely shut down in
a short circuit condition.
application diagram
TCLK
18
PACK+
PACK+
17
1
2
NC
16
15
3 kΩ
CBPS
+
NC
µ
0.1
F
3
4
5
6
BNEG
BNEG
BNEG
BNEG
NC 14
PACK− 13
PACK− 12
PACK− 11
PACK− 10
CHARGER
LOAD
BNEG
NC
PACK−
9
7
8
UDG−98205
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2001, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢅꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇꢂ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢊ
ꢋ ꢌꢍ ꢎꢏ ꢐꢑ ꢁꢐ ꢏꢏ ꢏꢌ ꢒ ꢓꢌ ꢀ ꢔꢑꢌ ꢕꢍ ꢖꢆꢒꢒ ꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐꢁꢒ ꢌ ꢕ ꢍ ꢌꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
AVAILABLE OPTIONS
NORMAL TO OVERCHARGE
OVERVOLTAGE TO NORMAL RECOVERY
PACKAGES
BCC−18 (GSH)
T
A
MIN
4.15
4.20
4.25
4.30
TYP
4.2
MAX
4.25
4.30
4.35
4.40
MIN
3.85
3.90
3.95
4.00
TYP
3.90
3.95
4.00
4.05
MAX
3.95
4.00
4.05
4.10
UNIT
UCC3952AGSH−1
UCC3952AGSH−2
UCC3952AGSH−3
UCC3952AGSH−4
V
V
V
V
4.25
4.30
4.35
−20°C to 70°C
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage (PACK+ to BNEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum forward voltage (PACK+ to PACK−) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Maximum reverse voltage (where PACK+ to BNEG = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V
Maximum cell continuous charge current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 A
Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Data Book for thermal limitations and
considerations of packages. All voltages are referenced to GND.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢉ ꢀꢁꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢊ
ꢋꢌ ꢍꢎ ꢏ ꢐꢑꢁꢐꢏ ꢏ ꢏ ꢌꢒ ꢓꢌ ꢀꢔꢑꢌ ꢕ ꢍ ꢖꢆꢒ ꢒꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐ ꢁꢒ ꢌꢕ ꢍ ꢌ ꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
electrical characteristics, T = −20°C to 70°C, all voltages are with respect to BNEG
A
(unless otherwise stated)
state transition threshold
PARAMETER
TEST CONDITIONS
MIN
4.15
4.175
4.20
4.225
4.25
4.275
4.30
4.325
3.85
3.87
3.90
3.92
3.95
3.97
4.00
4.02
2.25
2.26
2.55
2.57
10
TYP
MAX UNITS
4.20
4.25
V
UCC3952A−1
UCC3952A−2
UCC3952A−3
UCC3952A−4
UCC3952A−1
UCC3952A−2
UCC3952A−3
UCC3952A−4
T
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
4.20 4.235
A
4.25
4.25 4.285
4.30 4.35
4.30 4.335
4.35 4.40
4.35 4.385
4.30
V
V
T
A
V
OV
Normal to overcharge voltage
T
A
V
T
A
3.90
3.90
3.95
3.95
4.00
4.00
4.05
4.05
2.35
2.35
2.65
2.65
25
3.95
3.94
4.00
3.99
4.05
4.04
4.10
4.09
2.45
2.44
2.75
2.73
40
V
T
A
V
T
A
V
OVR
Overcharge to normal recovery voltage
V
T
A
V
T
A
V
V
Normal to undercharge
V
UV
T
A
Undercharge to normal recovery
Overdischarge delay time
V
UVR
dOD
T
A
t
t
ms
T
A
13.5
1.0
25
36
1.75
1.75
2.5
Overvoltage delay time
s
dOV
T
A
= 25°C
1.15
2.3
short circuit protection
PARAMETER
TEST CONDITIONS
PACK+ = 3.7 V
MIN
3.5
3.8
1
TYP
MAX UNITS
5
5
2
2
6.5
I
t
Discharge current limit
A
THLD
PACK+ = 3.7 V,
PACK+ = 3.7 V,
PACK+ = 3.7 V,
PACK+ = 3.7 V
PACK+ = 3.7 V,
T
= 25°C
6.3
A
I = 6.5 A
I
3.0
Discharge current delay
ms
dDLY
I = 6.5 A, T = 25°C
I
1.05
7.5
7.4
2.9
A
R
Discharge current reset resistance
MΩ
RESET
T
A
= 25°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢅꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇꢂ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢊ
ꢋ ꢌꢍ ꢎꢏ ꢐꢑ ꢁꢐ ꢏꢏ ꢏꢌ ꢒ ꢓꢌ ꢀ ꢔꢑꢌ ꢕꢍ ꢖꢆꢒꢒ ꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐꢁꢒ ꢌ ꢕ ꢍ ꢌꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
electrical characteristics, T = −20°C to 70°C, all voltages are with respect to BNEG (unless
A
otherwise stated) (continued)
bias
PARAMETER
Supply current
TEST CONDITIONS
MIN
TYP
5
MAX UNITS
V
V
V
V
V
V
< V
< V
< V
< V
8
UV
UV
OV
PACK
PACK
PACK
OV
I
I
I
µA
DD
< V
T
= 25°C
= 25°C
5
7.5
OV,
A
11
11
24
Operating supply current in overvoltage
Shutdown current
µA
DDov
SD
< V
(PACK),
T
22
(OV)
A
= 2.0 V
= 2.0 V,
2.5
(PACK)
(PACK)
µA
T
A
= 25°C
2.25
Minimum cell voltage when all circuits are fully
functional
V
min
1.7
V
FET switch
PARAMETER
TEST CONDITIONS
1 mA < I < 2 A,
SWITCH
MIN
TYP
MAX UNITS
V
> V
,
PACK
OV
Battery overcharged state switch permits discharge
current only.
100
400
350
mV
mV
mV
mV
mΩ
mΩ
V
PACK
> V
,
1 mA < I
< 2 A,
OV
SWITCH
Battery overcharged state switch permits discharge
100
current only,
T = 25°C
A
V
Voltage at PACK−
PACK−
PACK+ = 2.5V,
−2 mA < I < −1 A,
SWITCH
Battery overdischarged state switch permits charge
current only.
−600 −100
PACK+ = 2.5V,
−2 mA < I
SWITCH
< −1 A,
Battery overdischarged state switch permits charge
−540 −100
current only,
T = 25°C
A
PACK+ = 2.5 V,
In normal mode (when not in OV or UV). This value
includes package and bondwire resistance.
60
60
80
70
R
Series resistance of the device
ON
PACK+ = 2.5 V,
T = 25°C
A
In normal mode (when not in OV or UV). This value
includes package and bondwire resistance.
thermal shutdown
PARAMETER
Thermal shutdown temperature (see Note 2)
NOTE 2: This parameter is ensured by design and is not production tested.
TEST CONDITIONS
MIN
TYP
MAX UNITS
T
(SD)
135
°C
4
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢉ ꢀꢁꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢊ
ꢋꢌ ꢍꢎ ꢏ ꢐꢑꢁꢐꢏ ꢏ ꢏ ꢌꢒ ꢓꢌ ꢀꢔꢑꢌ ꢕ ꢍ ꢖꢆꢒ ꢒꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐ ꢁꢒ ꢌꢕ ꢍ ꢌ ꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
APPLICATION INFORMATION
PACK+ 17
PACK+ 16
10 kΩ
V
UV
CBPS 15
V
UVR
4−1
MUX
T
DEL
OV
TCLK 18
V
1 SEC
OVR
STATE
MACHINE
LOGIC
T
THRESHOLD
COMPARATOR
NC
NC
1
2
3
4
5
6
7
8
9
V
OV
1.5 V
SEL
DEL
UV
10 mS
CLK
BNEG
BNEG
BNEG
BNEG
BNEG
NC
SYSTEM
CLOCK
GENERATOR
TDLS
1 mS
SETD
RST
V
PUMP
50 mV
2 MΩ
50 mV
PACK−
THERMAL
SHUTDOWN
PACK− 10
PACK− 11
PACK− 12
NC 14
PACK− 13
UDG−98205
Figure 1. Detailed Block Diagram
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢅꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇꢂ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢊ
ꢋ ꢌꢍ ꢎꢏ ꢐꢑ ꢁꢐ ꢏꢏ ꢏꢌ ꢒ ꢓꢌ ꢀ ꢔꢑꢌ ꢕꢍ ꢖꢆꢒꢒ ꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐꢁꢒ ꢌ ꢕ ꢍ ꢌꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
pin descriptions
BNEG
Connect the negative terminal of the battery to this pin.
PACK+
Connect to the positive terminal of the battery. This pin is available to the user.
CBPS
This power supply bypass pin is connected to PACK+ through an internal 3-kΩ resistor. An external 0.1-µF
capacitor must be connected between this pin and BNEG.
PACK–
The negative terminal of the battery pack (negative terminal available to the user). The internal FET switch
connects this terminal to the BNEG terminal to give the battery pack user appropriate access to the battery. In
an overcharged state, only discharge current is permitted. In an overdischarged state, only charge current is
permitted.
TCLK
Production test mode pin. This pin is used to provide a high-frequency clock to the IC during production testing.
In an application, this pin is left unconnected or tied to BNEG.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢅ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢉ ꢀꢁꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢊ
ꢋꢌ ꢍꢎ ꢏ ꢐꢑꢁꢐꢏ ꢏ ꢏ ꢌꢒ ꢓꢌ ꢀꢔꢑꢌ ꢕ ꢍ ꢖꢆꢒ ꢒꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐ ꢁꢒ ꢌꢕ ꢍ ꢌ ꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
APPLICATION INFORMATION
battery voltage monitoring
The battery cell voltage is sampled by connecting a resistor divider across it and comparing the resulting voltage
to a precision internal reference voltage. Under normal conditions (cell voltage is below the overvoltage
threshold and above the undervoltage threshold), the UCC3952A consumes less than 8 µA of current and the
internal MOSFET is fully turned on with the aid of a charge pump.
When the cell voltage falls below the undervoltage threshold for two consecutive samples, the IC disconnects
the load from the battery pack and enters a super-low-power mode. The pack remains in this state until it detects
the application of a charger, at which point charging is enabled. The requirement of two consecutive readings
below the undervoltage threshold filters out momentary drops in cell voltage due to load transients, preventing
nuisance trips.
If the cell voltage exceeds the overvoltage threshold for the overcharge delay time, charging is disabled;
however, discharge current is still allowed. This feature of the IC is explained further in the controlled
charge/discharge mode section of this document.
overcurrent monitoring and protection
Discharge current is continuously monitored via an internal sense resistor. In the event of excessive current,
an overcurrent condition is declared if the high current persists for t
. This delay allows for charging of the
dDLY
system bypass capacitors without tripping the overcurrent protection. A 0.1-µF capacitor on the CBPS pin
provides momentary holdup for the IC to assure proper operation in the event that a hard short suddenly pulls
the cell voltage below the minimum operating voltage.
Once the overcurrent condition has been declared, the internal MOSFET turns off. To return the device to normal
operation, the UCC3952A needs to have a load impedance greater than 7.5 MΩ placed across PACK+ to
PACK−. This typically can be achieved by removing the battery pack from the system. At this point, the pack
returns to its normal state of operation.
controlled charge/discharge mode
When the chip senses an overvoltage condition, it prevents any additional charging, but allows discharge. This
is accomplished by activating a linear control loop, which controls the gate of the MOSFET based on the
differential voltage across its drain-to-source terminals. The linear loop attempts to regulate the differential
voltage across the MOSFET to 100 mV. When a light load is applied to the part, the loop adjusts the impedance
of the MOSFET to maintain 100 mV across it. As the load increases, the impedance of the MOSFET is
decreased to maintain the 100-mV control. At heavy loads (still below the overcurrent limit), the loop does not
maintain regulation and drives the gate of the MOSFET to the battery voltage (not the charge-pump output
voltage). The MOSFET R
in the overvoltage state is higher than R
during normal operation. The
DS(on)
DS(on)
voltage drop (and associated power loss) across the internal MOSFET in this mode of operation is still
significantly lower than the typical solution of two external back-to-back MOSFETs, where the body diode is
conducting.
When the chip senses an undervoltage condition, it disconnects the load from the battery pack and shuts itself
down to minimize current drain from the battery. Several circuits remain powered and detect placement of the
battery pack into a charger. Once the charger presence is detected, the linear loop is activated and the chip
allows charging current into the battery. This linear control mode of operation is in effect until the battery voltage
reaches a level of V
, at which time normal operation is resumed.
UVR
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢅꢉ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇꢂ ꢉ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢇꢊ
ꢋ ꢌꢍ ꢎꢏ ꢐꢑ ꢁꢐ ꢏꢏ ꢏꢌ ꢒ ꢓꢌ ꢀ ꢔꢑꢌ ꢕꢍ ꢖꢆꢒꢒ ꢐ ꢗꢘ ꢙꢗ ꢕꢒ ꢐꢁꢒ ꢌ ꢕ ꢍ ꢌꢁ
ꢚ
SLUS463C − AUGUST 2000 − REVISED MARCH 2001
GSH (R-PLGA-N18)
PLASTIC LAND GRID ARRAY
0,60
0,40
3,50
3,30
2,70 TYP
0,50
0,30
1,30
4,65
4,45
4,05 TYP
3,90 TYP
0,50
0,30
0,40
0,20
2,90 TYP
0,80 MAX
Seating Plane
0,05
0,10 MAX
4200956/A 07/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
8
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