UCC3958PWPTR-1 [TI]
Single Cell Lithium-Ion Battery Protection Circuit;
| 型号： | UCC3958PWPTR-1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single Cell Lithium-Ion Battery Protection Circuit 电池 |
| 文件： | 总8页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC3958 -1/-2/-3/-4
PRELIMINARY
Single Cell Lithium-Ion Battery Protection Circuit
FEATURES
DESCRIPTION
• Protects Sensitive Lithium-Ion Cells Form
Over Charging and Over Discharging
UCC3958 is a monolithic BCMOS lithium-ion battery protection
circuit that is designed to enhance the useful operating life of
one cell rechargeable battery packs. Cell protection features
consist of internally trimmed charge and discharge voltage lim-
its, discharge current limit with a delayed shutdown and an ultra
low current sleep mode state when the cell is discharged. Addi-
tional features include an on chip MOSFET for reduced exter-
nal component count and a charge pump for reduced power
losses while charging or discharging a low cell voltage battery
pack. This protection circuit requires a minimum number of ex-
ternal components and is able to operate and safely shutdown
in the presence of a short circuit load.
• Dedicated for One Cell Applications
• Does Not Require External FETs or Sense
Resistors
• Internal Precision Trimmed Charge and
Discharge Voltage Limits
• Extremely Low Power Drain
• Low FET Switch Voltage Drop of 150mV
Typical for 3A Currents
• Short Circuit Current Protection (with User
Programmable Delay)
• 3A Current Capacity
• Thermal Shutdown
• User Controlled Enable Pin
BLOCK DIAGRAM
UDG-98050
6/98
UCC3958 -1/-2/-3/-4
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (PACK+ to BNEG). . . . . . . . . . . . . . . . . . . 7.5V
Maximum Continuous Charge Current . . . . . . . . . . . . . . . . . 3A
Maximum Charger Voltage (PACK+ to PACK–) . . . . . . . . . . 9V
Maximum Reverse Voltage (PACK+ to PACK–) . . . . . . . . . –8V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations and
considerations of packages.
CONNECTION DIAGRAMS
SOIC-16 (Top View)
DP Package
TSSOP-24 (Top View)
PWP Package
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, PACK+ = 4V, –20°C < TA < 70°C. All voltages
measured with respect to BNEG. TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
State Transition Thresholds
NORM to OV (VOV
)
UCC3958-1
UCC3958-1
UCC3958-2
UCC3958-2
UCC3958-3
UCC3958-3
UCC3958-4
UCC3958-4
(Note 1)
4.15
3.85
4.20
3.90
4.25
3.95
4.30
4.00
2.25
2.55
7
4.20
3.90
4.25
3.95
4.30
4.00
4.35
4.05
2.35
2.65
18
4.25
3.95
4.30
4.00
4.35
4.05
4.40
4.10
2.45
2.75
34
V
V
OV to NORM (VTHI
)
)
)
)
NORM to OV (VOV
)
V
OV to NORM (VTHI
V
NORM to OV (VOV
)
V
OV to NORM (VTHI
V
NORM to OV (VOV
)
V
OV to NORM (VTHI
V
NORM to UV (VUV
UV to NORM (VTLO
OV, UV Delay Time (TD)
)
V
)
V
All Dash Numbers
2
msec
UCC3958 -1/-2/-3/-4
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, PACK+ = 4V, –20°C < TA < 70°C. All voltages
measured with respect to BNEG. TA = TJ.
PARAMETER
TEST CONDITIONS
NORM, ISWITCH = 2A
MIN
TYP
MAX UNITS
BNEG/PACK - SWITCH
VBNEG - VPACK
–100 –150
100 150
–100 –300
mV
mV
mV
NORM, ISWITCH = –2A
VPACK+ > VOV, ISWITCH = 20mA to 2A,
(OV State)
VPACK+ = 2.5V, ISWITCH = –20mA to –2A,
(UV State)
100
600
mV
RDSON
NORM ISWITCH = 2A
NORM ISWITCH = –2A
50
50
1
75
75
20
mΩ
mΩ
µA
I
BNEG – (Charger Leakage Current in OV)
VPACK+ > VOV (OV State)
([VPACK+] – [VPACK–]=6V)
BIAS Current
IPACK
IPACK
VBAT
+
+
VPACK+ > VUV
7
1
20
1.5
1.5
17
µA
µA
V
In Super Low Power Mode (VPACK+ < VUV
Minimum Operating Cell Voltage
)
Battery Sample Rate (TS)
Short Circuit Protection
ITHLD
7
12
ms
2.75
5.25
350
2.5
7.25
A
TDLY
CDLY = 0
µs
ms
CDLY = 100pF
(Maximum Recommended Value)
RRESET
Overcurrent Reset Resistance
7.5
MΩ
LPWARN Output
LP Warn Threshold
2.55
2.65
280
120
0.3
0.3
6
2.75
560
280
0.4
V
ns
ns
V
TR
CLOAD = 100pF, 10% to 90% of PACK+
CLOAD = 100pF, 10% to 90% of PACK+
ISINK = 200µA, VUV < VPACK+ < VTLO
ISOURCE = 200µA, VTLO < VPACK+ < VUV
TF
VHIGH (VPACK+ –VLPWARN
)
VLOW
0.4
V
Measure Delay
OVUVB Output
TR
ms
CLOAD = 100pF, Hi Z to 90% of PACK+
CLOAD = 100pF, Hi Z to 10% of PACK+
ISOURCE = 200µA, VPACK+ ≥ VOV
ISINK = 200µA, VPACK+ ≤ VUV
Output Tristated
280
140
0.3
0.3
10
560
280
0.4
0.4
ns
ns
V
TF
VHIGH (VPACK+ – VOVUVB
VLOW
)
V
ZOUT
MΩ
ms
Measure Delay
18
CE Input
ISINK
Note 1: Other threshold voltages are available.
150
nA
3
UCC3958 -1/-2/-3/-4
PIN DESCRIPTIONS
(nominally 2.65V). This pin will stay high until the
BNEG: Connect the negative terminal of the battery to
detected battery voltage goes above V
condition is declared.
, or UV
these pins.
TLO
CBPS: This power supply bypass pin is connected to
PACK+ through an internal 10k resistor. An external
capacitor must be connected between this pin and
BNEG. This capacitor functions as temporary charge
storage for high current conditions (short circuit).
Minimum capacitor value is 0.15µF. This value should be
increased if the CDLY cap is used.
OVUVB: This pin is an overvoltage/undervoltage
condition indicator. Under normal operating conditions
this pin is tristated. When an overvoltage (OV) state is
detected, this pin is pulled high. When undervoltage (UV)
condition is detected, this pin is pulled low.
PACK+: Connect to the positive terminal of the battery.
This pin is available to the user.
CDLY: Delay control pin for the short circuit protection
feature. A capacitor connected between this pin and the
BNEG pin will increase the time delay for sensing an
over current condition. This adjustment may be useful in
those applications where high peak load currents may
momentarily exceed the protection circuit’s threshold and
interruption of the battery current would be undesirable.
The nominal delay time is set internally at 350µs
PACK-: These pins should be connected to the negative
terminal of the battery pack (negative terminal available
to the user). The internal FET switch connects this
terminal to the BNEG terminal to give the battery pack
user appropriate access to the battery. In an overcharged
state, only discharge current is permitted. In an
overdischarged state, only charge current is permitted.
CEB: Chip Enable Bar. This pin is pulled low (wrt BNEG)
by a 100nA current source. In order to disable the IC, the
user must pull this pin high to PACK+.
SUB: Do not connect. These pins must be electrically
isolated from all other pins. These pins may be soldered
to isolated copper pads for heatsinking. This will improve
heat transfer, which may be necessary at high load
currents.
LPWARN: Low Power Warning Indicator. This pin is
forced high when the battery voltage drops below V
TLO
APPLICATION INFORMATION
Battery Voltage Monitoring
If the cell voltage exceeds the Over Voltage threshold for
two consecutive samples, charging is disabled, however
discharge current is still allowed. This feature of the IC is
explained further in the section on Controlled Charge/
Discharge Mode.
The battery cell voltage is sampled every 12ms by con-
necting a resistor divider across it and comparing the re-
sulting voltage to a precision internal reference voltage.
Under normal conditions (cell voltage is below Over Volt-
age threshold and above Under Voltage threshold), the
UCC3958 consumes approximately 7µA of current and
0.10
0.08
0.06
0.04
0.02
0.00
the internal MOSFET is turned on with an R
of
DSON
50mΩ. The UCC3958 contains an on-chip Charge Pump
to ensure that the internal MOSFET gate is driven high
for complete turn-on, reducing power losses. The charge
pump switches and capacitors are all internal.
When the cell voltage falls below the Under Voltage
threshold for two consecutive samples, the IC discon-
nects the load from the battery pack and enters a super
low power mode (nominally 1µA). The pack will remain
in this state until it detects the application of a charger, at
which point controlled charging is enabled. The require-
ment of two consecutive readings below the UV thresh-
old filters out momentary drops in cell voltage due to load
transients, preventing nuisance trips.
3.0
3.4
3.8
4.2
2.6
CELL VOLTAGE
Figure 1. Typical Rdson vs Cell Voltage (DP Package
Pin 7 to Pin 10, at 25°C, 1 Amp Load)
4
UCC3958 -1/-2/-3/-4
APPLICATION INFORMATION (continued)
larger load capacitors by connecting an external delay
capacitor from the CDLY pin to one of the BNEG pins.
Once an Over Current condition has been declared, the
internal MOSFET turns off. The only way to return the
pack to normal operation is to remove the load by un-
plugging the pack from the system. The overcurrent is re-
set when an internal pull down brings PACK– to within
less than 0.05V above BNEG. At this point, the pack re-
turns to its normal state of operation. A capacitor on the
CBPS pin provides momentary holdup for the UCC3958
to assure proper operation in the event that a hard short
suddenly pulls the cell voltage below the minimum oper-
ating voltage. This cap value can be 0.15µF if the op-
tional CDLY capacitor is not used. An internal 10k
resistor buffers the bypass capacitor from the Li-Ion cell.
Figure 2. Typical OV Leakage Current with Runaway
Charger at 25°C
Over Current Monitoring and Protection
Discharge current is continuously monitored via an inter-
nal sense resistor. In the event of excessive current, an
Over Current condition is declared if the high current
state persists for over 350µs. This delay allows for charg-
ing of the system bypass capacitors without tripping the
overcurrent. A delay of 350µs guarantees that the pack
can charge up to 680µF without declaring an Over Cur-
rent condition. The delay may be extended to charge
Figure 4. Typical Overcurrent Delay Time vs CDLY
System Status Indicators
The UCC3958 provides several convenient system moni-
toring signals. The first one is the Low Power Warning.
This output goes high when the cell voltage is less than
300mV above the Under Voltage Threshold. It signals
the system that the battery is getting close to its dis-
charge limit.
The second monitoring signal is a tri-statable OV/UV out-
put. Under normal operations conditions, this signal is
tri-stated. When an Over Voltage condition is declared,
the output is pulled high. When an Under Voltage condi-
tion is declared, the output is pulled low. This signal is
especially useful during test, allowing easy verification of
the OV and UV thresholds. These outputs are with re-
spect to BNEG.
UDG-98051
Figure 3. State Diagram
5
UCC3958 -1/-2/-3/-4
APPLICATION INFORMATION (continued)
0.2Amp 1.0Amp 2.0Amp
Controlled Charge/Discharge Mode
When the chip senses an over-voltage condition, it pre-
vents any additional charging, but allows discharge. This
is accomplished by activating a linear control loop which
controls the gate of the MOSFET based on the differen-
tial voltage across its drain to source terminals. The lin-
ear loop attempts to regulate the differential voltage
across the MOSFET to 100mV. When a light load is ap-
plied to the part, the loop adjusts the impedance of the
MOSFET to maintain 100mV across it. As the load in-
creases, the impedance of the MOSFET is decreased to
maintain the 100mV control. At heavy loads (still below
“over-current” limit level), the loop will not maintain regu-
lation and will drive the gate of the MOSFET to the bat-
tery voltage (not the charge-pump output voltage). The
700
600
500
400
300
200
100
0
2.10
2.20
2.30
2.40
2.00
MOSFET R
higher than R
in the over-voltage state will be slightly
DSON
Figure 5. Typical MOSFET Voltate Drop During
Charge in UV vs. Cell Voltage.
during normal operation. The voltage
DSON
drop (and associated power loss) across the internal
MOSFET in this mode of operation is lower than the typi-
cal solution of two external back-to-back MOSFETs,
where the body diode is conducting.
UDG-97152
Figure 6. SIngle Cell Lithium-Ion Battery Protector IC Application Diagram
6
UCC3958 -1/-2/-3/-4
APPLICATION INFORMATION (continued)
When the chip senses an under-voltage condition, it dis- lows charging current into the battery. This linear control
connects the load from the battery pack and shuts itself mode of operation is in effect until the battery voltage
down to minimize current drain from the battery. Several reaches a level 300mV above the under-voltage thresh-
circuits remain powered and will detect placement of the old, at which time normal operation is resumed.
battery pack into a charger. Once the charger presence
is detected, the linear loop is activated and the chip al-
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