UCD9090-Q1_技术文档

UCD9090-Q1

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ZHCSAW9A –JANUARY 2013–REVISED FEBRUARY 2013

可支持高效配置和电源接口 (ACPI) 的 10 轨电源排序器和监视器

查询样品: UCD9090-Q1

1

特性

说明

UCD9090-Q1 是一款 10 电压轨 PMBus 和 I²C 可寻址

2

•

符合汽车应用要求

具有符合 AEC-Q100 的下列结果：

电源排序器和监视器。该器件集成了一个 12 位

ADC，此 ADC 可监视多达 10 个电源电压输入。 23

个通用输入输出 (GPIO) 引脚可用于电源使能、加电复

位信号、外部中断、级联或其他系统功能。其中的 10

个 GPIO 引脚提供 PWM 功能。利用这些引

脚，UCD9090-Q1 可支持裕度调节及通用 PWM 功

能。

•

–

器件温度 1 级：-40°C 至 125°C 的环境运行温

度范围

器件人体模型 (HBM) 静电放电 (ESD) 分类等级

H2

器件充电器件模型 (CDM) ESD 分类等级 C4B

•

监视及排序 10 个电压轨

–

所有电压轨每 400μs 采样一次

用户可通过使用由引脚选择的电压轨状态特性来实现特

定电源状态。这个特性能够通过使用最多 3 个 GPI 来

启用或禁用电压轨。对于执行系统低功耗模式及用于

硬件设备的高级配置和电源接口 (ACPI) 技术规范而

言，这一特性是很有用处的。

具有 2.5V，0.5% 内部 V_REF的 12 位模数转换

器 (ADC)

–

排序基于时间，电压轨及引脚相关性

每个监视器有 4 个可编程欠压及过压阈值

•

每个监视器可提供非易失性误差及峰值日志记录

（多达30个故障详细条目）

德州仪器 (TI) 的 Fusion Digital Power™ 设计工具软件

在器件配置中提供帮助。这款基于 PC 的图形用户界

面 (GUI) 提供了一种用于配置，存储和监视所有系统

操作参数的直观界面。

针对 10 个电压轨的闭环裕度调节能力

–

裕度输出可调节轨电压以与用户规定的裕度门限

相匹配

•

可编程安全装置定时器及系统复位

灵活的数字 I/O 配置

12V

12V OUT

TEMP12V

TEMP IC

3.3V

Supply

I12V

INA196

可利用引脚选择电压轨状态

多相位脉宽调制 (PWM) 时钟发生器

12V OUT

GPIO

VIN

3.3V OUT

VMON

VOUT

–

时钟频率从 15.259kHz 到 125MHz

/EN

DC-DC 1

3.3V OUT

VFB

VMON

–

能够为同步开关模式电源配置独立的时钟输出

JTAG，I²C，SMBus 和 PMBus™ 接口

1.8V OUT

0.8V OUT

I0.8V

•

VIN

1.8V OUT

/EN VOUT

GPIO

TEMP0.8V

I12V

LDO1

应用范围

TEMP12V

TEMP0.8V

任何需要对多个电源轨进行排序和监视的系统

TEMP IC

VIN

0.8V OUT

VOUT

UCD9090

/EN

GPIO

PWM

WDI from main

processor

DC-DC

2

GPIO

VFB

WDO

I0.8V

INA196

POWER_GOOD

Vmarg

2MHz

WARN_OC_0.8V_

OR_12V

Closed Loop

Margining

SYSTEM RESET

OTHER

SEQUENCER DONE

(CASCADE INPUT)

I2C/

PMBUS

JTAG

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PMBus, Fusion Digital Power are trademarks of Texas Instruments.

2

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLVSBH9

UCD9090-Q1

ZHCSAW9A –JANUARY 2013–REVISED FEBRUARY 2013

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

FUNCTIONAL BLOCK DIAGRAM

JTAG

Or

GPIO

General Purpose I/O

(GPIO)

I2C/PMBus

Comparators

Rail Enables (10 max)

6

Digital Outputs (10 max)

Digital Inputs (8 max)

Monitor

Inputs

23

SEQUENCING ENGINE

11

12-bit

200ksps,

Multi-phase PWM (8 max)

Margining Outputs (10 max)

ADC

(0.5% Int. Ref)

FLASH Memory

BOOLEAN

Logic Builder

User Data, Fault

and Peak Logging

48-pin QFN

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

VALUE

UNIT

V

Voltage applied at V33D to DV_SS

Voltage applied at V33A to AV_SS

Voltage applied to any other pin⁽²⁾

–0.3 to 3.8

V

–0.3 to (V33A + 0.3)

V

Storage temperature (T_stg

)

–40 to 150

2.5

°C

kV

V

Human-body model (HBM)

ESD rating

Charged-device model (CDM)

750

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS

.

THERMAL INFORMATION

UCD9090-Q1

THERMAL METRIC⁽¹⁾

UNITS

RGZ (48 PINS)

θ_JA

Junction-to-ambient thermal resistance

25

8.9

5.5

0.3

1.5

1.7

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

θ_JCbot

(1) 有关传统和新的热度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。

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spacer

RECOMMENDED OPERATING CONDITIONS

MIN

3

NOM

MAX

3.6

UNIT

V

Supply voltage during operation (V_33D, V_33DIO, V_33A

)

3.3

Operating free-air temperature range, T_A

–40

125

°C

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

SUPPLY CURRENT

I_V33A

V_V33A= 3.3 V

V_V33DIO= 3.3 V

V_V33D= 3.3 V

8

2

mA

I_V33DIO

Supply current⁽¹⁾

I_V33D

ANALOG INPUTS (MON1–MON13)

40

V_V33D= 3.3 V, storing configuration parameters in

flash memory

50

mA

V_MON

Input voltage range

MON1–MON10

MON11

0

0.2

–4

2.5

4

V

INL

ADC integral nonlinearity

ADC differential nonlinearity

Input leakage current

Input offset current

LSB

nA

DNL

I_lkg

–2

2

3 V applied to pin

100

5

I_OFFSET

1-kΩ source impedance

MON1–MON10, ground reference

MON11, ground reference

–5

8

μA

MΩ

MΩ

pF

R_IN

Input impedance

0.5

1.5

3

C_IN

Input capacitance

10

t_CONVERT

ADC sample period

12 voltages sampled, 3.89 μs/sample

0°C to 125°C

400

μs

ADC 2.5 V, internal reference accuracy

–0.5%

–1%

0.5%

1%

V_REF

–40°C to 125°C

ANALOG INPUT (PMBUS_ADDRx)

I_BIAS

Bias current for PMBus Addr pins

9

11

μA

V

V_{ADDR_OPEN}

V_{ADDR_SHORT}

Voltage – open pin

PMBUS_ADDR0, PMBUS_ADDR1 open

2.26

Voltage – shorted pin

PMBUS_ADDR0, PMBUS_ADDR1 short to ground

0.124

V

(1) Device programmed but not configured, and no peripherals connected to any pins, are the basis for typical supply current values.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

DIGITAL INPUTS AND OUTPUTS

V_OL

Low-level output voltage

I_OL= 6 mA⁽²⁾, V_33DIO= 3 V

I_OH= –6 mA⁽³⁾, V_33DIO= 3 V

Dgnd +

0.3

V

V_OH

High-level output voltage

V_33DIO

–0.6

V_IH

V_IL

High-level input voltage

Low-level input voltage

V_33DIO= 3 V

2.1

3.6

1.4

V

V_33DIO= 3.5 V

MARGINING OUTPUTS

f_{PWM_FREQ}MARGINING-PWM frequency

FPWM1-8

PWM1-2

15.260

0.001

0%

125,000

7800

kHz

DUTY_PWM

MARGINING-PWM duty-cycle range

100%

SYSTEM PERFORMANCE

V_DDSlew

V_RESET

Minimum V_DDslew rate

V_DDslew rate between 2.3 V and 2.9 V

For power-on reset (POR)

0.25

V/ms

V

Supply voltage at which device comes

out of reset

2.4

t_RESET

f_(PCLK)

t_retention

Low-pulse duration needed at RESET pin To reset device during normal operation

2

240

100

μs

Internal oscillator frequency

T_A= 125°C, T_A= 25°C

T_J= 25°C

250

260

MHz

Years

Retention of configuration parameters

Number of nonvolatile erase-and-write

cycles

Write_Cycles

T_J= 25°C

20

K cycles

(2) The maximum total current, I_OLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.

(3) The maximum total current, I_OHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.

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PMBus, SMBus, I²C

The following section shows the timing characteristics and timing diagram for the communications interface that

supports I²C, SMBus, and PMBus.

I²C, SMBus, PMBus TIMING REQUIREMENTS

T_A= –40°C to 85°C, 3 V < V_DD< 3.6 V; typical values at T_A= 25°C and V_CC= 2.5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Slave mode, SMBC 50% duty cycle

Slave mode, SCL 50% duty cycle

MIN

10

TYP

MAX UNIT

f_(SMB)

SMBus or PMBus operating frequency

I²C operating frequency

Bus free time between start and stop

Hold time after (repeated) start

Repeated-start setup time

Stop setup time

400

kHz

μs

f_(I2C)

10

t_(BUF)

4.7

0.26

0

t_(HD:STA)

t_(SU:STA)

t_(SU:STO)

t_(HD:DAT)

t_(SU:DAT)

t_(TIMEOUT)

t_(LOW)

μs

Data hold time

Receive mode

See⁽¹⁾

ns

Data setup time

50

ns

Error signal or detect

35

ms

μs

Clock low period

0.5

(2)

t_(HIGH)

t_(LOW:SEXT)

t_f

Clock high period

See

0.26

50

25

μs

(3)

Cumulative clock-low slave-extend time

Clock or data fall time

See

ms

ns

(4)

See

120

(5)

t_r

Clock or data rise time

See

ns

(1) The device times out when any clock low exceeds t_(TIMEOUT)

.

(2) t_(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This

specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).

(3) t_(LOW:SEXT)is the cumulative time a slave device can extend the clock cycles in one message from initial start to the stop.

(4) Fall time t_f= 0.9 VDD to (V_ILMAX – 0.15)

(5) Rise time t_r= (V_ILMAX – 0.15) to (V_IHMIN + 0.15)

Figure 1. Timing Diagram for I²C and SMBus

Start

Stop

T

LOW:SEXT

T

LOW:MEXT

PMB_Clk

Clk

ACK

Clk

ACK

PMB_Data

Figure 2. Bus Timing in Extended Mode

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ZHCSAW9A –JANUARY 2013–REVISED FEBRUARY 2013

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DEVICE INFORMATION

Figure 3. UCD9090-Q1 PIN ASSIGNMENT

33 34 35

27

28

29

30

31

MON1

MON2

MON3

MON4

MON5

MON6

MON7

MON8

MON9

MON10

MON11

TCK/GPIO18

TDO/GPIO19

TDI/GPIO20

TMS/GPIO21

TRST

1

2

38

39

40

41

42

45

46

48

37

36

AVSS1

1

MON1

GPIO1

GPIO2

4

35

BPCAP

2

3

MON2

5

6

34

V33A

RESET

GPIO3

33

V33D

4

5

GPIO1

GPIO4

7

UCD9090

32

31

30

29

28

DVSS

TRST

GPIO2

GPIO3

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

18

21

24

25

26

6

UCD9090

7

TMS/GPIO21

TDI/GPIO20

GPIO4

8

PMBUS_CLK

PMBUS_DATA

FPWM1/GPIO5

FPWM2/GPIO6

PMBUS_CLK

8

9

TDO/GPIO19

9

PMBUS_DATA

PMBUS_ALERT

PMBUS_CNTRL

PMBUS_ADDR0

PMBUS_ADDR1

27 TCK/GPIO18

10

11

12

19

20

44

43

26

GPIO17

FPWM1/GPIO5

FPWM2/GPIO6

FPWM3/GPIO7

FPWM4/GPIO8

FPWM5/GPIO9

FPWM6/GPIO10

FPWM7/GPIO11

FPWM8/GPIO12

10

11

12

13

14

15

16

17

25

GPIO16

FPWM3/GPIO7

PWM1/GPI1

PWM2/GPI2

22

23

RESET

3

32 36 47

Table 1. PIN FUNCTIONS

PIN NAME

PIN NO.

I/O TYPE DESCRIPTION

ANALOG MONITOR INPUTS

MON1

MON2

MON3

MON4

MON5

MON6

MON7

MON8

MON9

MON10

MON11

GPIO

1

I

Analog input (0 V–2.5 V)

2

Analog input (0 V–2.5 V)

Analog input (0.2 V–2.5 V)

38

39

40

41

42

45

46

48

37

GPIO1

4

I/O

General-purpose discrete I/O

6

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Table 1. PIN FUNCTIONS (continued)

PIN NAME

GPIO2

PIN NO.

I/O TYPE DESCRIPTION

5

I/O

General-purpose discrete I/O

GPIO3

6

GPIO4

7

GPIO13

18

21

24

25

26

GPIO14

GPIO15

GPIO16

GPIO17

PWM OUTPUTS

FPWM1/GPIO5

FPWM2/GPIO6

FPWM3/GPIO7

FPWM4/GPIO8

FPWM5/GPIO9

FPWM6/GPIO10

FPWM7/GPIO11

FPWM8/GPIO12

PWM1/GPI1

PWM2/GPI2

10

11

12

13

14

15

16

17

22

23

I/O/PWM

I/PWM

PWM (15.259 kHz to 125 MHz) or GPIO

PWM (0.93 Hz to 7.8125 MHz) or GPI

I/PWM

PMBus COMM INTERFACE

PMBUS_CLK

PMBUS_DATA

PMBUS_ALERT

PMBUS_CNTRL

PMBUS_ADDR0

PMBUS_ADDR1

JTAG

8

I/O

PMBus clock (must have pullup to 3.3 V)

9

I/O

PMBus data (must have pullup to 3.3 V)

19

20

44

43

O

I

PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)

PMBus control

I

PMBus analog address input. Least-significant address bit

PMBus analog address input. Most-significant address bit

I

TCK/GPIO18

TDO/GPIO19

TDI/GPIO20

TMS/GPIO21

TRST

27

28

29

30

31

I/O

I

Test clock or GPIO

Test data out or GPIO

Test data in (tie to V_ddwith 10-kΩ resistor) or GPIO

Test mode select (tie to V_ddwith 10-kΩ resistor) or GPIO

Test reset – tie to ground with 10-kΩ resistor

INPUT POWER AND GROUNDS

RESET

V33A

3

Active-low device reset input. Hold low for at least 2 μs to reset the device.

Analog 3.3-V supply. See the Layout Guidelines section.

Digital core 3.3-V supply. See the Layout Guidelines section.

1.8-V bypass capacitor. See the Layout Guidelines section.

Analog ground

34

33

35

36

47

32

NA

V33D

BPCap

AVSS1

AVSS2

DVSS

Analog ground

Digital ground

QFP ground pad

Thermal pad – tie to ground plane

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FUNCTIONAL DESCRIPTION

TI FUSION GUI

The Texas Instruments Fusion Digital Power Designer is available for device configuration. This PC-based

graphical user interface (GUI) offers an intuitive I²C or PMBus interface to the device. It allows the design

engineer to configure the system operating parameters for the application without directly using PMBus

commands, store the configuration to on-chip nonvolatile memory, and observe system status (voltage, and so

forth). The data sheet references Fusion Digital Power Designer throughout as Fusion GUI and many sections

include screenshots. Download the Fusion GUI from www.ti.com.

PMBUS INTERFACE

The PMBus is a serial interface specifically designed to support power management. Its basis is on the SMBus

interface, built on the I²C physical specification. The UCD9090-Q1 supports revision 1.1 of the PMBus standard.

Wherever possible, standard PMBus commands support the function of the device. For unique features of the

UCD9090-Q1, defined MFR_SPECIFIC commands configure or activate those features. The UCD90xxx

Sequencer and System Health Controller PMBUS Command Reference (SLVU352) defines these commands.

One can find the most-current UCD90xxx PMBus™ Command Reference within the TI Fusion Digital Power

Designer software via the Help Menu (Help, Documentation & Help Center, Sequencers tab, Documentation

section).

This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power

System Management Protocol Specification Part II – Command Language, Revision 1.1, dated 5 February 2007.

The Power Management Bus Implementers Forum publishes the specification, which is available from

www.pmbus.org.

The UCD9090-Q1 is PMBus compliant, in accordance with the Compliance section of the PMBus specification.

The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT

function. The hardware can support either 100-kHz or 400-kHz PMBus operation.

THEORY OF OPERATION

Modern electronic systems often use numerous microcontrollers, DSPs, FPGAs, and ASICs. Each device can

have multiple supply voltages to power the core processor, analog-to-digital converter, or I/O. These devices are

typically sensitive to the order and timing of how the voltages are sequenced on and off. The UCD9090-Q1 can

sequence supply voltages to prevent malfunctions, intermittent operation, or device damage caused by improper

power up or power down. Appropriate handling of under- and overvoltage faults can extend system life and

improve long-term reliability. The UCD9090-Q1 stores power supply faults to on-chip nonvolatile flash memory

for aid in system failure analysis.

Four-corner testing during system verification can improve system reliability. During four-corner testing, the

system operates at the minimum and maximum expected ambient temperature and with each power supply set

to the minimum and maximum output voltage, commonly referred to as margining. One use of the UCD9090-Q1

is to implement accurate closed-loop margining of up to 10 power supplies.

The UCD9090-Q1 10-rail sequencer can be used in a PMBus- or pin-based control environment. The TI Fusion

GUI provides a powerful but simple interface for configuring sequencing solutions for systems having between

one and 10 power supplies by using 10 analog voltage-monitor inputs, two GPIs, and 21 highly configurable

GPIOs. A rail includes voltage, a power-supply enable, and a margining output. The rail definition must include at

least one of these. After defining how the power-supply rails should operate in a particular system, the user can

select analog input pins and GPIOs to monitor and enable each supply (Figure 4).

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Figure 4. Fusion GUI Pin-Assignment Tab

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After configuring the pins, select other key monitoring and sequencing criteria for each rail from the Vout Config

tab (Figure 5):

•

Nominal operating voltage (Vout)

Undervoltage (UV) and overvoltage (OV) warning and fault limits

Margin-low and margin-high values

Power-good-on and power-good-off limits

PMBus or pin-based sequencing control (On/Off Config)

Rails and GPIs for sequence-on dependencies

Rails and GPIs for sequence-off dependencies

Turn-on and turn-off delay timing

Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled

or disabled

•

Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)

Figure 5. Fusion GUI V_OUT-Config Tab

The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage

of a rail and also update all of the other limits associated with that rail according to the percentages shown to the

right of each entry.

The plot in the upper left section of Figure 5 shows a simulation of the overall sequence-on and sequence-off

configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good-on and power-

good-off voltages, and any timing dependencies between the rails.

After a rail voltage has reached its POWER_GOOD_ON voltage and is in regulation, the device compares it

against two UV and two OV thresholds in order to determine if it has exceeded a warning or fault limit. In case of

a fault detection, the UCD9090-Q1 responds based on a variety of flexible, user-configured options. Faults can

cause rails to restart, shut down immediately, sequence off using turnoff delay times, or shut down a group of

rails and sequence them back on. Different types of faults can result in different responses.

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The user selects fault responses, along with a number of other parameters including user-specific manufacturing

information and external scaling and offset values, in the different tabs within the Configure function of the Fusion

GUI. Once the configuration satisfies the user requirements, a user can write it to device SRAM if an I²C or

PMBus connects the Fusion GUI to a UCD9090-Q1. SRAM contents can then be stored to data flash memory so

that the configuration remains in the device after a reset or power cycle.

The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard,

for viewing and controlling device and system status.

Figure 6. Fusion GUI Monitor Page

The UCD9090-Q1 also has status registers for each rail and the capability to log faults to flash memory for use in

system troubleshooting. This is helpful in the event of a power-supply or system failure. The status registers

(Figure 7) and the fault log (Figure 8) are available in the Fusion GUI. See the UCD90xxx Sequencer and

System Health Controller PMBus Command Reference (SLVU352) and the PMBus Specification for detailed

descriptions of each status register and supported PMBus commands.

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Figure 7. Fusion GUI Rail-Status Register

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Figure 8. Fusion GUI Flash-Error Log (Logged Faults)

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POWER-SUPPLY SEQUENCING

The UCD9090-Q1 can control the turnon and turnoff sequencing of up to 10 voltage rails by using a GPIO to set

a power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a

sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I²C

serial bus. In pin-based designs, one can also use the PMBUS_CNTRL pin to sequence-on and sequence-off.

The auto-enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on starts at

power up after each rail has its dependencies and time delays met. Consider a rail to be on or within regulation

when the measured voltage for that rail crosses the power-good-on (POWER_GOOD_ON ⁽¹⁾) limit. The rail is still

in regulation until the voltage drops below power-good-off (POWER_GOOD_OFF). Without having the voltage

monitoring set for a given rail, that rail is considered ON if an OPERATION command, PMBUS CNTRL pin, or

auto-enable commands it on and (TON_DELAY + TON_MAX_FAULT_LIMIT) time passes. Consider a rail OFF

when commanded OFF and (TOFF_DELAY + TOFF_MAX_WARN_LIMIT) time passes.

Turnon Sequencing

The UCD9090-Q1 supports the following sequence-on options for each rail:

•

Monitor only – do not sequence-on

Fixed delay time (TON_DELAY) after an OPERATION command to turn on

Fixed delay time after assertion of the PMBUS_CNTRL pin

Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON)

Fixed time after a designated GPI has reached a user-specified state

Any combination of the previous options

The maximum TON_DELAY time is 3276 ms.

Turnoff Sequencing

The UCD9090-Q1 supports the following sequence-off options for each rail:

•

Monitor only – do not sequence-off

Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off

Fixed delay time after deassertion of the PMBUS_CNTRL pin

Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF)

Fixed delay time in response to an undervoltage, overvoltage, or maximum turn-on fault on the rail

Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail

Fixed delay time in response to a GPI reaching a user-specified state

Any combination of the previous options

The maximum TOFF_DELAY time is 3276 ms.

Rail 1 and Rail 2 are both sequenced “ON”

and “OFF” by the PMBUS_CNTRL pin

only

PMBUS_CNTRL PIN

TON_DELAY[1]

TOFF_DELAY[1]

Rail 2 has Rail 1 as an “ON” dependency

Rail 1 has Rail 2 as an “OFF” dependency

RAIL 1 EN

POWER_GOOD_ON[1]

POWER_GOOD_OFF[1]

RAIL 1 VOLTAGE

TON_DELAY[2]

TOFF_DELAY[2]

RAIL 2 EN

RAIL 2 VOLTAGE

TON_MAX_FAULT_LIMIT[2]

TOFF_MAX_WARN_LIMIT[2]

Figure 9. Sequence-On and Sequence-Off Timing

(1) In this document, configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx

Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first

time the parameter appears.

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Sequencing Configuration Options

In addition to the turnon and turnoff sequencing options, the user can configure the time between when a rail is

enabled and when the monitored rail voltage must reach its power-good-on setting by using maximum turnon

(TON_MAX_FAULT_LIMIT). Maximum turnon can be set in 1-ms increments. A value of 0 ms means that there

is no limit and the device can try to turn on the output voltage indefinitely.

Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies and

user-defined delay times. Configure a sequenced shutdown by selecting the appropriate rail and GPI

dependencies and turnoff delay (TOFF_DELAY) times for each rail. The turnoff delay times begin when the

PMBUS_CNTRL pin deasserts, when using the PMBus OPERATION command to give a soft-stop command, or

when a fault occurs on a rail that has other rails set as fault-shutdown slaves.

Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD9090-

Q1s, it is possible for each controller to be both a master and a slave to another controller.

PIN-SELECTED RAIL STATES

This feature allows the use of up to three GPIs to enable or disable any rail. This is useful for implementing

system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used

for operating system-directed power management in servers and PCs. In up to 8 system states, the power

system designer can define which rails are on and which rails are off. If presentation of a new state on the input

pins requires a rail to change state, it does so with regard to its sequence-on or sequence-off dependencies.

This function causing a rail to change its state results in a modification of the OPERATION command. This

requires setting ON_OFF_CONFIG to use the OPERATION command for a given rail for this function to have

any effect on the rail state. The device uses the first three pins configured with the GPI_CONFIG command to

select one of eight system states. After a device reset, the sampling of these pins determines the system state,

which if enabled is the basis for updating each rail state. When selecting a new system state, changes to the

status of the GPIs must not take longer than 1 microsecond. See the UCD90xxx Sequencer and System Health

Controller PMBus Command Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES.

Table 2. GPI Selection of System States

System

State

GPI 2 State

GPI 1 State

GPI 0 State

Not asserted

Asserted

Not asserted

Asserted

Not asserted

Asserted

0

1

2

3

4

5

6

7

Not asserted

Asserted

Not asserted

Asserted

Not asserted

Asserted

Not asserted

Asserted

MONITORING

The UCD9090-Q1 has 11 monitor input pins (MONx) that are multiplexed into a 12-bit ADC that has a 2.5-V

reference. Configuring the monitor pins is possible so that they can measure voltage signals to report voltage-,

current-, and temperature-type measurements. A single rail can include all three measurement types, each

monitored on a separate MON pin. If a rail has both voltage and current assigned to it, then the user can

calculate power for the rail. Digital filtering applied to each MON input depends on the type of signal. Voltage

inputs have no filtering. Current and temperature inputs have a low-pass filter.

VOLTAGE MONITORING

The UCD9090-Q1 can monitor up to 12 voltages using the analog input pins. The input voltage range is 0 V–2.5

V for all MONx inputs except MON11 (pin 37), which has a range of 0.2 V–2.5 V. Any voltage between 0 V and

0.2 V on these pins reads as 0.2 V. Use external resistors to attenuate voltages higher than 2.5 V.

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The ADC operates continuously, requiring 3.89 μs to convert a single analog input. The sequencing and

monitoring algorithm samples each rail every 400 μs. The maximum source impedance of any sampled voltage

should be less than 4 kΩ. The source impedance limit is particularly important when using a resistor-divider

network to lower the voltage applied to the analog input pins.

Configure MON1–MON6 using digital hardware comparators, if desired, to achieve faster fault responses. Each

hardware comparator has four thresholds [two UV (Fault and Warning) and two OV (Fault and Warning)]. The

hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the ADC inputs)

and can disable rails or assert GPOs. The only fault response available for the hardware comparators is to shut

down immediately.

The ADC uses an internal 2.5-V reference. The ADC reference has a tolerance of ±0.5% between 0°C and

125°C and a tolerance of ±1% between –40°C and 125°C. Monitoring voltages higher than 2.5 V requires an

external voltage divider. Enter the nominal rail voltage and the external scale factor into the Fusion GUI to report

the actual voltage being monitored instead of the ADC input voltage. The nominal voltage sets the range and

precision of the reported voltage according to Table 3.

MON1 – MON6

Fast Digital

Comparators

MON1

12-bit

SAR ADC

200ksps

M

U

X

MON2

.

MON13

Analog

Inputs

(12)

Glitch

Filter

MON1 – MON13

Internal

2.5Vref

0.5%

Figure 10. Voltage Monitoring Block Diagram

Table 3. Voltage Range and Resolution

VOLTAGE RANGE

(Volts)

RESOLUTION

(Millivolts)

0 to 127.99609

0 to 63.99805

0 to 31.99902

0 to 15.99951

0 to 7.99976

0 to 3.99988

0 to 1.99994

0 to 0.99997

3.90625

1.95313

0.97656

0.48824

0.24414

0.12207

0.06104

0.03052

Although the reporting of monitor results can have a resolution of about 15 μV, the 2.5-V reference and the 12-bit

ADC determine the real conversion resolution of 610 μV.

CURRENT MONITORING

Monitor current by using the analog inputs. Use external circuitry, see Figure 11, in order to convert the current to

a voltage within the range of the UCD9090-Q1 MONx input in use.

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For a monitor input configured as a current, a sliding-average digital filter smooths the measurements. The

device takes a current measurement for one rail every 200 μs. If programmed to support 10 rails (with or without

monitoring current at all rails), then the current measurement for each rail occurs every 2 ms. The current

calculation comprises a sliding average using the last four measurements. The filter reduces the probability of

false fault detections, and introduces a small delay to the current reading. If a rail definition includes a voltage

monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches

POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after

TON_DELAY.

The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external

currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit;

IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the

undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference

contains a detailed description of how to use MBus commands to implement current-fault responses.

IOUT_CAL_GAIN is a PMBus command that allows the user to enter the scale factor of an external current

sensor and any amplifiers or attenuators between the current sensor and the MON pin in milliohms.

IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus

commands allows the reporting of current in amperes. The following example using the INA196 would require

programming IOUT_CAL_GAIN to Rsense(mΩ) × 20.

UCD9090

INA196

MONx

VOUT

Vin+

Vin-

Rsense

AVSS1

GND

V+

3.3V

Gain = 20V/V

Figure 11. Current Monitoring Circuit Example Using the INA196

REMOTE TEMPERATURE MONITORING AND INTERNAL TEMPERATURE SENSOR

The UCD9090-Q1 has support for internal and remote temperature sensing. The internal temperature sensor

requires no calibration and can report the device temperature via the PMBus interface. The remote temperature

sensor can report the remote temperature by using a configurable gain and offset for the type of sensor being

used in the application, such as a linear temperature sensor (LTS) connected to the analog inputs.

Use external circuitry to convert the temperature to a voltage within the range of the UCD9090-Q1 MONx input

being used.

If an input is configured as a temperature, the measurements are smoothed by a sliding-average digital filter. The

temperature for one rail is measured every 100 ms. If programmed to support 10 rails (with or without monitoring

temperature at all rails), then the current measurement for each rail temperature occurs every 1 s. The

temperature calculation comprises a sliding average using the last 16 measurements. The filter reduces the

probability of false fault detections, and introduces a small delay to the temperature reading. A silicon diode

sensor with an accuracy of ±5°C, monitored using the ADC, measures the internal device temperature.

Temperature monitoring begins immediately after reset and initialization.

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The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1,

which reads the internal temperature; READ_TEMPERATURE_2, which reads external temperatures; and

OT_FAULT_LIMIT and OT_WARN_LIMIT, which set the overtemperature fault and warning limit. The UCD90xxx

Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how to

use PMBus commands to implement temperature-fault responses.

TEMPERATURE_CAL_GAIN is a PMBus command that allows the user to enter the scale factor of an external

temperature sensor and any amplifiers or attenuators between the temperature sensor and the MON pin in °C/V.

TEMPERATURE_CAL_OFFSET is the temperature that results in 0 V at the MON pin. The combination of these

PMBus commands allows the reporting of temperature in degrees Celsius.

UCD9090

TMP20

MONx

VOUT

AVSS1

GND

V+

3.3V

Vout = -11.67mV/°C x T + 1.8583

at -40°C < T < 85°C

Figure 12. Remote Temperature Monitoring Circuit Example using the TMP20

TEMPERATURE BY HOST INPUT

If the host system has the option of not using the temperature-sensing capability of the UCD9090-Q1, it can still

provide the desired temperature to the UCD9090-Q1 through the PMBus. The host may have temperature

measurements available through I²C- or SPI-interfaced temperature sensors. The UCD9090-Q1 would use the

temperature given by the host in place of an external temperature measurement for a given rail. The temperature

provided by the host would still be used for detecting overtemperature warnings or faults, logging peak

temperatures, input to Boolean logic-builder functions, and feedback for the fan-control algorithms. To write a

temperature associated with a rail, the PMBus command used is the READ_TEMPERATURE_2 command. If the

host writes that command, the value written is used as the temperature until the writing of another value. This is

true even if the temperature does not have an assigned monitor pin. When there is a monitor pin associated with

the temperature, then after writing READ_TEMPERATURE_2 , there is no further use for the monitor pin until the

part is reset. When there is not a monitor pin associated with the temperature, the internal temperature sensor

senses the temperature until the writing of the READ_TEMPERATURE_2 command.

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UCD9090

Faults and

Warnings

I2C

I2C or SPI

REMOTE

TEMP

SENSOR

Logged Peak

Temperatures

READ_TEMPERATURE_2

HOST

Boolean Logic

Figure 13. Temperature Provided by Host

FAULT RESPONSES AND ALERT PROCESSING

The UCD9090-Q1 monitors whether the rail stays within a window of normal operation. There are two

programmable warning levels (under and over) and two programmable fault levels (under and over). When any

monitored voltage goes outside of the warning or fault window, the PMBALERT# pin asserts immediately, and

setting of the appropriate bits in the PMBus status registers occurs (see Figure 7). The UCD90xxx Sequencer

and System Health Controller PMBus Command Reference and the PMBus Specification provides detailed

descriptions of the status registers.

The user can enable or disable a programmable glitch filter for each MON input and then, on a glitch filter for an

input defined as a voltage, set that filter between 0 and 102 ms with 400-μs resolution.

The device bases fault-response decisions on results from the 12-bit ADC. The device cycles through the ADC

results and compares them against the programmed limits. Timing of the event within the ADC conversion cycle

and the selected fault response determine the time to respond to an individual event.

PMBUS_CNTRL PIN

TIME BETWEEN

RESTARTS

TIME BETWEEN

RESTARTS

TIME BETWEEN

RESTARTS

TON_DELAY[1]

TOFF_DELAY[1]

MAX_GLITCH_TIME

RAIL 1 EN

VOUT_OV_FAULT_LIMIT

MAX_GLITCH_TIME +

TOFF_DELAY[1]

MAX_GLITCH_TIME +

TOFF_DELAY[1]

VOUT_UV_FAULT_LIMIT

POWER_GOOD_ON[1]

MAX_GLITCH_TIME

TOFF_DELAY[1]

RAIL 1 VOLTAGE

TON_DELAY[2]

TOFF_DELAY[2]

RAIL 2 EN

RAIL 2 VOLTAGE

Rail 1 and Rail 2 are both sequenced “ON” and

“OFF” by the PMBUS_CNTRL pin only

Rail 1 is set to use the glitch filter for UV or OV events

Rail 1 is set to RESTART 3 times after a UV or OV event

Rail 1 is set to shutdown with delay for a OV event

Rail 2 has Rail 1 as an “ON” dependency

Rail 1 has Rail 2 as a Fault Shutdown Slave

Figure 14. Sequencing and Fault-Response Timing

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PMBUS_CNTRL PIN

TON_DELAY[1]

Rail 1 and Rail 2 are both sequenced

“ON” and “OFF” by the PMBUS_CNTRL

pin only

RAIL 1 EN

Time Between Restarts

Rail 2 has Rail 1 as an “ON” dependency

Rail 1 is set to shutdown immediately

and RESTART 1 time in case of a Time

On Max fault

POWER_GOOD_ON[1]

RAIL 1 VOLTAGE

TON_MAX_FAULT_LIMIT[1]

TON_DELAY[2]

TON_MAX_FAULT_LIMIT[1]

RAIL 2 EN

RAIL 2 VOLTAGE

Figure 15. Maximum Turnon Fault

The configurable fault limits are:

TON_MAX_FAULT – Flagged if an enabled rail does not reach the POWER_GOOD_ON limit within the

configured time

VOUT_UV_WARN – Flagged if a voltage rail drops below the specified UV warning limit after reaching the

POWER_GOOD_ON setting

VOUT_UV_FAULT – Flagged if a rail drops below the specified UV fault limit after reaching the

POWER_GOOD_ON setting

VOUT_OV_WARN – Flagged if a rail exceeds the specified OV warning limit at any time during startup or

operation

VOUT_OV_FAULT – Flagged if a rail exceeds the specified OV fault limit at any time during startup or operation

MAX_TOFF_WARN – Flagged if a rail not reach 12.5% of the nominal rail voltage within the configured time

following a command to shut down

Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or fault

occurs. If a warning occurs, the following takes place:

Warning Actions

— Immediately assert the PMBALERT# pin

— Flag the status bit

— Assert a GPIO pin (optional)

— Omit logging warnings to flash

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Choose from a number of fault-response options:

Fault Responses

— Continue Without Interruption: Flag the fault and take no action

— Shut Down Immediately: Shut down the faulted rail immediately and restart according to the rail

configuration

— Shut Down using TOFF_DELAY: If a fault occurs on a rail, exhaust whatever retries are

configured. If the rail does not come back, schedule the shutdown of this rail and all fault-

shutdown slaves. Sequence all selected rails off, including the faulty rail, according to their

sequence-off dependencies and T_OFF_DELAY times. For the Do Not Restart selection,

sequence off all selected rails on fault detection.

Restart

— Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down.

— Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down.

The measurement for time between restarts is between the rail enable pin deassertion (after any

glitch filtering and turnoff delay times, if configured to observe them) and reassertion. That time

setting can be between 0 and 1275 ms in 5-ms increments.

— Restart Continuously: Same as Restart Up To N Times except that the device continues to restart

until the fault goes away, the specified combination of PMBus OPERATION command and

PMBUS_CNTRL pin status commands it off, reset of the device, or removal of power from the

device.

— Shut Down Rails and Sequence On (Re-sequence): Shut down the selected rails immediately or

after reaching the continue-operation time, and then sequence-on those rails using sequence-on

dependencies and T_ON_DELAY times.

SHUT DOWN ALL RAILS AND SEQUENCE ON (RESEQUENCE)

One can configure the UCD9090-Q1 to turn off a set of rails and then sequence them back on in response to a

fault or a RESEQUENCE command. To sequence all rails in the system, select all rails as fault-shutdown slaves

of the faulted rail. The rails designated as fault-shutdown slaves do soft shutdowns regardless of whether the

setting for the faulted rail is to stop immediately or stop with delay. Only after all retries are exhausted for a given

fault does the device perform shut-down-all-rails and sequence-on.

While waiting for the rails to turn off, any of the rails reaching its TOFF_MAX_WARN_LIMIT results in the

reporting of an error. There is a configurable option to continue with the resequencing operation if an error report

occurs. After the faulted rail and fault-shutdown slaves sequence-off, the UCD9090-Q1 waits for a programmable

delay time between 0 and 1275 ms in increments of 5 ms and then sequences-on the faulted rail and fault-

shutdown slaves according to the start-up sequence configuration. This repeats until the faulted rail and fault-

shutdown slaves successfully achieve regulation, or for a user-selected 1, 2, 3, 4, or unlimited number of times. If

the resequence operation is successful, the resequence counter resets if all of the resequenced rails maintain

normal operation for one second.

Once shut-down-all-rails and sequence-on begin, the device ignores any faults on the fault-shutdown slave rails.

The occurrence of two or more simultaneous faults with different fault-shutdown slaves results in taking the more

conservative. For example, if a set of rails is already on its second resequence and the device is configured to

resequence three times, and another set of rails enters the resequence state, resequencing that second set of

rails only happens once. Another example – if one set of rails is waiting for all of its rails to shut down so that it

can resequence, and another set of rails enters the resequence state, the device now waits for all rails from both

sets to shut down before resequencing.

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GPIOs

The UCD9090-Q1 has 21 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable

output-mode options, including open-drain or push-pull outputs that it can actively drive to 3.3 V or ground. The

device can use an additional two pins as either inputs or PWM outputs but not as GPOs. Table 4 lists possible

uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be dependents in

sequencing and alarm processing. Additional uses are for system-level functions such as external interrupts,

power-goods, resets, or for the cascading of multiple devices. Configuring a rail without a MON pin but with a

GPIO set as an enable can sequence a GPO up or down.

Table 4. GPIO Pin-Configuration Options

RAIL EN

(10 MAX)

GPI

(8 MAX)

GPO

(10 MAX)

PWM OUT

(10 MAX)

MARGIN PWM

(10 MAX)

PIN NAME

FPWM1/GPIO5

FPWM2/GPIO6

FPWM3/GPIO7

FPWM4/GPIO8

FPWM5/GPIO9

FPWM6/GPIO10

FPWM7/GPIO11

FPWM8/GPIO12

GPI1/PWM1

GPI2/PWM2

GPIO1

10

11

12

13

14

15

16

17

22

23

4

X

GPIO2

5

GPIO3

6

GPIO4

7

GPIO13

18

21

24

25

26

27

28

29

30

GPIO14

GPIO15

GPIO16

GPIO17

TCK/GPIO18

TDO/GPIO19

TDI/GPIO20

TMS/GPIO21

GPO Control

PMBus commands or logic defined in internal Boolean function blocks can control the GPIOs when configured as

outputs. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG) can provide control over

LEDs, enable switches, and so forth, with the use of an I²C interface. See the UCD90xxx Sequencer and System

Health Controller PMBus Command Reference for details on controlling a GPO using PMBus commands.

GPO Dependencies

A user can configure GPIOs as outputs that are based on Boolean combinations of up to two ANDs all ORed

together (Figure 16). Inputs to the logic blocks can include the first eight defined GPOs, GPIs, and rail-status

flags. The user can select one rail-status type as an input for each AND gate in a Boolean block, and for a

selected rail status, include the status flags of all active rails as inputs to the AND gate. _LATCH rail-status types

stay asserted until cleared by a MFR PMBus command or by a specially configured GPI pin. Table 5 shows the

different rail-status types. See the UCD90xxx Sequencer and System Health Controller PMBus Command

Reference for complete definitions of rail-status types. The GPO response is configurable to have a delayed

assertion or deassertion.

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Sub block repeated for each of GPI(1:7)

GPI_INVERSE(0)

GPI_POLARITY(0)

GPI_ENABLE(0)

AND_INVERSE(0)

1

_GPI(0)

GPI(0)

_GPI(1:7)

_STATUS(0:8)

_GPO(1:7)

_STATUS(9)

There is one STATUS_TYPE_SELECT for each of the two AND

boolean block

gates in

a

STATUS_TYPE_SELECT

STATUS(0)

STATUS(1)

OR_INVERSE(x)

Status Type 1

Sub block repeated for each of STATUS(0:8)

GPOx

STATUS_INVERSE(9)

STATUS_ENABLE(9)

Status Type 31

ASSERT_DELAY(x)

1

STATUS(9)

AND_INVERSE(1)

DE-ASSERT_DELAY(x)

_GPI(0:7)

_STATUS(0:9)

_GPO(0:7)

Sub block repeated for each of GPO(1:7)

GPO_INVERSE(0)

GPO_ENABLE(0)

1

_GPO(0)

GPO(0)

Figure 16. Boolean Logic Combinations

Figure 17. Fusion Boolean Logic Builder

Table 5. Rail-Status Types for Boolean Logic

Rail-Status Types

POWER_GOOD

IOUT_UC_FAULT

TOFF_MAX_WARN_LATCH

SEQ_ON_TIMEOUT_LATCH

MARGIN_EN

TEMP_OT_FAULT

MRG_LOW_nHIGH

VOUT_OV_FAULT

VOUT_OV_WARN

VOUT_UV_WARN

VOUT_UV_FAULT

TON_MAX_FAULT

TOFF_MAX_WARN

IOUT_OC_FAULT

IOUT_OC_WARN

TEMP_OT_WARN

SEQ_OFF_TIMEOUT_LATCH

SYSTEM_WATCHDOG_TIMEOUT_LATCH

IOUT_OC_FAULT_LATCH

SEQ_ON_TIMEOUT

SEQ_OFF_TIMEOUT

SYSTEM_WATCHDOG_TIMEOUT

VOUT_OV_FAULT_LATCH

VOUT_OV_WARN_LATCH

VOUT_UV_WARN_LATCH

VOUT_UV_FAULT_LATCH

TON_MAX_FAULT_LATCH

IOUT_OC_WARN_LATCH

IOUT_UC_FAULT_LATCH

TEMP_OT_FAULT_LATCH

TEMP_OT_WARN_LATCH

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GPO Delays

A user can configure the GPOs so that they manifest a change in logic with a delay on assertion, deassertion,

both, or none. GPO behavior using delays has different effects depending on whether the logic change occurs at

a faster rate than the delay. On a normal delay configuration, if the logic for a GPO changes to a state and

reverts back to the previous state within the time of a delay, then the GPO does not manifest the change of state

on the pin. In Figure 18, the GPO setting is such that it follows the GPI with a 3-ms delay at assertion and also at

de-assertion. When the GPI first changes to a high logic state, the device maintains the state for a time longer

than the delay, allowing the GPO to follow with an appropriate logic state. The same goes when the GPI returns

to its previous low logic state. The second time that the GPI changes to a high logic state, it returns to a low logic

state before the delay time expires. In this case, the GPO does not change state. A delay configured in this

manner serves as a glitch filter for the GPO.

3ms

GPI

GPO

1ms

Figure 18. GPO Behavior When Not Ignoring Inputs During Delay

The Ignore Input During Delay bit allows the output of a change in GPO even if it occurs for a time shorter than

the delay. This configuration setting has the GPO ignore any activity from the triggering event until the delay

expires. Figure 19 represents the two cases for ignoring the inputs during a delay. In the case in which the logic

changes occur with more time than the delay, the GPO signal looks the same as when not ignoring the input.

Then on a GPI pulse shorter than the delay, the GPO still changes state. Any pulse that occurs on the GPO

when having the Ignore Input During Delay bit set has a duration of at least the time delay.

3ms

GPI

GPO

1ms

Figure 19. GPO Behavior When Ignoring Inputs During Delay

State Machine Mode Enable

With this bit in the GPO_CONFIG command set, the device uses only one of the AND paths at a given time.

When the GPO logic result is currently TRUE, the device uses AND path 0 until the result becomes FALSE.

When the GPO logic result is currently FALSE, the device uses AND path 1 until the result becomes TRUE. This

provides a very simple state machine and allows for more-complex logical combinations.

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GPI Special Functions

There are five special input functions which use GPIs. There can be no more than one pin assigned to each of

these functions.

•

GPI Fault Enable – When set, the device treats de-assertion of the GPI as a fault.

Latched Statuses Clear Source – When a GPO uses a latched status type (_LATCH), one can configure a

GPI that clears the latched status.

•

Input Source for Margin Enable – With this pin asserted, the device puts all rails with margining enabled in

a margined state (low or high).

Input Source for Margin Low or Not-High – With this pin asserted, the device sets all margined rails to

margin low as long as the input source asserts the margin enable. With this pin deasserted, the device sets

the rails to margin high.

The

configuration

of

GPI

polarity

can

be

either

active-low

or

active-high.

The

PIN_SELECTED_RAIL_STATES command uses the first three GPIs defined, regardless of their main purpose.

Power-Supply Enables

Configuration of ach GPIO can be as a rail-enable pin with either active-low or active-high polarity. Output mode

options include open-drain or push-pull outputs that one can actively drive to 3.3 V or ground. During reset, the

GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which the device drives low. To hold the

power supplies off during reset, tie external pulldown or pullup resistors to the enable pins. The UCD9090-Q1

can support a maximum of 10 enable pins.

NOTE

The only use of GPIO pins that have FPWM capability (pins 10–17) should be as power-

supply enable signals if the signal is active-high.

Cascading Multiple Devices

One can use a GPIO pin to coordinate multiple controllers by using the pin as a power-good output from one

device and connecting it to the PMBUS_CNTRL input pin of another. This imposes a master-slave relationship

among multiple devices. During start-up, the slave controllers initiate their start sequences after the master has

completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the

master starts to sequence-off, it sends the shutdown signal to its slaves.

A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master

shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple

controllers, but it does not enforce interdependency between rails within a single controller.

The PMBus specification implies that the power-good signal is active when all the rails in a controller are

regulating at their programmed voltage. The UCD9090-Q1 allows configuring of GPIOs to respond to a desired

subset of power-good signals.

PWM Outputs

FPWM1–FPWM8

Pins 10–17 are configurable as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to 125

MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers, or general-purpose PWMs.

Any FPWM pin not used as a PWM output is configurable as a GPIO. A designer can use one FPWM in a pair

as a PWM output and the other pin as a GPO. The device actively drives FPWM pins low from reset when used

as GPOs.

The frequency settings for the FPWMs apply to pairs of pins:

•

FPWM1 and FPWM2 – same frequency

FPWM3 and FPWM4 – same frequency

FPWM5 and FPWM6 – same frequency

FPWM7 and FPWM8 – same frequency

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If not using an FPWM pin from a pair while the setting of its companion is to function as a PWM, TI recommends

configuring the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the

system. Setting an FPWM automatically enables the other FPWM within the pair if not configured for any other

functionality.

Derive the frequency for the FPWM by dividing down a 250-MHz clock. To determine an actual frequency to

which an FPWM can be set, divide 250 MHz by any integer between 2 and (2¹⁴– 1).

The FPWM duty-cycle resolution depends on the frequency setting for a given FPWM. After determining the

frequency, calculate the duty-cycle resolution using Equation 1.

Change per Step (%)_FPWM= frequency ÷ (250 × 10⁶× 16) × 100

(1)

Take for an example determining the actual frequency and the duty-cycle resolution for a 75-MHz target

frequency.

1. Divide 250 MHz by 75 MHz to obtain 3.33.

2. Round off 3.33 to obtain an integer of 3.

3. Divide 250 MHz by 3 to obtain the actual closest frequency of 83.333 MHz.

4. Use Equation 1 to calculate the duty-cycle resolution of 2.0833%.

PWM1-2

Pins 22 and 23 are usable as GPIs or PWM outputs. These PWM outputs have an output frequency of 0.93 Hz

to 7.8125 MHz.

Derive the frequency for PWM1 and PWM2 by dividing down a 15.625-MHz clock. To determine a possible

frequency setting for these PWMs, one must divide 15.625 MHz by any integer between 2 and (2²⁴– 1). The

duty-cycle resolution depends on the set frequency for PWM1 and PWM2.

The PWM1 or PWM2 duty-cycle resolution depends on the frequency set for the given PWM. Knowing the

frequency, one can calculate the duty-cycle resolution using Equation 2.

Change per Step (%)_PWM1/2= frequency ÷ 15.625 × 10⁶× 100

(2)

Calculate as follows to determine the PWM1 frequency setting closest 1 MHz:

1. Divide 15.62 5 MHz by 1 MHz to obtain 15.625.

2. Round off 15.625 to obtain an integer of 16.

3. Divide 15.625 MHz by 16 to obtain the actual closest frequency of 976.563 kHz.

4. Use Equation 2 to calculate the duty-cycle resolution of 6.25%.

All frequencies below 238 Hz have a duty-cycle resolution of 0.0015%.

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Programmable Multiphase PWMs

The user can align FPWMs with reference to their phase. The phase for each FPWM is configurable from 0° to

360°. This provides flexibility in PWM-based applications such as power-supply controller, digital clock

generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180° and 270°

(Figure 20).

Figure 20. Multiphase PWMs

MARGINING

Product validation testing uses margining to verify that the complete system works properly over all conditions,

including minimum and maximum power-supply voltages, load range, ambient temperature range, and other

relevant parameter variations. Margining can be controlled over PMBus using the OPERATION command or by

configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG command in the

UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes different available

margining options, including ignoring faults while margining and using closed-loop margining to trim the power-

supply output voltage one time at power up.

Open-Loop Margining

To perform open-loop margining, connect a power-supply feedback node to ground through one resistor and to

the margined power supply output (V_OUT) through another resistor. The power-supply regulation loop responds to

the change in feedback-node voltage by increasing or decreasing the power-supply output voltage to return the

feedback voltage to the original value. The fixed resistor values and the voltage at V_OUTand ground determine

the voltage change. It is necessary to configure two GPIO pins as open-drain outputs for connecting resistors

from the feedback node of each power supply to V_OUTor ground.

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MON(1:10)

3.3V

UCD9090

POWER

SUPPLY

10kW

out

V

GPIO(1:10)

/EN

VOUT

VFB

3.3V

Rmrg_HI

VFB

“0” or “1”

GPIO

VOUT

Rmrg_LO

3.3V

POWER

SUPPLY

Vout

W

10k

/EN

VOUT

VFB

Rmrg_HI

Rmrg_LO

VOUT

.

3.3V

Open Loop Margining

Figure 21. Open-Loop Margining

Closed-Loop Margining

Closed-loop margining uses a PWM or FPWM output for each power supply being margined. An external RC

network converts the FPWM pulse train into a dc margining voltage. The margining voltage is connected to the

appropriate power-supply feedback node through a resistor. The device monitors the power-supply output

voltage and controls the margining voltage by adjusting the PWM duty cycle until the power-supply output

voltage reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions are the

same that apply to the voltage measurement resolution (Table 3). Closed-loop margining can operate in several

modes (Table 6). Given that this closed-loop system has feedback through the ADC, the ADC measurement

dominates the closed-loop margining accuracy. The relationship between duty cycle and margined voltage is

configurable so that voltage increases when duty cycle increases or decreases. For more details on configuring

the UCD9090-Q1 for margining, see the Voltage Margining Using the UCD9012x application note (SLVA375).

Table 6. Closed-Loop Margining Modes

Mode

Description

DISABLE

Margining is disabled.

ENABLE_TRI_STATE

When not margining, the PWM pin is in the high-impedance state.

When not margining, continuous adjustment of the PWM duty cycle keeps the voltage at

VOUT_COMMAND.

ENABLE_ACTIVE_TRIM

ENABLE_FIXED_DUTY_CYCLE

When not margining, the PWM duty-cycle setting is for a fixed duty cycle.

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MON(1:10)

3.3V

UCD9090

POWER

SUPPLY

Vout

10kW

GPIO

/EN

VOUT

VFB

R1

R2

250 kHz – 1MHz

Vmarg

V

FB

FPWM1

R3

R4

C1

Closed Loop

Margining

Figure 22. Closed-Loop Margining

RUN-TIME CLOCK

The run-time clock value is in milliseconds and days. Both are 32-bit numbers. Issuing a STORE_DEFAULT_ALL

command saves this value in nonvolatile memory. Detection of a power-down condition can also save the value

(see BROWNOUT FUNCTION).

The run-time clock is also writable. This allows the host to correct the clock periodically. It also allows initializing

the clock to the actual, absolute time in years (for example, March 23, 2010). The user must translate the

absolute time to days and milliseconds.

The three usage scenarios for the run-time clock are:

•

Time from restart (reset or power-on) – the run-time clock starts from 0 each time a restart occurs

Absolute run-time, or operating time – the device preserves the run-time clock setting across restarts, for

tracking the total time that the device has been in operation (Note: Boot time is not part of this. Only normal

operation time is captured here.)

•

Local time – an external processor sets the run-time clock to real-world time at each time the device restarts.

The run-time clock value is the timestamp for any logged faults.

SYSTEM RESET SIGNAL

The UCD9090-Q1 can generate a programmable system-reset pulse as part of sequence-on. Programming a

GPIO to remain deasserted until the voltage of a particular rail or combination of rails reaches its respective

POWER_GOOD_ON levels, plus a programmable delay time, creates the pulse. Program the system-reset delay

duration as shown in Table 7. See an example of two SYSTEM RESET signals in Figure 23. Configuration of the

first SYSTEM RESET signal is such that it becomes de-asserted on Power Good On and asserted on Power

Good Off after a given common delay time. Configurationn of the second SYSTEM RESET signal is such that it

sends a pulse after a delay time on achieving Power Good On. The pulse duration is configurable between 0.001

s and 32.256 s. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for

pulse-duration configuration details.

Power Good On

Power Good Off

POWER GOOD

Delay

SYSTEM RESET

configured without pulse

Pulse

SYSTEM RESET

configured with pulse

Figure 23. System Reset With and Without Pulse Setting

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The system reset can react to watchdog timing. In Figure 24, the first delay on SYSTEM RESET is for the initial

reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog

configuration includes a start time and a reset time. If these times expire without the WDI clearing them, then the

expectation is that the CPU providing the watchdog signal is not operating. Either a delay or GPI tracking-release

delay toggles the SYSTEM RESET to determine if the CPU recovers.

Power Good On

POWER GOOD

Watchdog

Reset Time

Watchdog

Start Time

Watchdog

Start Time

WDI

Delay

Watchdog

Reset Time

SYSTEM RESET

Delay or

GPI Tracking Release Delay

Figure 24. System Reset With Watchdog

Table 7. System-Reset Delay

Delay

0 ms

1 ms

2 ms

4 ms

8 ms

16 ms

32 ms

64 ms

128 ms

256 ms

512 ms

1.02 s

2.05 s

4.10 s

8.19 s

16.38 s

32.8 s

WATCHDOG TIMER

The user can configure a GPI and GPO as a watchdog timer (WDT). The WDT can be independent of power-

supply sequencing or tied to a GPIO functioning as a watchdog output (WDO) configured to provide a system-

reset signal. One can reset the WDT by toggling a watchdog input (WDI) pin or by writing to

SYSTEM_WATCHDOG_RESET over I²C. The WDI and WDO pins are optional when using the watchdog timer.

The SYSTEM_WATCHDOG_RESET command can replace the WDI and the Boolean-logic-defined GPOs or the

system-reset function can manifest the WDO.

The WDT can be active immediately at power up or set to wait while the system initializes. Table 8 lists the

programmable wait times before the initial time-out sequence begins.

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Table 8. WDT Initial Wait Time

WDT INITIAL WAIT TIME

0 ms

100 ms

200 ms

400 ms

800 ms

1.6 s

3.2 s

6.4 s

12.8 s

25.6 s

51.2 s

102 s

205 s

410 s

819 s

1638 s

The watchdog time-out is programmable from 0.001s to 32.256 s. See the UCD90xxx Sequencer and System

Health Controller PMBus Command Reference for details on configuring the watchdog time-out. If the WDT

times out, the UCD9090-Q1 can assert a GPIO pin configured as WDO that is separate from a GPIO defined as

system-reset pin, or it can generate a system-reset pulse. After a time-out, toggling the WDI pin or writing to

SYSTEM_WATCHDOG_RESET over I²C restarts the WDT.

<t_WDI

t_WDI

<t_WDI

WDI

WDO

Figure 25. Timing of GPIOs Configured for Watchdog Timer Operation

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DATA AND ERROR LOGGING TO FLASH MEMORY

The UCD9090-Q1 can log faults and the number of device resets to flash memory, which also stores peak

voltage measurements for each rail. To reduce stress on the flash memory, the device starts a 30-second timer if

a measured value exceeds the previously logged value, and writes only the highest value from the 30-second

interval from RAM to flash.

Flash memory can store multiple faults, and accessing the faults over PMBus helps to debug power-supply bugs

or failures. Each logged fault includes:

•

Rail number

Fault type

Fault time since previous device reset

Last measured rail voltage

Flash memory also stores the total number of device resets. One can reset the value using PMBus.

With the brownout function enabled, the device only logs the run-time clock value, peak monitor values, and

faults to flash on detection of a power-down. The device stores its run-time clock value across resets or power

cycles unless the brownout function is disabled, in which case the run-time clock returns to zero after each reset.

It is also possible to update and calibrate the UCD9090-Q1 internal run-time clock via a PMBus host. For

example, a host processor with a real-time clock could periodically update the UCD9090-Q1 run-time clock to a

value that corresponds to the actual date and time. The host must translate the UCD9090-Q1 timer value back

into the appropriate units, based on the usage scenario chosen. See the REAL_TIME_CLOCK command in the

UCD90xxx Sequencer and System Health Controller PMBus Command Reference for more details.

BROWNOUT FUNCTION

The user can enable the UCD9090-Q1 to turn off all nonvolatile logging until a brownout event is detected. A

brownout event occurs if V_CCdrops below 2.9 V. In order to enable this feature, the user must provide enough

local capacitance to deliver up to 80 mA (consider additional load based on GPOs sourcing external circuits such

as LEDs) for 5 ms while maintaining a minimum of 2.6 V at the device. If using the brownout circuit (Figure 26),

then place a Schottky diode so that it blocks the other circuits that are also powered from the 3.3-V supply.

With this feature enabled, the UCD9090-Q1 saves faults, peaks, and other log data to SRAM during normal

operation of the device. On detection of a brownout event, the device copies all data from SRAM to Flash. Use of

this feature allows the UCD9090-Q1 to keep track of a single run-time clock that spans device resets or system

power down (rather than resetting the run-time clock after device reset). Use of this feature can also improve the

UCD9090-Q1 internal response time to events, because the device disables Flash writes during normal system

operation. This is an optional feature which one can enable using the MISC_CONFIG command. For more

details, see the UCD90xxx Sequencer and System Health Controller PMBus Command Reference.

UCD9090

B340A

V33A

V33D

AVSS1

AVSS2

3.3V

C

DVSS

Figure 26. Brownout Circuit

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PMBUS ADDRESS SELECTION

Two pins are allocated to decode the PMBus address. At power up, the device applies a bias current to each

address-detect pin, and the internal 12-bit ADC captures the voltage on that pin. Calculate the PMBus address

as follows.

PMBus Address = 12 × bin(V_AD01) + bin(V_AD00

)

Where bin(V_AD0x) is the address bin for one of eight addresses as shown in Table 9. The MIN and MAX

VOLTAGE RANGE (V) define the address bins. Each bin is a constant ratio of 1.25 from the previous bin. This

method maintains the width of each bin relative to the tolerance of standard 1% resistors.

Table 9. PMBus Address Bins

RPMBus

ADDRESS BIN

PMBus RESISTANCE (kΩ)

Open

—

11

200

154

118

90.9

69.8

53.6

41.2

31.6

—

10

9

8

7

6

5

4

Short

A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the

PMBus address to default to address 126 (0x7E). A high impedance (open) on either address pin that produces

a voltage above the maximum voltage also causes the PMBus address to default to address 126 (0x7E).

Address 0 is not used because it is the PMBus general-call address. This device or any other device that shares

the PMBus with it cannot use addresses 11 and 127, because TI reserves those for manufacturing programming

and test. TI recommends not using address 126 for any devices on the PMBus, because this is the address to

which the UCD9090-Q1 defaults in case of a short or open on the address lines. Table 10 summarizes which

PMBus addresses can be used. Specific devices have other SMBus or PMBus addresses assigned to them. For

a system with other types of devices connected to the same PMBus, see the SMBus device address

assignments table in Appendix C of the latest version of the System Management Bus (SMBus) specification.

The SMBus specification is available for download at http://smbus.org/specs/smbus20.pdf.

Table 10. PMBus Address Assignment Rules

Address

STATUS

Prohibited

Avoid

Reason

0

SMBus general address call

11

Causes conflicts with other devices during program flash updates

PMBus alert response protocol

12

Prohibited

For JTAG use

Prohibited

126

127

Default value; may cause conflicts with other devices

Used by TI manufacturing for device tests

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VDD

UCD9090

10uA

Ibias

On/Off Control

To 12-bit ADC

PMBUS_ADDR0

PMBUS_ADDR1

Resistors to set

PMBus address

Figure 27. PMBus Address-Detection Method

CAUTION

TI recommends not selecting address 126 (0x7E) as a permanent PMBus address for

any given application design. Leaving the address in default state as 126 (0x7E)

enables the JTAG and does not allow using the JTAG-compatible pins (27–30) as

GPIOs. The UCD9090-Q1 runs at 10% slower frequency with JTAG enabled to ensure

best JTAG operation.

DEVICE RESET

•

The UCD9090-Q1 has three different reset mechanisms:

–

RESET1 as determined by the voltage on the supply pin (V_33D

RESET2 as determined by the voltage on the RESET pin

RESET2 by a soft-reset command issued over PMBus

)

The UCD90160 has an integrated power-on reset (POR) circuit which monitors the supply voltage, V_33D. When

V_33Dis less than V_RESET(2.4-V maximum), the device is in the RESET1 state, and when V_33Dis greater than

V_RESET, the device exits the RESET1 state.

As V_33Dincreases above approximately 2.6 V, the device begins an initialization routine which includes a flash

error-log integrity check. Normally, the duration of this initialization routine is approximately 20 ms (t_INITin

Figure 28). If the flash error-log integrity check fails, the initialization routine can last for approximately 200 ms. At

the end of the initialization routine, the device begins normal operation as defined by the device configuration.

During the initialization routine, one considers the device to be in the RESET2 state.

It is possible to force the device into the RESET2 state by an external circuit connected to the RESET pin (hard

reset) while the device is operating within the recommended supply voltage range. A voltage less than V_ILfor

longer than t_RESETplaces the device in RESET2 and a voltage greater than V_IHon the RESET pin allows the

initialization routine to start. It is also poslsible to force the device into RESET2 by issuing the soft-reset

command (SendByte 0xDB) over PMBus. After processing of the self-clearing soft-reset command, the

initialization routine begins.

The description of the state of the GPIO pins during RESET1 and RESET2 is as follows:

•

All GPIO: During RESET1, these may sink or source current when approximately 0.7 V < V_33D< V_RESET

FPWM GPIO: During RESET2, these pins sink current.

Other GPIO: During RESET2, these pins behave as inputs (HiZ).

.

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V_V33D

3.0V < V_V33D< 3.6V

~2.6V

V_RESET

RESET1

T_INIT

RESET2

T_INIT

RESET2

RESET1

RESET2

Time

Hard or Soft

RESET asserted

Hard or Soft

RESET de-asserted

Figure 28. UCD9090-Q1 RESET1 and RESET2 Behavior

For cases where GPIO behavior during supply ramp-up might affect system circuitry, the designer may add a

small filter capacitor to the GPIO to help filter the behavior. Use a 100-Ω to 200-Ω series resistor between the

GPIO pin and the filter capacitor to limit the GPIO current. To avoid erroneous noise on the RESET pin, use a

10-kΩ pullup resistor (from RESET to 3.3 V) and a 1000-pF capacitor (from RESET to AVSS).

DEVICE CONFIGURATION AND PROGRAMMING

From the factory, the device contains the sequencing and monitoring firmware. Its configuration is also such that

all GPOs are high-impedance (except for FPWM/GPIO pins 10–17, which it drives low), with no sequencing or

fault-response operation. See Configuration Programming of UCD Devices, available from the Documentation &

Help Center that can be selected from the Fusion GUI Help menu, for full UCD9090-Q1 configuration details.

After the user has designed a configuration file using Fusion GUI, there are three general device-configuration

programming options:

1. A host microcontroller can program devices in-circuit by using PMBus commands over I²C (see the

UCD90xxx

Sequencer

and

System

Health

Controller

PMBus

Command

Reference).

Each parameter write replaces the data in the associated memory (RAM) location. After the device receives

all the required configuration data, it transfers that data to the associated nonvolatile memory (data flash) by

issuing a special command, STORE_DEFAULT_ALL. This method is how the Fusion GUI normally reads

and writes a device configuration.

2. The Fusion GUI (Figure 29) can create a PMBus or I²C command script file which the I²C master can use to

configure the device.

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Figure 29. Fusion GUI PMBus Configuration Script Export Tool

3. Another in-circuit programming option is for the Fusion GUI to create a data flash image from the

configuration file (Figure 30). Export of the configuration files can be in Intel hex, serial vector format (SVF),

or S-record. Download the image file to the device using I²C or JTAG. The Fusion GUI tools are usable on-

board if the Fusion GUI can gain ownership of the I²C bus on the target board.

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Figure 30. Fusion GUI Device Configuration Export Tool

For small runs, use a ZIF socketed board with an I²C header with the standard Fusion GUI or manufacturing

GUI. One can use the TI evaluation module for the UCD90xxx 64-pin sequencer and system-health monitor

(UCD90SEQEVM64-650) for this purpose. The Fusion GUI can also create a data flash file that a dedicated

device programmer can then load into the UCD9090-Q1.

To configure the device over I²C or PMBus, one must power the UCD9090-Q1. The PMBus clock and data pins

must be accessible with pullup resistors between 1 kΩ and 2 kΩ pulling them high to the same V_DDsupply that

powers the device. Take care not to introduce additional bus capacitance (<100 pF). One can use a gang

programmer via JTAG or I²C to write the user configuration to data flash before installing the device in the circuit.

To use I²C, multiplex the clock and data lines or have a socket assign the device addresses. The Fusion GUI

tools are usable for socket addressing. A user can also do pre-programming using a single-device test fixture.

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Table 11. Configuration Options

Data Flash via JTAG

Data Flash via I²C

PMBus Commands via I²C

Data flash export (.srec or hex

type file)

Data flash export (.svf type file)

Dedicated programmer

Project file I²C/PMBus script

Off-Board Configuration

On-Board Configuration

Fusion tools (with exclusive bus

access via USB to I²C adapter)

Fusion tools (with exclusive bus

access via USB to I²C adapter)

Data flash export

IC

Fusion tools (with exclusive bus

access via USB to I²C adapter)

Fusion tools (with exclusive bus

access via USB to I²C adapter)

The advantages of off-board configuration include:

•

Does not require access to device I²C bus on board

Once soldered on board, full board power is available without further configuration.

Can be partially reconfigured once the device is mounted.

Full Configuration Update While in Normal Mode

Although TI recommends performing a full configuration of the UCD9090-Q1 in a controlled test setup, there may

be times which required updating the configuration while the device is in an operating system. Updating the full

configuration based on methods listed in DEVICE CONFIGURATION AND PROGRAMMING section while the

device is in an operating system can be challenging, because these methods do not permit the UCD9090-Q1 to

operate as required by application during the programming. During described methods, the GPIOs may not be in

the desired states ,which can disable rails that provide power to the UCD9090-Q1. To overcome this, the

UCD9090-Q1 has the capability to allow full configuration update while still operating in normal mode.

Updating the full configuration while in normal mode consists of disabling data-flash write protection, erasing the

data flash, writing the data-flash image, and resetting the device. There is not a requirement to reset the device

immediately, but note that the UCD9090-Q1 continues to operate based on the previous configuration with fault

logging disabled until reset. See Configuration Programming of UCD Devices, available from the Documentation

& Help Center that is selectable from the Fusion GUI Help menu, for details.

JTAG INTERFACE

One can use the JTAG port for production programming, and also use four of the six JTAG pins as GPIOs during

normal operation. See the Pin Functions table at the beginning of the document and Table 4 for a list of the

JTAG signals and the names of those which can be used as GPIOs. The JTAG port is compatible with the IEEE

Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. This

device does not support boundary scan. The UCD9090-Q1 runs at 10% slower frequency while the JTAG is

enabled to ensure best JTAG operation.

The JTAG interface can provide an alternate interface for programming the device. Being disabled by default

allows enabling the GPIO pins with which JTAG is multiplexed. There are two conditions which enable the JTAG

interface:

•

On power-up, if the data flash is blank. This condition allows JTAG to be used for writing the configuration

parameters to a programmed device with no PMBus interaction.

•

When address 126 (0x7E) is detected at power up. A short to ground or an open condition on either address

pin generates address 126 (0x7E), which enables JTAG mode.

The UCD9090-Q1 system clock runs at 90% of nominal speed while in JTAG mode. For this reason, it is

important not to leave the UCD9090-Q1 in JTAG mode for normal application operation.

The Fusion GUI can create SVF files (See theDEVICE CONFIGURATION AND PROGRAMMING section) based

on a given data flash configuration, and which one can used to program the desired configuration by JTAG. For a

Boundary Scan Description Language (BSDL) file that supports the UCD9090-Q1, see the product folder in

www.ti.com.

There are many JTAG programmers in the market, and they all do not function the same. If planning to use

JTAG to configure the device, confirm that the available JTAG tools can reliably configure the device before

committing to a programming solution.

38

UCD9090-Q1

www.ti.com.cn

ZHCSAW9A –JANUARY 2013–REVISED FEBRUARY 2013

INTERNAL FAULT MANAGEMENT AND MEMORY ERROR CORRECTION (ECC)

The UCD9090-Q1 verifies the firmware checksum at each power up. If the checksum does not match, then the

device waits for I²C commands but does not execute the firmware. The device also verifies its configuration

checksum at power up. If it does not match, the factory default configuration is loaded. This results in asserting

the PMBALERT# pin and setting a flag in the status register. The error-log checksum validates the contents of

the error log to ensure no corruption in that section of flash.

There is an internal firmware watchdog timer. If it times out, the device resets so that if the firmware program is

corrupted, the device goes back to a known state. This is a normal device reset, so all of the GPIO pins are

open-drain and the FPWM pins are driven low while the device is in reset. Checks are also done on each

parameter that is passed, to make sure it falls within the acceptable range.

Error-correcting code (ECC) is used to improve data integrity and provide high-reliability storage of data-flash

contents. ECC uses dedicated hardware to generate extra check bits for the user data being written into the flash

memory. This adds an additional six bits to each 32-bit memory word stored into the flash array. These extra

check bits, along with the hardware ECC algorithm, allow for detection and correction any single-bit error when

reading the data flash.

39

UCD9090-Q1

ZHCSAW9A –JANUARY 2013–REVISED FEBRUARY 2013

www.ti.com.cn

APPLICATION INFORMATION

12V

12V OUT

TEMP12V

TEMP IC

3.3V

Supply

I12V

INA196

12V OUT

VIN

5V OUT

VOUT

GPIO1

/EN

VMON1

VMON2

VMON3

VMON4

VMON5

VMON6

VMON7

VMON8

VMON9

VMON10

DC-DC 1

VFB

5V OUT

VIN

3.3V OUT

2.5V OUT

VOUT

GPIO2

GPIO3

GPIO4

/EN

DC-DC 2

VFB

1.8V OUT

0.8V OUT

I0.8V

TEMP0.8V

I12V

VIN

2.5V OUT

VOUT

/EN

DC-DC 3

GPIO5

TEMP12V

VIN

VFB

1.8V OUT

/EN VOUT

LDO1

TEMP0.8V

UCD9090

TEMP IC

WDI from main

processor

GPI1

0.8V OUT

VIN

VOUT

GPIO6

/EN

DC-DC 4

GPIO18

GPIO12

GPIO13

GPIO14

GPIO17

WDO

VFB

POWER_GOOD

I0.8V

INA196

Vmarg

2MHz

WARN_OC_0.8V_

OR_12V

FPWM5

Closed Loop

Margining

SYSTEM RESET

OTHER

SEQUENCER DONE

(CASCADE INPUT)

I2C/

PMBUS

JTAG

Figure 31. Typical Application Schematic

NOTE

Figure 31 is a simplified application schematic. Simplifying the schematic entailed

omission of voltage dividers such as the ones placed on the VMON1 input. All VMONx

pins configured to measure a voltage that exceeds the 2.5V ADC reference must have a

voltage divider.

40

UCD9090-Q1

www.ti.com.cn

ZHCSAW9A –JANUARY 2013–REVISED FEBRUARY 2013

Layout Guidelines

The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board

(PCB). Connect the exposed thermal pad of the PCB to the device V_SSpins and provide at least a 4 × 4 pattern

of PCB vias to connect the thermal pad and V_SSpins to the circuit ground on other PCB layers.

For supply-voltage decoupling, provide power-supply pin bypass to the device as follows:

•

0.1-μF, X7R ceramic in parallel with 0.01-μF, X7R ceramic at pin 35 (BPCAP)

0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 33 (V_33D

0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 34 (V_33A

)

Depending on use and application of the various GPIO signals used as digital outputs, one may desire some

impedance control to quiet fast signal edges. For example, using the FPWM pins for fan control or voltage

margining configures the pin as a digital clock signal. Route these signals away from sensitive analog signals. It

is also good design practice to provide a series impedance of 20 Ω to 33 Ω at the signal source to slow fast

digital edges.

Estimating ADC Reporting Accuracy

The UCD9090-Q1 uses a 12-bit ADC and an internal 2.5-V reference (V_REF) to convert MON pin inputs into

digitally reported voltages. The least significant bit (LSB) value is V_LSB= V_REF/2^Nwhere N = 12, resulting in a

VLSB = 610 μV. The error in the reported voltage is a function of the ADC linearity errors and any variations in

VREF. The total unadjusted error (E_TUE) for the UCD9090-Q1 ADC is ±5 LSB, and the variation of VREF is

±0.5% between 0°C and 125°C and ±1% between –40°C and 125°C. V_TUEcalculates as V_LSB× E_TUE. The total

reported voltage error is the sum of the reference-voltage error and V_TUE. At lower monitored voltages, V_TUE

dominates reported error, whereas at higher monitored voltages, the tolerance of V_REFdominates the reported

error. Calculate reported error using Equation 3, where REFTOL is the tolerance of V_REF, V_ACTis the actual

voltage being monitored at the MON pin, and V_REFis the nominal voltage of the ADC reference.

æ

ç

è

ö

÷

ø

V

_REF´E_TUE

1+REFTOL

æ

ö

RPT_ERR

=

´

+ V_ACT-1

ç

÷

V_ACT

4096

è

ø

(3)

From Equation 3, for temperatures between 0°C and 125°C, if V_ACT= 0.5 V, then RPT_ERR= 1.11%. If

V_ACT= 2.2 V, then RPT_ERR= 0.64%. For the full operating temperature range of –40°C to 125°C, if VACT = 0.5V,

then RPT_ERR= 1.62%. If V_ACT= 2.2 V, then RPT_ERR= 1.14%.

41

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048H

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

A

B

PIN 1 INDEX AREA

7.15

6.85

1.0

0.8

C

SEATING PLANE

0.05

0.00

0.08 C

5.3 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

13

24

44X 0.5

12

25

49

SYMM

4X

5.5

0.30

0.18

36

48X

1

0.1

C B A

48

37

0.05

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4224232/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.3)

6X(1.12)

(1.28)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

6X

(1.12)

44X (0.5)

(1.28)

TYP

49

SYMM

(6.8)

(R0.05)

TYP

12

25

(

0.2) TYP

VIA

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224232/A 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.64)

TYP

(1.28)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

(1.28)

TYP

44X (0.5)

(0.64)

TYP

49

SYMM

(R0.05) TYP

(6.8)

METAL

TYP

12

25

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4224232/A 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCD9090-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 10 通道序列发生器和系统运行状况监视器监视器
文件：	总49页 (文件大小：2655K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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