V62/03670-04XE_技术文档

TSB41BA3F-EP

ZHCSS31 –SEPTEMBER 2020

TSB41BA3F-EP IEEE 1394b 三端口电缆收发器/仲裁器

• 失效防护电路检测器件突然断电的情况，并禁用端

口以确保TSB41BA3F-EP 不会加载任何已连接器

件的tpbias，并阻止任何漏电流从端口流回电源平

面

• 支持国防、航空航天和医疗应用：

– 受控基线

1 特性

• 新特性（适用于在BETA 模式下运行的端口)：扰频

器同步丢失检测、快速上电重新连接、同步丢失时

快速重新训练、快速子载波去抖、快速连接（跳频

去抖和速度协商），请参阅节13.2.3

• 完全支持s100、s100b、s200、s200b、s400 和

s400b 信号传输速率（b 表示IEEE 1394b 信号）

下的1394-1995、IEEE 1394a-2000 和IEEE

1394b-2002 规定，请参阅节13.1

• 提供三个完全向后兼容的双语1394b（速率为

400Mbps）和符合1394a-2000（速率为

100/200/400Mbps）的标准

• 全面的1394a-2000 支持包括：连接去抖、仲裁短

路复位、多速度连接、仲裁加速、飞越连接、端口

禁用/挂起/恢复、扩展的恢复信号，以实现与传统

dv 器件的兼容性

• 完全可以与Firewire^™、DTVLink、SB1394、

DishWire 和IEEE 标准1394 的i.LINK^™实施互操

作

• 电缆/收发器硬件速度和端口模式可通过终端状态进

行选择

• 通过将端口设置为仅Beta、仅400Mbps、仅

200Mbps 或仅100Mbps，支持连接到CAT5 电缆

收发器

• 通过将端口设置为仅Beta、仅200Mbps 和仅

100Mbps，支持连接到s200 塑料光纤收发器

• Beta 模式下所有端口的光学信号检测输入可连接到

光学收发器

– 一个组装/测试基地

– 一个制造基地

– 延长了产品生命周期

– 延长了产品变更通知

– 产品可追溯性

2 应用

• 航空电子设备和国防

• 工厂自动化与控制

• 医疗

3 说明

TSB41BA3F-EP 提供了在基于电缆的 IEEE 1394 网络

中实施三端口节点所需的数字和模拟收发器功能。每个

电缆端口包含两个差分线路收发器。收发器包括可根据

需要监控线路条件的电路，用以确定连接状态、进行初

始化和仲裁以及数据包接收和传输。TSB41BA3F-EP

与链路层控制器 (LLC) 相连，例如 TSB82AF15-EP、

TSB12LV21 、 TSB12LV26 、 TSB12LV32 、

TSB42AA4 、 TSB42AB4 、 TSB12LV01B 、

TSB12LV01C 或 TSB82AA2。它还可以通过电缆端口

连接到集成的 1394 链路 + PHY 层，例如

TSB43AB2。

• 通过允许端口1 和2 强制进入仅1394a 模式，支持

使用1394a 连接器

表3-1. 器件信息节15

封装

器件型号

封装尺寸

• PHY-LINK 接口可从1394a-2000 模式

（49.152MHz 时为2/4/8 位）或1394b 模式

（98.304MHz 时为8 位）进行选择

TSB41BA3F-EP

12.00mm × 12.00mm

80 引脚PFP

• 寄存器位让软件可以控制软件器件复位、竞争者

位、电源等级位、链路活动控制位和1394a-2000

特性

• 每个端口具有单独的偏置(tpbias)

• 电缆端口监控远程节点活动连接的线路条件

• 监测电缆是否存在电源

• 传入偏置检测电路上符合1394a-2000 标准的共模

噪声滤波器用于滤除串扰噪声

• 使用断电功能在电池供电应用中省电

• 低成本49.152MHz 晶体以100/200/400Mbps 速率

发送和接收数据，并以49.152MHz 和98.304MHz

提供链路层控制器时钟

• 可与使用3.3V 电源的链路层控制器进行互操作

• 可使用1.8V、3.3V 和5V 电源与其他1394 物理层

(PHY) 进行互操作

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSFA1

TSB41BA3F-EP

ZHCSS31 –SEPTEMBER 2020

www.ti.com.cn

Table of Contents

11.4 Transmit.................................................................. 29

12 Principles Of Operation (1394a-2000 Interface)........33

12.1 LLC Service Request..............................................34

12.2 Status Transfer........................................................37

12.3 Receive...................................................................38

12.4 Transmit.................................................................. 39

12.5 Interface Reset and Disable....................................42

13 Applications, Implementation, and Layout............... 46

13.1 Known exceptions to functional specification

(errata).........................................................................46

13.2 Application Information........................................... 46

14 Device and Documentation Support..........................66

14.1 Tools and Software................................................. 66

14.2 Device Nomenclature..............................................66

14.3 Documentation Support.......................................... 67

14.4 支持资源..................................................................68

14.5 Trademarks.............................................................68

14.6 静电放电警告.......................................................... 68

14.7 术语表..................................................................... 68

15 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Terminal Configuration and Functions..........................3

Terminal Functions............................................................3

6 Specifications................................................................ 11

6.1 Absolute Maximum Ratings...................................... 11

6.2 ESD Ratings..............................................................11

6.3 Recommended Operating Conditions.......................12

6.4 Thermal Information..................................................12

6.5 Electrical Characteristics - Driver..............................13

6.6 Electrical Characteristics - Receiver......................... 13

6.7 Electrical Characteristics - Device............................ 13

6.8 Switching Characteristics..........................................14

7 Operating Life Deration.................................................15

8 Parameter Measurement Information..........................16

9 Overview.........................................................................17

10 Functional Block Diagram.......................................... 21

11 Principles Of Operation (1394b Interface).................22

11.1 LLC Service Request.............................................. 23

11.2 Status Transfer........................................................26

11.3 Receive................................................................... 28

Information.................................................................... 69

15.1 Packaging Information............................................ 69

15.2 Mechanical Data..................................................... 70

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

September 2020

*

Initial Release

2

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5 Terminal Configuration and Functions

PFP PACKAGE

(TOP VIEW)

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AGND

AVDD

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

AVDD

DGND

DVDD-CORE

SM

DGND

DVDD-CORE

S2_PC0

S1_PC1

S0_PC2

DVDD-3.3

DVDD-CORE

DGND

SE

CPS

S3

S4

PLLVDD-3.3

PLLVDD-CORE

PLLGND

XI

TSB41BA3F

VREG_PD

BMODE

RESET

XO

DGND

PLLGND

AVDD

PD

TESTM

R0

ENHANCE_EN

LPS

R1

AGND

1

2

3

4

5

6

7 8 9 10 11 12 13 14 15 16 17 18 19 20

Terminal Functions

TERMINAL

I/O

DESCRIPTION

PFP

NO.

NAME

AGND

TYPE

Supply

21, 40,

43, 50,

61, 62

Analog circuit ground terminals. These terminals must be tied together to the low-

impedance circuit board ground plane.

–

AVDD

Supply

24, 39,

44, 51,

57, 63

Analog circuit power terminals. A combination of high-frequency decoupling capacitors near

each terminal is suggested, such as paralleled 0.1 μF and 0.001 μF. Lower frequency 10-

μF filtering capacitors are also recommended. These supply terminals are separated from

the PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and DVDD-3.3 terminals internal to the

device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must

be tied together with a low dc impedance connection on the circuit board.

–

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TERMINAL

I/O

DESCRIPTION

PFP

NO.

NAME

BMODE

TYPE

CMOS

74

I

Beta-mode input. This terminal determines the PHY-link interface connection protocol.

When logic-high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-

link interface. When logic-low (deasserted), the PHY-link interface complies with the legacy

1394a-2000 standard. When using an LLC such as the 1394b-2002 TSB82AF15-EP, this

terminal must be pulled high. When using an LLC such as the 1394a-2000 TSB12LV26,

this terminal must be tied low.

备注

NOTE: The PHY-link interface cannot be changed between the different

protocols during operation.

CPS

CMOS

34

I

Cable-power status input. This terminal is normally connected to cable power through a

400-kΩ resistor. This circuit drives an internal comparator that detects the presence of

cable power. This transition from cable power sensed to cable power not sensed can be

used to generate an interrupt to the LLC.

CTL0

CTL1

CMOS

9

10

I/O Control I/Os. These bidirectional signals control communication between the TSB41BA3F-

EP and the LLC. Bus holders are built into these terminals.

11, 12,

13, 15,

16, 17,

19, 20

I/O

D0–D7

Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus

holders are built into these terminals.

If power management control (PMC) is selected using LCLK_PMC, then some of these

terminals can be used for PMC. See the LCLK_PMC terminal description for more

information.

DGND

Supply

4, 14,

38, 64,

72, 76

Digital circuit ground terminals. These terminals must be tied together to the low-

impedance circuit board ground plane.

DVDD-CORE

8, 37,

65, 71

Digital core circuit power terminals. A combination of high-frequency decoupling capacitors

near each terminal is suggested, such as paralleled 0.1 μF and

0.001 μF. An additional 1-μF capacitor is required for voltage regulation. These supply

terminals are separated from the DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and AVDD

terminals internal to the device to provide noise isolation.

–

DVDD-3.3

Supply

6, 18,

69, 70

Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling

capacitors near each terminal is suggested, such as paralleled 0.1 μF and

0.001 μF. Lower-frequency 10-μF filtering capacitors are also recommended. The

DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board.

These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-

CORE, and AVDD terminals internal to the device to provide noise isolation. The

PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc

impedance connection on the circuit board.

4

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TERMINAL

I/O

DESCRIPTION

PFP

NO.

NAME

TYPE

LCLK_PMC

CMOS

7

I

Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to

the PHY. On hardware reset, this terminal is sampled to determine the power management

control (PMC) mode.

LCLK_PMC

H

n/c¹

LCLK_PMC²

LPS

L

BMODE Mode

H

L

No LLC (PMC mode)

lps

Legacy LLC

Beta LLC

H

In PMC mode, because no LLC is attached, the data lines (D7–D0) are available to

indicate power states. In PMC mode, the following signals are output:

•

D0—port 0 cable-power disable (see Note)

D1—port 1 cable-power disable (port in sleep or disabled)

D2—port 2 cable-power disable (port in sleep or disabled)

D6—All ports cable-power disable (all ports in sleep/disable) logical AND of bits D0–

D2

•

D3–D5 and D7 are reserved for future use.

备注

NOTE: The cable-power disable is asserted when the port is either:

•

Hard-disabled (both the disabled and hard-disabled bits are set)

Sleep-disabled (both the disabled and sleep_enable bits are set)

Disconnected

Asleep

Connected in DS mode, but nonactive (that is, suspended or disabled)

Otherwise, the cable-power disable output is deasserted (that is, cable power is enabled)

when the port is dc-connected or active. A bus holder is built into this terminal.

LPS

CMOS

80

I

Link power status input. This terminal monitors the active/power status of the link-layer

controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be

connected to either the V_DDsupplying the LLC through an approximately 1-kΩ resistor or to

a pulsed output which is active when the LLC is powered. A pulsed signal must be used

when an isolation barrier exists between the LLC and PHY (see 图13-7).

The LPS input is considered inactive if it is sampled low by the PHY for more than an

LPS_RESET time (~2.6 μs), and is considered active otherwise (that is, asserted steady

high or an oscillating signal with a low time less than 2.6 μs). The LPS input must be high

for at least 22 ns to be observed as high by the PHY.

When the TSB41BA3F-EP detects that the LPS input is inactive, it places the PHY-LLC

interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D

(D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the

PCLK output remains active. If the LPS input remains low for more than an LPS_DISABLE

time (~26 μs), then the PHY-LLC interface is put into a low-power disabled state in which

the PCLK output is also held inactive.

The LLC state that is communicated in the self-ID packet is considered active only if both

the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is

communicated in the self-ID packet is considered inactive if either the LPS input is inactive

or the LCtrl register bit is cleared to 0.

1

Internal pulldown on LCLK_PMC

LCLK_PMC from LLC normally low during reset

2

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TERMINAL

I/O

DESCRIPTION

PFP

NO.

NAME

LREQ

TYPE

CMOS

3

I

LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3F-

EP. A bus holder is built into this terminal.

PCLK

CMOS

5

O

PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the

LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK

output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC

when the PHY-link interface is in legacy 1394a-2000 (BMODE input deasserted).

PD

CMOS

Supply

77

1

I

Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD

input high also activates an internal pulldown on the RESET terminal to force a reset of the

internal control logic.

PINT

O

PHY interrupt. The PHY uses this output to serially transfer status and interrupt information

to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this

terminal.

PLLGND

25, 28

29, 30

PLL circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

–

PLLVDD-CORE Supply

PLL core circuit power terminals. A combination of high-frequency decoupling capacitors

near each terminal is suggested, such as paralleled 0.1 μF and

0.001 μF. An additional 1-μF capacitor is required for voltage regulation. The PLLVDD-

CORE terminals must be separate from the DVDD-CORE terminals. These supply

terminals are separated from the DVDD-CORE, DVDD-3.3, PLLVDD-3.3, and AVDD-3.3

terminals internal to the device to provide noise isolation.

PLLVDD-3.3

Supply

CMOS

31

75

PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors

near the terminal are suggested, such as paralleled 0.1 μF and

0.001 μF. Lower frequency 10-μF filtering capacitors are also recommended. This supply

terminal is separated from the DVDD-CORE, DVDD-3.3, PLLVDD-CORE, and AVDD-3.3

terminals internal to the device to provide noise isolation. The DVDD-3.3 terminals must be

tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3,

and DVDD-3.3 terminals must be tied together with a low dc impedance connection.

–

RESET

I

Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup

resistor to V_DDis provided so only an external delay capacitor is required for proper power-

up operation (see power-up reset in the Application Information section). The RESET

terminal also incorporates an internal pulldown which is activated when the PD input is

asserted high. This input is otherwise a standard logic input, and can also be driven by an

open-drain-type driver.

R0

R1

Bias

23

22

Current setting resistor terminals. These terminals are connected to a precision external

resistance to set the internal operating currents and cable driver output currents. A

resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage

limits.

–

SE

CMOS

35

79

I

Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For

normal use, this terminal must be pulled low either through a 1-kΩ resistor to GND or

directly to GND.

ENHANCE_EN CMOS

Enhancement Enable Formerly SLPEN Automotive sleep mode enable input. At power-on

reset, FPR, FRT and FTD register values are set by ENHANCE_EN. - When

ENHANCE_EN is low FPR, FRT and FTD enhancements are enabled. - When

ENHANCE_EN is high FPR, FRT and FTD enhancements are disabled. See 节

13.2.3.NOTE: SLPEN has not been used in most applications. In most applications pin 79

SLPEN was tied to ground (low). If the TSB41BA3F-EP device is used as a drop-in

replacement where pin 79 ENHANCE_EN is low, all three enhancements will be enabled

without any hardware or software changes. If automotive sleep mode is required, then it

would be required to use revision D or enable sleep mode through software programming

of page 0 registers.

SM

CMOS

36

I

Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For

normal use this terminal must be pulled low either through a 1-kΩ resistor to GND or

directly to GND.

6

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TERMINAL

I/O

DESCRIPTION

PFP

NO.

NAME

TYPE

S2_PC0

S1_PC1

S0_PC2

CMOS

66

67

68

I

Port mode selection terminals 2-0 and power-class programming. On hardware reset, this

terminal when used with the other five selection terminals allows the user to select the

speed and mode of the ports. See 表5-1. Depending on the selection, these inputs can set

the default value of the power class indicated during self-ID.

Programming is done by tying the terminals high through a 1-kΩ resistor or by tying directly

to ground through a 1-kΩ resistor. Bus holders are built into these terminals.

S3

CMOS

33

32

2

I

Port mode selection terminal 3. On hardware reset, this terminal when used with the other

five selection terminals allows the user to select the speed and mode of the ports. See 表

5-1. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or

by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built into this

terminal.

S4

Port mode selection terminal 4. On hardware reset, this terminal when used with the other

five selection terminals allows the user to select the speed and mode of the ports. See 表

5-1. Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or

by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built into this

terminal.

S5_LKON

I/O

Port mode selection terminal 5 and link-on output. This terminal can be connected to the

link-on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on

the link layer.

On hardware reset this terminal, when used with the other Port Speed/Mode Selection

terminals, allows the user to select whether ports act like a 1394b bilingual port (terminal at

logic 0) or as a 1394a-2000-only port (terminal 1394b bilingual mode or high through a 1-

kΩ or less resistor to enable 1394b bilingual mode or high through a 1-kΩ or less resistor to

enable 1394a-2000-only mode. A bus holder is built into this terminal. See 表5-1. A bus

holder is built into this terminal.

After hardware reset, this terminal is the link-on output, which notifies the LLC or other

power-up logic to power up and become active. The link-on output is a square wave signal

with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is

otherwise driven low, except during hardware reset when it is high-impedance.

The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit

cleared) and when one of the following occurs:

1. The PHY receives a link-on PHY packet addressed to this node.

2. The PEI (port-event interrupt) register bit is 1.

3. Any of the CTOI (configuration-timeout interrupt),

CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits is 1

and the RPIE (resuming-port interrupt enable) register bit is also 1.

4. The PHY is power-cycled and the power class is 0 through 4.

Once activated, the link-on output is active until the LLC becomes active (both the LPS

input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-

reset occurs unless the link-on output is otherwise active because one of the interrupt bits

is set (that is, the link-on output is active due solely to the reception of a link-on PHY

packet).

In the case of power-cycling the PHY, the LKON signal must stop after 167 µs if the

preceding conditions have not been met.

备注

NOTE: If an interrupt condition exists which otherwise would cause the link-on

output to be activated if the LLC were inactive, then the link-on output is

activated when the LLC subsequently becomes inactive.

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TERMINAL

I/O

DESCRIPTION

PFP

NO.

NAME

TESTM

TYPE

CMOS

78

I

Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For

normal use this terminal must be pulled high through a 1-kΩ resistor to V_DD

.

Cable

45

46

41

42

I/O Port-0 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

TPA0–

TPA0+

TPB0–

TPB0+

52

53

48

49

I/O Port-1 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

TPA1–

TPA1+

TPB1–

TPB1+

58

59

55

56

I/O Port-2 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

TPA2–

TPA2+

TPB2–

TPB2+

TPBIAS0_SD0 Cable In

TPBIAS1_SD1

TPBIAS2_SD2

47

54

60

I/O Twisted-pair bias output and signal detect input. This provides the 1.86-V nominal bias

voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for

signaling to the remote nodes that there is an active cable connection in 1394a-2000 mode.

Each of these terminals, except for an unused port, must be decoupled with a 1-μF

capacitor to ground. For the unused port, this terminal can be left unconnected.

When a port is configured as a Beta-mode port (B1, B2, B4) this terminal becomes an input

and must be high when a valid signal is present. For optical transceivers, the signal detect

of the transceiver must be connected to this terminal. The input is an LVCMOS level input.

VREG_PD

CMOS

Crystal

73

I

Voltage regulator power-down input. When asserted logic-high through a 1kΩ resistor, this

terminal powers down the internal 3.3-V-to-1.8-V regulator. For single-supply (3.3-V only)

operation, this terminal must be pulled low either through a 1-kΩ resistor to GND or directly

to GND. (If there is high system noise or ground bounce expected, smaller resistor will offer

more immunity)

XI

XO

27

26

I

O

Crystal oscillator inputs. These terminals connect to a 49.152-MHz parallel-resonant

fundamental-mode crystal. The optimum values for the external shunt capacitors depend

on the specifications of the crystal used (see the crystal selection section in the TSB41AB3

IEEE 1394a-2000 Three-Port Cable Transceiver/Arbiter data sheet, SLLS418. XI is a 1.8-V

CMOS input.

8

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MODE

表5-1. Port Speed/Mode Selection

INPUT SELECTION

RESULTING PORT, POWER CLASS, AND SELF-ID

PORT⁽¹⁾

S5_

NO.

S4 S3 S2_ PC0 S1_ PC1 S0_ PC2

POWER CLASS

SELF-ID

LKON

2

1

0

1

2

3

4

5

6

7

0

1

0

1

0

1

PC0

0

PC1

0

PC2

0

Bi

T

S

Bi

T

S

T

Bi

T

S

PC = (PC0, PC1, PC2)

PC = 000

1394b

DS

B1

B2

B4

B2

DS

B1

B2

B4

Bi

B1

B2

B4

0

1

PC = 000

0

1

0

PC = 000

0

1

PC = 100

1394a

8

0

1

0

B1

S

DS

T

DS

T

PC = 100

S100 ⁽²⁾

9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DS

B2

B1

B2

B4

B1

Bi

T

S

T

S

T

S

DS

Bi

T

B2

B4

B1

B2

B4

B2

B1

B2

B4

B1

B2

B4

B2

B1

B2

B4

S

PC = 100

1394b

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

1

PC = 100

1

PC = 100

PC0

PC = PC0,0,0 (100 or 000)

Bi

B1

DS

B1

B2

B4

B1

Bi

DS

(1) LEGEND:

Bi = 1394b-2002 bilingual (S400b only Beta operating speed and data strobe: S400, S200, and S100 operating speeds)

DS = 1394a-2000, data strobe-only, S400, S200, and S100 operating speeds

B1 = 1394b-2002 Beta-only, S100b operating speed

B2 = 1394b-2002 Beta-only, S200b and S100b operating speeds

B4 = 1394b-2002 Beta-only, S400b, S200b, and S100b operating speeds

S = TPBIAS#_SD# terminal is in signal detect input mode

T = TPBIAS#_SD# terminal is in TPBIAS output mode

(2) Mode 8 must only be used to do an S100 home network translation. It must not be used as a nominal end equation mode.

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3.3 V

TSB41BA3F

Signal Detect

S5

S4

TPBIAS0_SD0

POF

S200

Port 0

TPBIAS

1394b

9-Pin

Bilingual

S3

TPBIAS1_SD1

Port 1

PC0 (Don‘t Care)

S2_PC0

3.3 V

TPBIAS

S1_PC1

S0_PC2

TPBIAS2_SD2

Port 2

1394a

6-Pin DS

Mode 21, Port/Speed Mode (1, 1, 0, PC0, 0, 1)

SD High

3.3 V

TSB41BA3F

Signal

Detect

S5

S4

TPBIAS0_SD0

Port 0

RJ45

S100

Equalizer Transformer

3.3 V

TPBIAS

S3

TPBIAS1_SD1

Port 1

1394a

6-Pin DS

PC0 (Don‘t Care)

S2_PC0

Signal Detect

S1_PC1

S0_PC2

TPBIAS2_SD2

Port 2

POF

S100

Mode 24, Port/Speed Mode (1, 1, 1, PC0, 0, 0)

English Data Sheet: SLLSFA1

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

MIN

–0.3

MAX

2.1

4

UNIT

V

V_DD18

V_DD33

Supply voltage range⁽¹⁾

DVDD-CORE, PLLVDD-CORE

DVDD-3.3,PLLVDD-3.3, AVDD

V

Sx, Sx_PCx, VREG_PD, PD, LPS, LREQ,

LCLK, CTLx, Dx, CPS. SLPEN, RESET,

BMODE, TESTM, SDx

V_DD33

+

V_I33

Input voltage range⁽¹⁾

V

–0.5

0.5

V_DD33

+

V_O33

Output voltage range at any output⁽¹⁾

PINT, PCLK, CTLx, Dx, LKON,

0.5

V_A

V_R

V_X

T_J

Analog I/O voltage range⁽¹⁾

TPAx. TPBx

V_DD33

2.1

V

–0.5

Reference voltage range⁽¹⁾

only R1 (R0 is internal ground reference)

XI, XO

Clock input voltage range⁽¹⁾

Absolute maximum junction temperature

Storage temperature range

V_DD18

150

V

°C

T_stg

150

–65

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

(1) All voltage values, except differential I/O bus voltages, are with respect to network ground.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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MAX UNIT

6.3 Recommended Operating Conditions

MIN TYP⁽¹⁾

Source power node

Supply voltage, 3.3 V_DD33

3

3⁽²⁾

3.3

3.6

V

3.6

Nonsource power node

Supply voltage, 1.8 V_DD18

Core voltage

1.75

1.85

2

V

0.7 V_DD33

LREQ, CTL0, CTL1, D0–D7, LCLK_PMC

S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2,

SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1,

TPBIAS2_SD2

High-level input voltage, V_IH

V

0.7 V_DD33

0.6 V_DD33

RESET

0.25

V_DD33

LREQ, CTL0, CTL1, D0–D7, LCLK_PMC

S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2,

SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1,

TPBIAS2_SD2

Low-level input voltage, V_IL

V

0.2 V_DD33

RESET

0.3 V_DD33

4

Output current, I_OL/OH

mA

°C

CTL0, CTL1, D0–D7, S5_LKON, PINT, PCLK

TPBIAS outputs

–4

–5.6

-40

Output current, I_O

1.3

T_A

Operating temperature (free-air)

110

T_J

Operating junction temperature

-40

125

°C

1394b Differential input voltage, V_ID

Cable inputs, during data reception

Cable inputs, during arbitration

200

800

mV

118

260

1394a Differential input voltage, V_ID

mV

168

265

TPB cable inputs, source power node

TPB cable inputs, nonsource power node

RESET input

0.4706

2⁽³⁾

2.515

2.015⁽²⁾

1394a Common-mode input voltage,

V_IC

V

Power-up reset time, t_pu

ms

TPA, TPB cable inputs, S100 operation

TPA, TPB cable inputs, S200 operation

TPA, TPB cable inputs, S400 operation

Between TPA and TPB cable inputs, S100 operation

Between TPA and TPB cable inputs, S200 operation

Between TPA and TPB cable inputs, S400 operation

±1.08

±0.5

1394a receive input jitter

ns

±0.315

±0.8

1394a receive input skew

±0.55

±0.5

(1) All typical values are at V_DD= 3.3 V and T_A= 25°C.

(2) For a node that does not source power, see Section 4.2.2.2 in IEEE 1394a-2000.

(3) Time after valid clock received at PHY XI input terminal.

6.4 Thermal Information

HTQFP (PFP)

80 PINS

28.7

UNIT

THERMAL METRIC⁽¹⁾

UNIT

°C/W

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

22.1

13.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JT

13.7

ψ_JB

R_θJC(bot)

2.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application

report.

English Data Sheet: SLLSFA1

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6.5 Electrical Characteristics - Driver

over recommended ranges of operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

172

300

TYP

MAX UNIT

V_OD

1394a differential output voltage

1394b differential output voltage

265

800

mV

56 Ω, See 图8-1

700

Driver difference current,

TPA+, TPA–, TPB+, TPB–

–1.05⁽¹⁾

–4.84⁽²⁾

–12.4⁽²⁾

I_DIFF

Drivers enabled, speed signaling off

S200 speed signaling enabled

1.05⁽¹⁾

mA

Common-mode speed signaling current,

TPB+, TPB–

–

2.53⁽²⁾

I_SP200

Common-mode speed signaling current,

TPB+, TPB–

–8.1⁽²⁾

I_SP400

V_OFF

S400 speed signaling enabled

mA

mV

Off-state differential voltage

20

Drivers disabled, See 图8-1

(1) Limits defined as algebraic sum of TPA+ and TPA–driver currents. Limits also apply to TPB+ and TPB–algebraic sum of driver

currents.

(2) Limits defined as absolute limit of each TPB+ and TPB–driver currents.

6.6 Electrical Characteristics - Receiver

over recommended ranges of operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP MAX UNIT

4

7

kΩ

pF

Z_ID

Z_IC

Differential impedance

Drivers disabled

4

20

kΩ

pF

Common-mode impedance

Drivers disabled

24

30

V_TH-R

Receiver input threshold voltage

Drivers disabled

mV

V

–30

0.6

V_TH-CB

Cable bias detect threshold, TPBx cable inputs

Positive arbitration comparator threshold voltage

Negative arbitration comparator threshold voltage

Speed signal threshold

1

V_TH

+

89

168

–89

131

396

mV

V_TH–

–168

49

V_TH-SP200

V_TH-SP400

TPBIAS–TPA common-mode

voltage, drivers disabled

Speed signal threshold

314

6.7 Electrical Characteristics - Device

over recommended ranges of operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN TYP

110

MAX UNIT

I_DD

Supply current 3.3 V_DD33

See ⁽¹⁾

150

7.5

mA

V

400-kΩ resistor⁽²⁾

V_TH

Power status threshold, CPS input⁽²⁾

4.7

0.85

V_DD33

High-level output voltage, CTL0, CTL1, D0–D7,

PCLK, S5_LKON outputs

V_OH

V_OL

I_OZ

V

V_DD33= 3 to 3.6 V, I_OH= –4 mA

I_OL= 4 mA

0.22

V_DD33

Low-level output voltage, CTL0, CTL1, D0–D7,

PCLK, S5_LKON outputs

Off-state output current, CTL0, CTL1, D0–D7,

S5_LKON I/Os

V_O= V_DD33or 0 V

±20

μA

I_IRST

V_O

Pullup current, RESET input

TPBIAS output voltage

V_I= 1.5 V or 0 V

–90

–20

μA

At rated I_Ocurrent

1.665

2.015

V

(1) Repeat max packet (one port receiving maximum size isochronous packet–4096 bytes, sent on every isochronous interval, data value

of 0x00FF 00FFh; two ports repeating; all ports with S400 Beta-mode connection), V_DD3.3= 3.3 V, internal regulator, T_A= 25°C

(2) Measured at cable-power side of resistor

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6.8 Switching Characteristics

PARAMETER

TEST CONDITION

MIN

0.3

80

TYP MAX UNIT

1394a-2000

0.8

800

0.8

ns

ps

ns

ps

t_r

t_f

TP differential rise time, transmit

TP differential fall time, transmit

10% to 90%, At 1394 connector

1394b-2002 S400B

1394a-2000

0.3

80

90% to 10%, At 1394 connector

1394b-2002 S400B

800

Setup time, CTL0, CTL1, D0–D7,

LREQ to PCLK

t_su

t_h

t_su

t_h

1394a-2000

1394b

2.5

0

ns

50% to 50%, See 图8-2

50% to 50%, See 图8-3

Hold time, CTL0, CTL1, D0–D7,

LREQ after PCLK

Setup time, CTL0, CTL1, D0–D7,

LREQ to LCLK_PMC

2.5

0

Hold time, CTL0, CTL1, D0–D7,

LREQ after LCLK_PMC

1394b

Delay time, PCLK to CTL0, CTL1,

D0–D7, PINT

1394a-2000 and

1394b-2002

t_d

0.5

1.6

English Data Sheet: SLLSFA1

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7 Operating Life Deration

The information in the section below is provided solely for your convenience and does not extend or modify the

warranty provided under TI’s standard terms and conditions for TI semiconductor products.

500000

Electromigration Fail Mode

400000

Wirebond Voiding Fail Mode

300000

200000

100000

70000

50000

40000

30000

20000

10000

85

90

95

100

105

110

115

120

125

Continuous Junction Temperature - T_J(°C)

wire

A. Silicon operating life design goal is 100000 power-on hours (POH) at 105°C junction temperature (does not include package

interconnect life).

B. The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant

failure mechanism affecting device wear out for the specific device process and design characteristics.

图7-1. TSB41BA3F-EP Operating Life Derating Chart

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8 Parameter Measurement Information

TPAx+

TPBx+

56 Ω

TPAx-

TPBx-

图8-1. Test Load Diagram

xCLK

t

su

t

h

Dx, CTLx, LREQ

图8-2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

xCLK

t

d

Dx, CTLx

图8-3. Dx and CTLx Output Delay Relative to xCLK Waveforms

English Data Sheet: SLLSFA1

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9 Overview

The TSB41BA3F-EP is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal

voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL)

from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The

PLLVDD-CORE terminals are decoupled with 1-μF and smaller decoupling capacitors and the DVDD-CORE

terminals are separately decoupled with 1-μF and smaller decoupling capacitors. The separation between

DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes.

The TSB41BA3F-EP can be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The

core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in the

recommended operating conditions section of this data sheet. The PLLVDD-CORE terminals must be separated

from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-μF and smaller

decoupling capacitors and the DVDD-CORE terminals separately decoupled with 1-μF and smaller decoupling

capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power

supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a

filter network to keep noise from the PLLVDD-CORE supply.

The TSB41BA3F-EP requires an external 49.152-MHz crystal to generate a reference clock. The external clock

drives an internal PLL, which generates the required reference signal. This reference signal provides the clock

signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by

the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the

received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A

98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices

when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power-down (PD)

function, when enabled by asserting the PD terminal high, stops operation of the PLL.

Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths

(depending on the requested transmission speed and PHY-link interface mode of operation). They are latched

internally, combined serially, encoded, and transmitted at 98.304, 122.78, 196.608, 245.76, 393.216, or 491.52

Mbps (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound

information stream.

The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When

using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link

interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as

the TSB82AF15-EP, the BMODE terminal must be asserted. The PHY-link interface then conforms to the

1394b-2002 standard.

The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode

of operation is determined by the interface capabilities of the ports being connected. When any of the three ports

is connected to a 1394a-2000-compliant device, the cable interface on that port operates in the 1394a-2000

data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b-

compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B, or

S400B speed. The TSB41BA3F-EP automatically determines the correct cable interface connection method for

the bilingual ports.

备注

The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal

selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When

the BMODE terminal is deasserted, the PHY-link interface is placed in 1394a-2000 mode and BOSS

arbitration is disabled. When the BMODE terminal is asserted, the PHY-link interface is placed in

1394b-2002 mode and BOSS arbitration is enabled.

During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams (depending on the

indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock,

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and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and

active cable ports.

Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators

to monitor the line states during initialization and arbitration when connected to a 1394a-2000-compliant device.

The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA

channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used

during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel

monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied

twisted pair bias (TPBIAS) voltage.

When connected to a 1394a-2000-compliant node, the TSB41BA3F-EP provides a 1.86-V nominal bias voltage

at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each

port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active

connection. This bias voltage source must be stabilized by an external filter capacitor of 1 μF.

The line drivers in the TSB41BA3F-EP are designed to work with external 112-Ω termination resistor networks in

order to match the 110-Ω cable impedance. One termination network is required at each end of a twisted-pair

cable. Each network is composed of a pair of series-connected ~56-Ω resistors. The midpoint of the pair of

resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The

midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground through a

parallel RC network with recommended values of 5 kΩ and 270 pF. The values of the external line-termination

resistors are designed to meet the standard specifications when connected in parallel with the internal receiver

circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current,

along with other internal operating currents.

When the power supply of the TSB41BA3F-EP is off while the twisted-pair cables are connected, the

TSB41BA3F-EP transmitter and receiver circuitry present a high-impedance signal to the cable that does not

load the device at the other end of the cable.

When the TSB41BA3F-EP is used without one or more of the ports brought out to a connector, the twisted-pair

terminals of the unused ports must be terminated for reliable operation. For each unused port, the preferred

method is for the port to be forced to the 1394a-only mode (data-strobe-only mode, DS), then the TPB+ and

TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be

connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can

be left unconnected. The TPBIAS#_SD# terminal can be left unconnected.

If the port is left in bilingual (Bi) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+

and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA–

terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected.

If the port is left in a forced 1394b Beta-only (B1, B2, or B4) mode, then the TPB+ and TPB– terminals can be

left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination

network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS#_SD#

terminal must be pulled to ground through a 1.2-kΩ or smaller resistor.

To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0,

S1_PC1, and S0_PC2) need to be pulled to V_CCor ground through a 1-kΩ resistor. The port must be operated in

the 1394b bilingual mode whenever a 1394b bilingual or a 1394b Beta-only connector is connected to the port.

To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly to

force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only

mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode

is provided to ensure that 1394b signaling is never sent across a 1394a cable.

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备注

A bilingual port can only connect to a 1394b-only port that operates at S400b. It cannot establish a

connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to a

1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b can

connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only

connect to a 1394b-only port at S100b.

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal

operation, the TESTM terminal must be connected to V_DDthrough a 1-kΩ resistor. The SE and SM terminals

must be tied to ground through a 1-kΩ resistor.

Three package terminals are used as inputs to set the default value for three configuration status bits in the self-

ID packet. They can be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment

design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default

power-class status for the node (the need for power from the cable or the ability to supply power to the cable);

see 表 5-1. The contender bit in the PHY register set indicates that the node is a contender either for the

isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3F-EP, this bit can only be

set by a write to the PHY register set. If a node is a contender for IRM or BM, then the node software must set

this bit in the PHY register set.

The LPS (link power status) terminal works with the S5_LKON terminal to manage the power usage in the node.

The LPS signal from the LLC is used with the LCtrl bit (see 表 13-1 and 表 13-2 in the APPLICATION

INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and

initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input

regardless of the state of the LCtrl bit).

备注

The TSB41BA3F-EP does not have a cable-not-active (CNA) terminal. To achieve a similar function,

the individual PHY ports can be set up to issue interrupts whenever the port changes state. If the LPS

terminal is low, then this generates a link-on (LKON) output clock. See register bits PIE, PEI, and

WDIE along with the individual interrupt bits.

The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal

definition) and is considered active otherwise. When the TSB41BA3F-EP detects that the LPS input is inactive,

the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic

0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low

for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a

low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3F-EP continues the

necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC

interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the

PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled

state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having

entered the LPS_DISABLE time, the TSB41BA3F-EP issues a bus reset. This broadcasts the node self-ID

packet, which contains the updated L bit state (the PHY LLC now being accessible).

The PHY uses the S5_LKON terminal to notify the LLC to power up and become active. When activated, the

output S5_LKON signal is a square wave. The PHY activates the S5_LKON output when the LLC is inactive and

a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as previously

described, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this

node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the S5_LKON output when

the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the

S5_LKON output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause

S5_LKON to be active. If the PHY is power-cycled and the power class is 0 through 4, then the PHY asserts

S5_LKON for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1.

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备注

Revision F of the TSB41BA3 contains feature enhancements that may impact ability to be drop in

replacement with revision D or prior. See 节13.2.3 for further details.

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10 Functional Block Diagram

R0

CPS

LPS

Bias Voltage

and

Current

R1

Received Data

TPBIAS0_SD0

TPBIAS1_SD1

TPBIAS2_SD2

Decoder/Retimer

SLPEN

PINT

Generator

PCLK

LCLK_PMC

LREQ

Link

Interface

CTL0

TPA0+

TPA0-

CTL1

I/O

D0

D1

D2

D3

D4

D5

D6

D7

Cable Port 0

TPB0+

TPB0-

Arbitration

and Control

State Machine

Logic

RESET

S5_LKON

BMODE

PD

TPA1+

TPA1-

S2_PC0

S1_PC1

S0_PC2

SE

Cable Port 1

TPB1+

TPB1-

SM

TPA2+

TPA2-

S3

S4

Cable Port 2

TESTM

TPB2+

TPB2-

XO

XI

Crystal Oscillator,

PLL System,

and Transmit

Clock Generator

Transmit

Data

Encoder

Voltage

VREG_PD

Regulator

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11 Principles Of Operation (1394b Interface)

The TSB41BA3F-EP is designed to operate with an LLC such as the Texas Instruments TSB82AF15-EP when

the BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the

respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This

interface is formally specified in the IEEE 1394b-2002 standard.

The interface to the LLC consists of the PCLK, LCLK_PMC, CTL0–CTL1, D0–D7, LREQ, PINT, LPS, and

S5_LKON terminals on the TSB41BA3F-EP, as shown in 图11-1.

TSB41BA3F

LCLK_PMC

PCLK

CTL0œCTL1

Link-Layer

D0œD7

Controller

LREQ

LPS

S5_LKON

PINT

图11-1. PHY-LLC Interface

The LCLK_PMC terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal

and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK_PMC.

The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals

are synchronized to the rising edge of PCLK.

The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data

between the TSB41BA3F-EP and LLC.

The D0–D7 terminals form a bidirectional data bus, which transfers status information, control information, or

packet data between the devices. The TSB41BA3F-EP supports S400B, S200B, and S100B data transfers over

the D0–D7 data bus. In S400B, S200B, and S100B operation, all Dn terminals are used.

The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request

access to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.

All data on LREQ is synchronous to LCLK_PMC.

The LPS and S5_LKON terminals are used for power management of the PHY and LLC. The LPS terminal

indicates the power status of the LLC, and can be used to reset the PHY-LLC interface or to disable PCLK. The

S5_LKON terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when either

LPS is inactive or the PHY register L bit is 0.

The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.

The TSB41BA3F-EP normally controls the CTL0–CTL1 and D0–D7 bidirectional buses. The LLC is allowed to

drive these buses only after the LLC has been granted permission to do so by the PHY.

Four operations can occur on the PHY-LLC interface: link service request, status transfer, data transmit, and

data receive. The LLC issues a service request to read or write a PHY register or to request the PHY to gain

control of the serial bus in order to transmit a packet.

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The PHY can initiate a status transfer either autonomously or in response to a register read request from the

LLC.

The PHY initiates a receive operation whenever a packet is received from the serial bus.

The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.

The transmit operation is initiated when the PHY grants control of the interface to the LLC.

表11-1 and 表11-2 show the encoding of the CTL0–CTL1 bus.

表11-1. CTL Encoding When PHY Has Control of the Bus

CTL0

CTL1

NAME

DESCRIPTION

0

1

0

1

0

1

Idle

No activity (this is the default mode)

Status

Receive

Grant

Status information is being sent from the PHY to the LLC.

An incoming packet is being sent from the PHY to the LLC.

The LLC has been given control of the bus to send an outgoing packet.

表11-2. CTL Encoding When LLC Has Control of the Bus

NAME DESCRIPTION

CTL0

CTL1

0

1

0

1

0

1

Idle

The LLC releases the bus (transmission has been completed).

An outgoing packet is being sent from the LLC to the PHY.

Reserved

Transmit

Reserved

Holation

The LLC is holding the bus while data is being prepared for transmission, or the LLC is sending a

request to arbitrate for access to the bus, or the LLC is identifying the end of a subaction gap to the

PHY.

11.1 LLC Service Request

To request access to the bus, to read or write a PHY register, or to send a link notification to PHY, the LLC sends

a serial bit stream on the LREQ terminal as shown in 图11-2.

LR0

LR1

LR2

LR3

LR (n-2)

LR (n-1)

Each cell represents one clock sample period, and n is the number of bits in the request stream.

图11-2. LREQ Request Stream

The length of the stream varies depending on the type of request as shown in 表11-3.

表11-3. Request Stream Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

11

10

18

6

Read register request

Write register request

Link notification request

PHY-link interface reset request

6

Regardless of the type of request, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is

required at the end of the stream. The second through fifth bits of the request stream indicate the type of the

request. In the following descriptions, bit LR1 is the most significant and is transmitted first in the request bit

stream. The LREQ terminal is normally low.

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表11-4 shows the encoding for the request type.

表11-4. Request Type Encoding

NAME

Reserved

DESCRIPTION

LR1–LR4

0000

Reserved

Immediate request. On detection of idle, the PHY arbitrates for the bus.

0001

Immed_Req

Next_Even

0010

Next even request. The PHY arbitrates for the bus to send an asynchronous packet in the even fairness

interval phase.

0011

0100

Next_Odd

Current

Next odd request. The PHY arbitrates for the bus to send an asynchronous packet in the odd fairness

interval phase.

Current request. The PHY arbitrates for the bus to send an asynchronous packet in the current fairness

interval.

0101

0110

Reserved

Isoch_Req_Even

Isochronous even request. The PHY arbitrates for the bus to send an isochronous packet in the even

isochronous period.

0111

Isoch_Req_Odd

Isochronous odd request. The PHY arbitrates for the bus to send an isochronous packet in the odd

isochronous period.

1000

1001

1010

1011

1100

Cyc_Start_Req

Reserved

Cycle start request. The PHY arbitrates for the bus to send a cycle start packet.

Reserved

Reg_Read

Reg_Write

Register read request. The PHY returns the specified register contents through a status transfer.

Register write request. Write to the specified register in the PHY.

Isoch_Phase_Even Isochronous phase even notification. The link reports to the PHY that:

1) A cycle start packet has been received.

2) The link has set the isochronous phase to even.

1101

Isoch_Phase_Odd Isochronous phase odd notification. The link reports to the PHY that:

1) A cycle start packet has been received.

2) The link has set the isochronous phase to odd.

1110

1111

Cycle_Start_Due

Reserved

Cycle start due notification. The link reports to the PHY that a cycle start packet is due for reception.

Reserved

For a bus request, the length of the LREQ bit stream is 11 bits as shown in 表11-5.

表11-5. Bus Request

BIT(s)

NAME

DESCRIPTION

0

1–4

5

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Request format

Request speed

Stop bit

Indicates the type of bus request. See 表11-4.

Indicates the packet format to be used for packet transmission. See 表11-6.

Indicates the speed at which the link sends the data to the PHY. See 表11-7 for the encoding of this field.

Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted.

6–9

10

表11-6 shows the 1-bit request format field used in bus requests.

表11-6. Bus Request Format Encoding

LR5

DATA RATE

0

Link does not request either Beta or legacy packet format for bus transmission

Link requests Beta packet format for bus transmission

1

表11-7 shows the 4-bit request speed field used in bus requests.

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表11-7. Bus Request Speed Encoding

DATA RATE

LR6–LR9

0000

S100

0001

Reserved

S200

0010

0011

Reserved

S400

0100

0101

Reserved

S800

0110

All Others

Invalid

备注

The TSB41BA3F-EP accepts a bus request with an invalid speed code and processes the bus request

normally. However, during packet transmission for such a request, the TSB41BA3F-EP ignores any

data presented by the LLC and transmits a null packet.

For a read register request, the length of the LREQ bit stream is 10 bits as shown in 表11-8.

表11-8. Read Register Request

BIT(s)

NAME

DESCRIPTION

0

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Address

A 1010 indicates this is a read register request.

Identifies the address of the PHY register to be read

Indicates the end of the transfer (always 0)

1–4

5–8

9

Stop bit

For a write register request, the length of the LREQ bit stream is 18 bits as shown in 表11-9.

表11-9. Write Register Request

BIT(s)

NAME

DESCRIPTION

0

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Address

Data

A 1011 indicates this is a write register request.

1–4

5–8

9–16

17

Identifies the address of the PHY register to be written

Gives the data that is to be written to the specified register address

Indicates the end of the transfer (always 0)

Stop bit

For a link notification request, the length of the LREQ bit stream is 6 bits as shown in 表11-10.

表11-10. Link Notification Request

BIT(s)

NAME

DESCRIPTION

0

1–4

5

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Stop bit

A 1100, 1101, or 1110 indicates this is a link notification request

Indicates the end of the transfer (always 0)

For fair or priority access, the LLC sends a bus request at least one clock after the PHY-LLC interface becomes

idle. The PHY queues all bus requests and can queue one request of each type. If the LLC issues a different

request of the same type, then the new request overwrites any nonserviced request of that type. On the receipt

(CTL terminals are asserted to the receive state, 10b) of a packet, queued requests are not cleared by the PHY.

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The cycle master node uses a cycle start request (Cyc_Start_Req) to send a cycle start message. After

receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The

PHY clears an isochronous request only when the serial bus has been won.

To send an acknowledge packet, the LLC must issue an immediate bus request (Immed_Req) during the

reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the

received packet and the start of the transmitted acknowledge packet. As soon as the received packet ends, the

PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless

the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but

instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to

send another type of packet. After the interface is released the LLC can proceed with another request.

For write register requests, the PHY loads the specified data into the addressed register as soon as the request

transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the

LLC at the next opportunity through a PHY status transfer. A write or read register request can be made at any

time, including while a bus request is pending. Once a read register request is made, the PHY ignores further

read register requests until the register contents are successfully transferred to the LLC. A bus reset does not

clear a pending read register request.

11.2 Status Transfer

A status transfer is initiated by the PHY when status information is to be transferred to the LLC. Two types of

status transfers can occur: bus status transfer and PHY status transfer. Bus status transfers send the following

status information: bus reset indications, subaction and arbitration reset gap indications, cycle start indications,

and PHY interface reset indications. PHY status transfers send the following information: PHY interrupt

indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link interface error

indications. The PHY uses a different mechanism to send the bus status transfer and the PHY status transfer.

Bus status transfers use the CTL0–CTL1 and D0–D7 terminals to transfer status information. Bus status

transfers can occur during idle periods on the PHY-link interface or during packet reception. When the status

transfer occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that

each individual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only

one status bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset

on the serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all

packet transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the

link, and sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a

PHY interface reset operation, the PHY-link interface is reset on the following PCLK cycle.

表11-11 shows the definition of the bits during the bus status transfer and 图11-3 shows the timing.

表11-11. Status Bits

STATUS BIT

DESCRIPTION

D0

D1

D2

D3

D4

D5

D6

D7

Bus reset

Arbitration reset gap—odd

Arbitration reset gap—even

Cycle start—odd

Cycle start—even

Subaction gap

PHY interface reset

Reserved

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XX

01

XX

CTL[0:1]

D[0:7]

ST

XX

Status Bits

图11-3. Bus Status Transfer Timing

PHY status transfers use the PINT terminal to send status information serially to the LLC as shown in 图 11-4.

PHY status transfers (see 表 11-12) can occur at any time during normal operation. The PHY uses the

PHY_INTERRUPT PHY status transfer when required to interrupt the LLC due to a configuration time-out, a

cable-power failure, a port interrupt, or an arbitration time-out. When transferring PHY register contents, the PHY

uses either the solicited or the unsolicited register read status transfer. The unsolicited register 0 contents are

passed to the LLC only during initialization of the serial bus. After any PHY-link interface initialization, the PHY

sends a PHY status transfer indicating whether or not a bus reset occurred during the inactive period of the PHY-

link interface. If the PHY receives an illegal request from the LLC, then the PHY issues an INTERFACE_ERROR

PHY status transfer.

LR0

LR1

LR2

LR3

LR (n-2)

LR (n-1)

Each cell represents one clock sample period, and n is the number of bits in the request stream.

图11-4. PINT (PHY Interrupt) Stream

表11-12. PHY Status Transfer Encoding

PI[1:3]

000

NAME

DESCRIPTION

NUMBER OF BITS

NOP

No status indication

5

001

PHY_INTERRUPT

Interrupt indication: configuration time-out, cable-power failure, port

event interrupt, or arbitration state machine time-out

010

011

100

101

110

111

PHY_REGISTER_SOL

PHY_REGISTER_UNSOL

PH_RESTORE_NO_RESET

PH_RESTORE_RESET

INTERFACE_ERROR

Reserved

Solicited PHY register read

17

Unsolicited PHY register read

17

PHY-link interface initialized; no bus resets occurred.

PHY-link interface initialized; a bus reset occurred.

PHY received illegal request.

5

Reserved

Most PHY status transfers are 5 bits long. The transfer consists of a start bit (always 1), followed by a request

type (see 表 11-12), and lastly followed by a stop bit (always 0). The only exception is when the transfer of a

register contents occurs. Solicited and unsolicited PHY register read transfers are 17 bits long and include the

additional information of the register address and the data contents of the register (see 表11-13).

表11-13. Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding

BIT(s)

0

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Address

Data

A 010 or a 011 indicates a solicited or unsolicited register contents transfer.

Identifies the address of the PHY register whose contents are being transferred

The contents of the register specified in bits 4 through 7

1–3

4–7

8–15

16

Stop bit

Indicates the end of the transfer (always 0)

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11.3 Receive

When the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive

on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start of

a packet by placing the speed code (encoded as shown in 表11-14) on the D terminals, followed by packet data.

The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been transferred.

The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received packets are

transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the

calculation of CRC or any other data protection mechanisms.

The PHY can optionally send status information to the LLC at anytime during the data-on indication. Only bus

status transfer information can be sent during a data-on indication. The PHY holds the CTL terminals in the

status state for 1 PCLK cycle and modifies the D terminals to the correct status state. Note that the status

transfer during the data-on indication does not need to be preceded or followed by a data-on indication.

It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus

followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed

exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without

transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all

1s) on the D terminals, followed by idle on the CTL terminals, without any speed code or data being transferred.

In all cases, in normal operation, the TSB41BA3F-EP sends at least one data-on indication before sending the

speed code or terminating the receive operation.

The TSB41BA3F-EP also transfers its own self-ID packet, transmitted during the self-ID phase of bus

initialization, to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.

PCLK

CTL0, CTL1

10

00

(e)

(a)

(b)

(c)

SPD

(d)

d0

D0–D7

XX

FF (data-on)

dn

00

A. SPD = speed code, see 表11-14. d0–dn = packet data.

图11-5. Normal Packet Reception Timing

PCLK

CTL0, CTL1

10

(a)

01

10

00

(e)

(b)

(c)

(d)

d0

FF

D0–D7

XX

FF (data-on)

STATUS

SPD

dn

00

(data-on)

A. SPD = speed code, see 表11-14. d0–dn = packet data. STATUS = status bits, see 表11-11.

图11-6. Normal Packet Reception Timing With Optional Bus Status Transfer

The sequence of events for a normal packet reception is as follows:

1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status

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transfer operation that is in progress so that the CTL lines can change from status to receive without an

intervening idle.

2. Data-on indication. The PHY can assert the data-on indication code on the D lines for one or more cycles

preceding the speed code. The PHY can optionally send a bus status transfer during the data-on indication

for one PCLK cycle. During this cycle, the PHY asserts status (01b) on the CTL lines while sending status

information on the D lines.

3. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines

for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle

for which the D lines are not the data-on code. If the speed code is invalid or indicates a speed higher than

that which the link is capable of handling, then the link must ignore the subsequent data.

4. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on

the D lines with receive on the CTL lines for the remainder of the receive operation.

5. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

PCLK

CTL0, CTL1

10

00

(c)

(a)

(b)

D0–D7

XX

FF (data-on)

00

图11-7. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:

1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status

transfer operation that is in progress so that the CTL lines can change from status to receive without an

intervening idle.

2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

3. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

表11-14. Receive Speed Codes and Format

D0–D7⁽¹⁾

0000 0000

0000 0001

0000 0100

0000 0101

0000 1000

0000 1001

0000 1101

1111 1111

All others

DATA RATE AND FORMAT

S100 legacy

S100 Beta

S200 legacy

S200 Beta

S400 legacy

S400 Beta

S800 Beta

Data-on indication

Reserved

(1) Y = Output as 1 by PHY, ignored by LLC.

X = Output as 0 by PHY, ignored by LLC.

11.4 Transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If

the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting

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the grant state (11b) on the CTL terminals and the grant type on the D terminals for one PCLK cycle, followed by

idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (11b), or

transmit (01b) on the CTL terminals. If the PHY does not detect a hold or transmit state within eight PCLK

cycles, then the PHY takes control of the PHY-link interface. The hold state is used by the LLC to retain control

of the bus while it prepares data for transmission. The LLC can assert hold for zero or more clock cycles (that is,

the LLC need not assert hold before transmit). During the hold state, the LLC is expected to drive the D lines to

0. The PHY asserts data-prefix on the serial bus during this time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have

been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle. If the hold is

asserted, then the hold is immediately followed by one clock cycle of idle. The link then releases the PHY-link

interface by putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the

PHY-link interface.

00

11

00

ZZ

PHY CTL[0:1]

00

GT

00

ZZ

PHY D[0:7]

ZZ

11

01

LLC CTL[0:1]

LLC D[0:7]

ZZ

00

d

0

d

1

ZZ

00

PHY CTL[0:1]

PHY D[0:7]

01

11

00

ZZ

LLC CTL[0:1]

LLC D[0:7]

d

n-1

d

n

LR

GT = grant type LR = link request type d0-dn = packet data

图11-8. Transmit Packet Timing With Optional Link Request

The hold state asserted at the end of packet transmission allows the LLC to make an additional link request for

packet transmission and/or to notify the PHY that the packet marks the end of a subaction. The link requests

allowed after packet transmission are listed in 表 11-15 (note that the link request types allowed during this

period are a subset of all of the allowed types of link requests—see 表 11-4). The associated speed codes and

packet format are listed in 表 11-15 and 表 11-16, respectively. If the LLC requests to send an additional packet,

then the PHY does not necessarily have to grant the request. If the LLC is notifying the PHY of the end of a

subaction, then the LLC sets D4 during the hold state at the end of packet transmission.

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表11-15. Link Request Type Encoding During

Packet Transmission

Request Type

D1–D3

000

No request

001

Isoch_Req_Odd

Isoch_Req_Even

Current

010

011

100

Next_Even

101

Next_Odd

110

Cyc_Start_Req

Reserved

111

表11-16. Link Request Speed Code Encoding

During Packet Transmission

DATA RATE

D5–D6

00

S100

01

S200

10

S400

11

S800

表11-17. Link Request Format Encoding During Packet Transmission

D0

FORMAT

0

Link does not request either Beta or legacy packet format for bus transmission.

Link requests Beta packet format for bus transmission.

1

表11-18. Subaction End Notification Encoding During Packet Transmission

D4

DESCRIPTION

Transmitted packet does not represent end of a subaction.

Transmitted packet marks the end of a subaction.

0

1

The PHY indicates to the link during the GRANT cycle which type of grant is being issued. This indication

includes the grant type as well as the grant speed. The link uses the bus grant for transmitting the granted

packet type. The link transmits a granted packet type only if its request type exactly matches the granted speed

and the granted format.

表11-19. Format Type During Grant Cycle

D0 VALUE DURING

GRANT CYCLE

FORMAT

0

1

Unspecified

Beta format

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表11-20. Grant Type Values During Grant Cycle

[D1–D3] VALUE DURING

REQUEST TYPE

GRANT CYCLE

000

001

010

011

100

101

110

111

Reserved

Isochronous grant

Reserved

Asynchronous grant

Cycle start grant

Immediate grant

表11-21. Speed Type Values During Grant Cycle

[D5–D6] VALUE DURING

SPEED TYPE

GRANT CYCLE

00

01

10

11

S100

S200

S400

S800

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12 Principles Of Operation (1394a-2000 Interface)

The TSB41BA3F-EP is designed to operate with an LLC such as the Texas Instruments TSB12LV21B,

TSB12LV26, TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low. Details of

operation for the Texas Instruments LLC devices are found in the respective LLC data sheets. The following

paragraphs describe the operation of the PHY-LLC interface. This interface is formally defined in IEEE

1394a-2000, Section 5A.

The interface to the LLC consists of the PCLK, CTL0–CTL1, D0–D7, LREQ, LPS, and S5_LKON terminals on

the TSB41BA3F-EP, as shown in 图12-1.

TSB41BA3F

PCLK (SYSCLK)

CTL0œCTL1

Link-Layer

D0œD7

Controller

LREQ

LPS

S5_LKON

图12-1. PHY-LLC Interface

The PCLK terminal provides a 49.152-MHz interface system clock. All control and data signals are synchronized

to and sampled on the rising edge of PCLK. This terminal serves the same function as the SYSCLK terminal of

1394a-2000-compliant PHY devices.

The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data

between the TSB41BA3F-EP and LLC.

The D0–D7 terminals form a bidirectional data bus, which transfers status information, control information, or

packet data between the devices. The TSB41BA3F-EP supports S100, S200, and S400 data transfers over the

D0–D7 data bus. In S100 operation, only the D0 and D1 terminals are used; in S200 operation, only the D0–

D3 terminals are used; and in S400 operation, all D0–D7 terminals are used for data transfer. When the

TSB41BA3F-EP is in control of the D0–D7 bus, unused Dn terminals are driven low during S100 and S200

operations. When the LLC is in control of the D0–D7 bus, unused Dn terminals are ignored by the TSB41BA3F-

EP.

The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request

access to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.

The LPS and S5_LKON terminals are used for power management of the PHY and LLC. The LPS terminal

indicates the power status of the LLC and can be used to reset the PHY-LLC interface or to disable PCLK. The

S5_LKON terminal sends a wake-up notification to the LLC or external circuitry and indicates an interrupt to the

LLC when either LPS is inactive or the PHY register L bit is 0.

The TSB41BA3F-EP normally controls the CTL0–CTL1 and D0–D7 bidirectional buses. The LLC is allowed to

drive these buses only after the LLC has been granted permission to do so by the PHY.

Four operations can occur on the PHY-LLC interface: link service request, status transfer, data transmit, and

data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain

control of the serial bus in order to transmit a packet, or to control arbitration acceleration.

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The PHY can initiate a status transfer either autonomously or in response to a register read request from the

LLC.

The PHY initiates a receive operation whenever a packet is received from the serial bus.

The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.

The transmit operation is initiated when the PHY grants control of the interface to the LLC.

表12-1 and 表12-2 show the encoding of the CTL0–CTL1 bus.

表12-1. CTL Encoding When PHY Has Control of the Bus

CTL0

CTL1

NAME

DESCRIPTION

0

1

0

1

0

1

Idle

No activity (this is the default mode)

Status

Receive

Grant

Status information is being sent from the PHY to the LLC.

An incoming packet is being sent from the PHY to the LLC.

The LLC has been given control of the bus to send an outgoing packet.

表12-2. CTL Encoding When LLC Has Control of the Bus

DESCRIPTION

CTL0

CTL1

NAME

Idle

0

1

The LLC releases the bus (transmission has been completed).

Hold

The LLC is holding the bus while data is being prepared for transmission or indicating that another packet

is to be transmitted (concatenated) without arbitrating.

0

1

0

1

Transmit

An outgoing packet is being sent from the LLC to the PHY.

None

Reserved

12.1 LLC Service Request

To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC

sends a serial bit stream on the LREQ terminal as shown in 图12-2.

LR0

LR1

LR2

LR3

LR (n-2)

LR (n-1)

Each cell represents one clock sample period, and n is the number of bits in the request stream.

图12-2. LREQ Request Stream

The length of the stream varies depending on the type of request as shown in 表12-3.

表12-3. Request Stream Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

7 or 8

Read register request

Write register request

9

17

6

Acceleration control request

Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is

required at the end of the stream. The second through fourth bits of the request stream indicate the type of the

request. In the following descriptions, bit 0 is the most significant and is transmitted first in the request bit stream.

The LREQ terminal is normally low.

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表12-4 shows the encoding for the request type.

表12-4. Request Type Encoding

NAME

DESCRIPTION

LR1–LR3

000

ImmReq

Immediate bus request. On detection of idle, the PHY takes control of the bus immediately without arbitration.

Isochronous bus request. On detection of idle, the PHY arbitrates for the bus without waiting for a subaction

gap.

001

IsoReq

010

011

100

101

110

111

PriReq

Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.

Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.

The PHY returns the specified register contents through a status transfer.

Write to the specified register

FairReq

RdReg

WrReg

AccelCtl

Reserved

Enable or disable asynchronous arbitration acceleration

Reserved

For a bus request, the length of the LREQ bit stream is 7 or 8 bits as shown in 表12-5.

表12-5. Bus Request

BIT(s)

NAME

DESCRIPTION

0

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Request speed

Stop bit

1–3

Indicates the type of bus request. See 表12-4.

Indicates the speed at which the PHY sends the data for this request. See 表12-6 for the encoding of this

field.

4–6

7

Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted.

表12-6 shows the 3-bit request speed field used in bus requests.

表12-6. Bus Request Speed Encoding

DATA RATE

LR4–LR6

000

S100

010

S200

100

S400

All Others

Invalid

备注

The TSB41BA3F-EP accepts a bus request with an invalid speed code and processes the bus request

normally. However, during packet transmission for such a request, the TSB41BA3F-EP ignores any

data presented by the LLC and transmits a null packet.

For a read register request, the length of the LREQ bit stream is 9 bits as shown in 表12-7.

表12-7. Read Register Request

BIT(s)

NAME

DESCRIPTION

0

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Address

A 100 indicates this is a read register request.

Identifies the address of the PHY register to be read

Indicates the end of the transfer (always 0)

1–3

4–7

8

Stop bit

For a write register request, the length of the LREQ bit stream is 17 bits as shown in 表12-8.

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表12-8. Write Register Request

BIT(s)

0

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

Request type

Address

Data

A 101 indicates this is a write register request.

1–3

4–7

8–15

16

Identifies the address of the PHY register to be written to

Gives the data that is to be written to the specified register address

Indicates the end of the transfer (always 0)

Stop bit

For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in 表12-9.

表12-9. Acceleration Control Request

BIT(s)

NAME

DESCRIPTION

0

1–3

4

Start bit

Indicates the beginning of the transfer (always 1)

Request type

Control

A 110 indicates this is an acceleration control request.

Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0

Indicates the end of the transfer (always 0)

5

Stop bIt

For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the PHY-

LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then any

pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if the

receive state is asserted while the LLC is sending the request. The LLC can then reissue the request one clock

after the next interface idle.

The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or

transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears an

isochronous request only when the serial bus has been won.

To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception

of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received

packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY

immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the

header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but

instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to

send another type of packet. After the interface is released, the LLC can proceed with another request.

The LLC can make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq,

IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request

was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted

control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are

cleared on a bus reset.

For write register requests, the PHY loads the specified data into the addressed register as soon as the request

transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the

LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the

PHY continues to attempt the transfer of the requested register until it is successful. A write or read register

request can be made at any time, including while a bus request is pending. Once a read register request is

made, the PHY ignores further read register requests until the register contents are successfully transferred to

the LLC. A bus reset does not clear a pending read register request.

The TSB41BA3F-EP includes several arbitration acceleration enhancements, which allow the PHY to improve

bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements

include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet

concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following

acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set.

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The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit the

cycle start message under certain circumstances. The acceleration control request is therefore provided to allow

the LLC temporarily to enable or disable the arbitration acceleration enhancements of the TSB41BA3F-EP

during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter

rolls over, indicating that a cycle-start message is imminent, and then re-enables the enhancements when it

receives a cycle-start message. The acceleration control request can be made at any time and is immediately

serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be re-

enabled, if the EAA bit is set.

12.2 Status Transfer

A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY

waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting

status(01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The

PHY maintains CTL = Status for the duration of the status transfer. The PHY might prematurely end a status

transfer by asserting something other than status on the CTL terminals. This occurs if a packet is received

before the status transfer completes. The PHY continues to attempt to complete the transfer until all status

information has been successfully transmitted. At least one idle cycle occurs between consecutive status

transfers.

The PHY normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed by

the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request,

or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition

where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID

register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a

received packet. The status flags are considered to have been successfully transmitted to the LLC immediately

on being sent, even if a received packet subsequently interrupts the status transfer. Register contents are

considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status

transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not

yet completed.

表12-10 shows the definition of the bits in the status transfer, and 图12-3 shows the timing.

表12-10. Status Bits

BIT(s)

NAME

DESCRIPTION

0

Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as

defined in the IEEE 1394a-2000 standard). This bit is used by the LLC in the busy/retry state machine.

1

Subaction gap

Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in

the IEEE 1394a-2000 standard). This bit is used by the LLC to detect the completion of an isochronous

cycle.

2

3

Bus reset

Interrupt

Indicates that the PHY has entered the bus reset state

Indicates that a PHY interrupt event has occurred. An interrupt event might be a configuration time-out, a

cable-power voltage falling too low, a state time-out, or a port status change.

Address

Data

This field holds the address of the PHY register whose contents are being transferred to the LLC.

This field holds the register contents.

4–7

8–15

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SYSCLK

CTL0, CTL1

D0, D1

00

01

00

(a)

(b)

S[0:1]

S[14:15]

图12-3. Status Transfer Timing

The sequence of events for a status transfer is as follows:

1. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with

the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless

interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer

occurs when only status information is to be sent. An 8-cycle (16-bit) transfer occurs when register data is to

be sent in addition to any status information.

2. Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines.

The PHY can also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin a

receive operation. The PHY asserts at least one idle cycle between consecutive status transfers.

12.3 Receive

Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting

receive on the CTL terminals and a logic 1 on each of the D bus terminals (data-on indication). The PHY

indicates the start of a packet by placing the speed code (encoded as shown in 表 12-11) on the D terminals,

followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet

has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All

received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not

included in the calculation of CRC or any other data protection mechanisms.

It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus

followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed

exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without

transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all

1s) on the D bus terminals, followed by Idle on the CTL terminals, without any speed code or data being

transferred. In all cases, in normal operation, the TSB41BA3F-EP sends at least one data-on indication before

sending the speed code or terminating the receive operation.

The TSB41BA3F-EP also transfers its own self-ID packet, transmitted during the self-ID phase of bus

initialization, to the LLC. This packet is transferred to the LLC just as any other received self-ID packet.

SYSCLK

CTL0, CTL1

10

(a)

(b)

(c)

SPD

(d)

d0

D0–D7

XX

FF (data-on)

dn

A. SPD = Speed code, see 表12-11. d0–dn = Packet data

图12-4. Normal Packet Reception Timing

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The sequence of events for a normal packet reception is as follows:

1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status

transfer operation that is in progress so that the CTL lines can change from status to receive without an

intervening idle.

2. Data-on indication. The PHY can assert the data-on indication code on the D lines for one or more cycles

preceding the speed code.

3. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines

for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle

for which the D lines are not the data-on code. If the speed code is invalid or indicates a speed higher that

which the link is capable of handling, then the link must ignore the subsequent data.

4. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on

the D lines with receive on the CTL lines for the remainder of the receive operation.

5. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

SYSCLK

CTL0, CTL1

10

00

(c)

(a)

(b)

D0–D7

XX

FF (data-on)

00

图12-5. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:

1. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status

transfer operation that is in progress so that the CTL lines can change from status to receive without an

intervening idle.

2. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

3. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

表12-11. Receive Speed Codes

D0–D7⁽¹⁾

00XX XXXX

0100 XXXX

0101 0000

11YY YYYY

DATA RATE

S100

S200

S400

data-on indication

(1) X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC.

12.4 Transmit