V62/04723-02YE [TI]
3.3-V ABT OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的3.3V ABT八路总线收发器
| 型号： | V62/04723-02YE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVTH245A-EP
3.3-V ABT OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS768A–NOVEMBER 2003–REVISED JUNE 2006
FEATURES
•
Controlled Baseline
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– One Assembly/Test Site, One Fabrication
Site
•
Enhanced Diminishing Manufacturing
Sources (DMS) Support
DB OR PW PACKAGE
(TOP VIEW)
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
V
CC
Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
)
A3
A4
•
•
•
•
•
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
A5
Supports Unregulated Battery Operation
Down to 2.7 V
A6
A7
Ioff and Power-Up 3-State Support Hot
Insertion
A8
GND
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
This octal bus transceiver is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
This device is designed for asynchronous communication between data buses. It transmits data from the A bus
to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The
output-enable (OE) input can be used to disable the device so the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVTH245A-EP
3.3-V ABT OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS768A–NOVEMBER 2003–REVISED JUNE 2006
ORDERING INFORMATION
TA
–40°C to 85°C
–55°C to 125°C
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP – PW
SSOP – DB
Tape and reel
Tape and reel
SN74LVTH245AIPWREP
SN74LVTH245AMDBREP
LH245AEP
LH245AMEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
DIR
A1
19
OE
B1
18
To Seven Other Channels
2
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SN74LVTH245A-EP
3.3-V ABT OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS768A–NOVEMBER 2003–REVISED JUNE 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
4.6
7
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
Current into any output in the low state
V
VO
VO
IO
7
V
–0.5 VCC + 0.5
V
128
64
mA
mA
mA
mA
IO
Current into any output in the high state(3)
IIK
Input clamp current
Output clamp current
VI < 0
–50
–50
69.5
83
IOK
VO < 0
DB package
PW package
θJA
Package thermal impedance(4)
Storage temperature range(5)
°C/W
°C
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Recommended Operating Conditions(1)
MIN
2.7
2
MAX UNIT
VCC
VIH
Supply voltage
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
VIL
0.8
5.5
–32
64
V
VI
V
IOH
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
IOL
∆t/∆v
∆t/∆VCC
Outputs enabled
10
200
–40
–55
I temp
85
TA
Operating free-air temperature
°C
M temp
125
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SN74LVTH245A-EP
3.3-V ABT OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS768A–NOVEMBER 2003–REVISED JUNE 2006
Electrical Characteristics
over recommended operating free-air temperature ranges (I or M) (unless otherwise noted)
M TEMP
TYP(1) MAX
I TEMP
TYP(1) MAX
PARAMETER
VIK
TEST CONDITIONS
UNIT
MIN
MIN
VCC = 2.7 V,
II = –18 mA
–1.2
–1.2
V
VCC = 2.7 V to 3.6 V, IOH = –100 µA
VCC – 0.2
VCC – 0.2
2.4
VCC = 2.7 V,
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = VCC or GND
VI = 5.5 V
2.4
2
VOH
V
V
VCC = 3 V
2
0.2
0.5
0.2
0.5
0.4
0.5
VCC = 2.7 V
VCC = 3 V
0.4
VOL
0.5
0.55
0.55
±1
VCC = 3.6 V,
±1
10
20
1
Control
inputs
VCC = 0 or 3.6 V,
10
II
VI = 5.5 V
20
µA
A or B
port(2)
VCC = 3.6 V
VI = VCC
1
VI = 0
–5
–5
Ioff
VCC = 0,
VI or VO = 0 V to 4.5 V
VI = 0.8 V
±100
µA
µA
75
75
VCC = 3 V
A or B
port
VI = 2 V
–75
–75
II(hold)
500
–750
VCC = 3.6 V,(3)
VI = 0 V to 3.6 V
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
IOZPU
IOZPD
±100
±100
±100
±100
µA
µA
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
Outputs high
VCC = 3.6 V,
0.19
5
0.19
5
ICC
IO = 0,
Outputs low
mA
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
(4)
∆ICC
0.2
0.2
Ci
VI = 3 V or 0
VO = 3 V or 0
4
9
4
9
pF
pF
Co
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) Unused terminals are at VCC or GND.
(3) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
4
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SN74LVTH245A-EP
3.3-V ABT OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS768A–NOVEMBER 2003–REVISED JUNE 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
M TEMP
VCC = 3.3 V
± 0.3 V
MIN MAX MIN
I TEMP
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC = 2.7 V
VCC = 2.7 V
MIN MAX
UNIT
MAX
6
MIN TYP(1)
MAX
3.5
3.5
5.5
5.5
5.9
5
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
1.2
1.2
1.3
1.7
2.2
2.2
5.5
5.5
7.9
7
1.2
1.2
1.3
1.7
2.2
2.2
2.3
2.1
3.2
3.4
3.5
3.4
4
4
A or B
OE
B or A
A or B
A or B
ns
ns
ns
6
9.5
7.9
7.8
7.2
7.1
6.5
6.5
5.1
7.2
7.1
OE
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
5
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SN74LVTH245A-EP
3.3-V ABT OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCBS768A–NOVEMBER 2003–REVISED JUNE 2006
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C = 50 pF
(see Note A)
t
/t
GND
L
PHZ PZH
500 Ω
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
2.7 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
t
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74LVTH245AIPWREP
SN74LVTH245AMDBREP
V62/04723-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
TSSOP
SSOP
DB
PW
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04723-02YE
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH245A-EP :
Catalog: SN74LVTH245A
Military: SN54LVTH245A
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVTH245AIPWREP TSSOP
SN74LVTH245AMDBREP SSOP
PW
DB
20
20
2000
2000
330.0
330.0
16.4
16.4
6.95
8.2
7.1
7.5
1.6
2.5
8.0
16.0
16.0
Q1
Q1
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVTH245AIPWREP
SN74LVTH245AMDBREP
TSSOP
SSOP
PW
DB
20
20
2000
2000
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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