V62/06644-05XE [TI]
CAP-FREE NMOS 250-mA LOW DROPOUT REGULATOR WITH REVERSE CURRENT PROTECTION; 无电容NMOS 250 mA低压差具有反向电流保护稳压器
| 型号： | V62/06644-05XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CAP-FREE NMOS 250-mA LOW DROPOUT REGULATOR WITH REVERSE CURRENT PROTECTION |
| 文件： | 总21页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS73201-EP, TPS73215-EP
TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
CAP-FREE NMOS 250-mA LOW DROPOUT REGULATOR
WITH REVERSE CURRENT PROTECTION
FEATURES
APPLICATIONS
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
•
•
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Optional
Optional
•
•
•
Enhanced Product-Change Notification
VIN
VOUT
IN
OUT
TPS732xx
GND NR
(1)
Qualification Pedigree
Stable with No Output Capacitor or Any Value
or Type of Capacitor
EN
•
•
Input Voltage Range: 1.7 V to 5.5 V
Optional
Typical Application Circuit for Fixed-Voltage Versions
Ultralow Dropout Voltage:
40 mV Typ at 250 mA
•
•
Excellent Load Transient Response—with or
without Optional Output Capacitor
DESCRIPTION
New NMOS Topology Provides Low Reverse
Leakage Current
The TPS732xx family of low-dropout (LDO) voltage
regulators uses a new topology: an NMOS pass
element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly
constant over all values of output current.
•
•
•
Low Noise: 30 µVRMS Typ (10 kHz to 100 kHz)
0.5% Initial Accuracy
1% Overall Accuracy (Line, Load, and
Temperature)
•
•
Less Than 1 µA Max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
The TPS732xx uses an advanced BiCMOS process
to yield high precision while delivering low dropout
voltages and low ground pin current. Current
consumption, when not enabled, is under 1 µA and
ideal for portable applications. The low output noise
(30 µVRMS with 0.1 µF CNR) is ideal for powering
VCOs. These devices are protected by thermal
shutdown and foldback current limit.
•
Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.2 V to 5 V
– Adjustable Outputs from 1.2 V to 5.5 V
– Custom Outputs Available
DCQ PACKAGE
SOT223
(TOP VIEW)
DBV PACKAGE
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
SOT23
(TOP VIEW)
TAB IS GND
OUT
N/C
1
2
3
4
8
7
6
5
IN
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
5
4
IN
GND
EN
1
2
3
OUT
N/C
N/C
EN
1
2
3
4
5
NR/FB
GND
NR/FB
IN
GND
EN
OUT
NR/FB
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS73201-EP, TPS73215-EP
TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
XX is the nominal output voltage (for example, 25 = 2.5 V, 01 = Adjustable(3)).
YYY is the package designator.
TPS732xxyyyz
Z is the package quantity.
(1) For the most current specification and package information, see the Package Option Addendum located at the end of this data sheet or
see the TI website at www.ti.com.
(2) Output voltages from 1.2 V to 4.5 V in 50-mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
(3) For fixed 1.2 V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
VIN range
–0.3 V to 6 V
–0.3 V to 6 V
VEN range
VOUT range
–0.3 V to 5.5 V
Internally limited
Indefinite
Peak output current
Output short-circuit duration
Continuous total power dissipation
Ambient temperature range, TA
Storage temperature range
ESD rating, HBM
See Dissipation Ratings Table
–55°C to 150°C
–65°C to 150°C
2 kV
ESD rating, CDM
500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
T
A ≤ 25°C
TA = 70°C
POWER
RATING
TA = 85°C
POWER
RATING
TA = 125°C
POWER
RATING
DERATING FACTOR
ABOVE TA = 25°C
BOARD
PACKAGE
RΘJC
RΘJA
POWER
RATING
Low-K(2)
High-K(3)
DBV
DBV
64°C/W 255°C/W
64°/W 180°C/W
3.9 mW/°C
5.6 mW/°C
450 mW
638 mW
275 mW
388 mW
215 mW
305 mW
58 mW
83 mW
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
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TPS73216-EP, TPS73218-EP, TPS73225-EP
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SGLS346–JUNE 2006
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TA = –55°C to +125°C), VIN = VOUT(nom) + 0.5 V(1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 µF, unless otherwise noted. Typical values are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
1.7
TYP
MAX UNIT
VIN
Input voltage range(1)
Internal reference (TPS73201)
Output voltage range (TPS73201)(2)
Nominal
5.5
1.21
V
V
V
VFB
TA = 25°C
1.198
VFB
1.2
5.5 – VDO
TA = 25°C
±0.5%
±0.5%
VOUT
Accuracy(1)
VOUT + 0.5 V ≤ VIN ≤ 5.5 V;
10 mA ≤ IOUT ≤ 250 mA
VIN, IOUT, and T
–1%
+1%
∆VOUT%/∆VIN
∆VOUT%/∆IOUT
Line regulation(1)
Load regulation
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
1 mA ≤ IOUT ≤ 250 mA
0.01
0.002
%/V
%/mA
10 mA ≤ IOUT ≤ 250 mA
0.0005
Dropout voltage(3)
(VIN = VOUT (nom) – 0.1V)
VDO
IOUT = 250 mA
40
150
600
mV
ZO(DO)
ICL
Output impedance in dropout
Output current limit
1.7 V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0 V
0.25
425
Ω
250
mA
mA
µA
ISC
Short-circuit current
Reverse leakage current(4) (–IIN
300
IREV
)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
IOUT = 10 mA (IQ)
0.1
15
550
950
1
400
IGND
Ground pin current
µA
IOUT = 250 mA
650
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5
0.02
µA
µA
FB pin current (TPS73201)
.1
.45
f = 100 Hz, IOUT = 250 mA
f = 10 kHz, IOUT = 250 mA
COUT = 10 µF, No CNR
58
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
37
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10 Hz to 100 kHz
VN
µVRMS
µs
COUT = 10 µF, CNR = 0.01 µF
VOUT = 3 V, RL = 30 Ω
COUT = 1 µF, CNR= 0.01 µF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
1.7
0
VIN
0.5
0.1
V
V
Enable low (shutdown)
Enable pin current (enabled)
VEN = 5.5 V
0.02
160
140
µA
Shutdown, Temperature increasing
Reset, Temperature decreasing
TSD
TA
Thermal shutdown temperature
Operating ambient temperature
°C
°C
–55
125
(1) Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
(2) TPS73201 is tested at VOUT = 2.5 V.
(3) VDO is not measured for the TPS73214, TPS73215, or TPS73216, since minimum VIN = 1.7 V.
(4) Fixed-voltage versions only; see the Applications section for more information.
3
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SGLS346–JUNE 2006
6
5
4
3
2
1
0
100
110
120
130
140
150
160
Continuous Tj (°C)
A. Tj = θJA × W + TA (at standard JESD 51 conditions)
Figure 1. Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
4
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TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
FUNCTIONAL BLOCK DIAGRAMS
IN
Charge
Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 2. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
OUT
R
1
R
2
Charge
Pump
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
5.0V
Short
Open
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
78.7kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
24.9kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
OUT
Current
Limit
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
R
R
19kΩ for best
1
2
GND
Ω
80k
Ω
8k
R1
R2
accuracy.
FB
Figure 3. Adjustable Voltage Version
5
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TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
PIN ASSIGNMENTS
DRB PACKAGE
3mm x 3mm SON
DBV PACKAGE
SOT23
(TOP VIEW)
DCQ PACKAGE
SOT223
(TOP VIEW)
(TOP VIEW)
OUT
N/C
1
2
3
4
8
7
6
5
IN
TAB IS GND
N/C
N/C
EN
5
4
IN
GND
EN
1
2
3
OUT
NR/FB
GND
NR/FB
1
2
3
4
5
IN
GND
EN
OUT
NR/FB
TERMINAL FUNCTIONS
TERMINAL
SOT23
(DBV)
SOT223
(DCQ)
3×3 SON
(DRB)
DESCRIPTION
NAME
PIN NO.
PIN NO.
PIN NO.
IN
1
2
1
3
8
Unregulated input supply
Ground
GND
4, Pad
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts
the regulator into shutdown mode. See the Shutdown section under Applications
Information for more details. EN can be connected to IN if not used.
EN
NR
3
4
5
4
5
3
Fixed voltage versions only—connecting an external capacitor to this pin bypasses
noise generated by the internal bandgap, reducing output noise to very low levels.
Adjustable voltage version only—this is the input to the control loop error amplifier,
and is used to set the output voltage of the device.
FB
4
5
4
2
3
1
OUT
Output of the Regulator. There are no output capacitor requirements for stability.
6
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TPS73201-EP, TPS73215-EP
TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
TYPICAL CHARACTERISTICS
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
−
_
40
C
_
+25 C
_
+25
C
_
_
+125
C
+125 C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
0.05
0.10
0.15
0.20
−
_
40
C
−
−
−
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
50
100
150
200
250
−
IOUT (mA)
VIN VOUT (V)
Figure 4.
Figure 5.
DROPOUT VOLTAGE vsOUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
80
60
40
20
0
100
80
60
40
20
0
TPS73225DBV
IOUT = 250mA
TPS73225DBV
_
+125
C
_
+25
C
−
_
40 C
−
−
25
50
0
25
50
75
100
125
0
50
100
150
200
250
_
Temperature ( C)
IOUT (mA)
Figure 6.
Figure 7.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
_
VOUT Error (%)
Worst Case dVOUT/dT (ppm/ C)
Figure 8.
Figure 9.
7
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TPS73216-EP, TPS73218-EP, TPS73225-EP
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SGLS346–JUNE 2006
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
900
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
IOUT = 250mA
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 4V
VIN = 2V
−
−
25
0
50
100
150
OUT (mA)
200
250
50
0
25
50
75
100
125
_
I
Temperature ( C)
Figure 10.
Figure 11.
CURRENT LIMIT vs VOUT
(FOLDBACK)
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
500
450
400
350
300
250
200
150
100
50
1
VENABLE = 0.5V
ICL
V
IN = VOUT + 0.5V
ISC
0.1
TPS73233
0.5
0
0.01
−
−
25
0
1.0
1.5
2.0
2.5
3.0
3.5
50
0
25
50
75
100
125
_
VOUT (V)
Temperature ( C)
Figure 12.
CURRENT LIMIT vs VIN
Figure 13.
CURRENT LIMIT vs TEMPERATURE
600
550
500
450
400
350
300
250
600
550
500
450
400
350
300
250
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
_
VIN (V)
Temperature ( C)
Figure 14.
Figure 15.
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SGLS346–JUNE 2006
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
IOUT = 100mA
COUT = Any
IOUT = 1mA
µ
COUT = 1
F
IOUT = 1mA
COUT = 10 F
µ
IO = 100mA
µ
CO = 1 F
IOUT = 1mA
COUT = Any
IOUT = 100mA
COUT = 10
Frequency = 100kHz
µ
F
C
C
= 10µF
= 0.01µF
IOUT = Any
OUT
VIN = VOUT + 1V
µ
COUT = 0
F
NR
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
−
VIN VOUT (V)
Frequency (Hz)
Figure 16.
Figure 17.
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
CNR = 0 µF
CNR = 0.01 µF
1
1
µ
COUT = 1
F
µ
COUT = 1
F
µ
COUT = 0
F
0.1
0.1
µ
COUT = 10 F
µ
COUT = 0
F
µ
COUT = 10
F
IOUT = 150mA
IOUT = 150mA
0.01
0.01
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 18.
Figure 19.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.5V
60
40
20
µ
CNR = 0.01
F
µ
COUT = 0
F
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p 10p 100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 20.
Figure 21.
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SGLS346–JUNE 2006
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted.
TPS73233
LOAD TRANSIENT RESPONSE
TPS73233
LINE TRANSIENT RESPONSE
µ
µ
µ
VIN = 3.8V
COUT = 0
F
F
F
IOUT = 250mA
50mV/tick
50mV/tick
VOUT
VOUT
VOUT
µ
COUT = 0
F
50mV/div
VOUT
COUT = 1
µ
COUT = 100
F
COUT = 10
50mV/div
1V/div
VOUT
50mV/tick
50mA/tick
dVIN
dt
5.5V
µ
= 0.5V/
s
250mA
4.5V
VIN
10mA
IOUT
µ
µ
10 s/div
10 s/div
Figure 22.
Figure 23.
TPS73233
TURN-ON RESPONSE
TPS73233
TURN-OFF RESPONSE
Ω
RL = 1k
Ω
RL = 20
VOUT
µ
COUT = 0
F
COUT = 10µF
RL = 20Ω
COUT = 1µF
RL = 20Ω
1V/div
1V/div
1V/div
1V/div
µ
COUT = 1
F
Ω
RL = 1k
RL = 20Ω
COUT = 10
µ
COUT = 0
F
µ
F
VOUT
2V
2V
VEN
0V
0V
VEN
µ
100 s/div
µ
100 s/div
Figure 24.
Figure 25.
TPS73233
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
1
6
5
4
3
2
1
0
VIN
VOUT
0.1
0.01
−
−
1
2
50ms/div
−
−
25
50
0
25
50
75
100
125
Temperature (°C)
Figure 26.
Figure 27.
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TPS73201-EP, TPS73215-EP
TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted.
TPS73201
RMS NOISE VOLTAGE vs CADJ
TPS73201
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
VOUT = 2.5V
40
µ
COUT = 0
F
Ω
R1 = 39.2k
20
10Hz < Frequency < 100kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 28.
Figure 29.
TPS73201
TPS73201
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
VOUT = 2.5V
Ω
R1 = 39.2k
CFB = 10nF
µ
COUT = 0
F
µ
COUT = 0
F
VOUT
VOUT
100mV/div
100mV/div
100mV/div
100mV/div
µ
COUT = 10 F
µ
COUT = 10
F
VOUT
VOUT
4.5V
250mA
3.5V
VIN
10mA
IOUT
µ
5
s/div
µ
10 s/div
Figure 30.
Figure 31.
11
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TPS73201-EP, TPS73215-EP
TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
APPLICATION INFORMATION
The TPS732xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS732xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and
an adjustable output version. All versions have
thermal and over-current protection, including
foldback current limit.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1 µF to 1 µF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response,
noise rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
Figure 32 shows the basic circuit connections for the
fixed voltage models. Figure 33 gives the
connections for the adjustable output version
(TPS73201).
The TPS732xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN – VOUT < 0.5 V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50 nΩF. Total ESR
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
TPS732xx
GND
EN
NR
OUTPUT NOISE
Optional bypass
capacitor to reduce
output noise.
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS732xx and
it generates approximately 32 µVRMS (10 Hz to
100 kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Figure 32. Typical Application Circuit for
Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
R2
VIN
VOUT
(1)
IN
OUT
FB
TPS732xx
R1
R2
CFB
Since the value of VREF is 1.2V, this relationship
reduces to:
EN
GND
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
Optional capacitor
reduces output noise
and improves
(2)
(R1 + R2)
×
1.204
VOUT
=
R1
for the case of no CNR
.
transient response.
An internal 27 kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10 nF, the total noise in the 10 Hz to 100 kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
Figure 33. Typical Application Circuit for
Adjustable-Voltage Versions
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 33. Sample
resistor values for common output voltages are
shown in Figure 3. For the best accuracy, make the
parallel combination of R1 and R2 approximately 19
kΩ.
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
(3)
for CNR = 10nF.
12
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TPS73201-EP, TPS73215-EP
TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
For large step changes in load current, the
TPS732xx requires a larger voltage drop from VIN to
VOUT to avoid degraded transient response. The
boundary of this transient dropout region is
approximately twice the dc dropout. Values of VIN
– VOUT above this line insure normal transient
response.
The TPS73201 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB
pin reduces output noise and improve load transient
performance.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the
rate of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
The TPS732xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT
.
The charge pump generates ~250 µV of switching
noise at ~2 MHz; however, charge-pump noise
contribution is negligible at the output of the regulator
for most values of IOUT and COUT
.
the TPS732xx can take
microseconds to return to the specified regulation
accuracy.
a couple of hundred
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE
PERFORMANCE
TRANSIENT RESPONSE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the PCB be designed with separate ground
planes for VIN and VOUT, with each ground plane
connected only at the GND pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the GND pin of
the device.
The low open-loop output impedance provided by the
NMOS pass element in
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1 µF) from the output pin to ground reduces
undershoot magnitude but increase duration. In the
a
voltage follower
adjustable version, the addition of a capacitor, CFB
from the output to the adjust pin also improves the
transient response.
,
INTERNAL CURRENT LIMIT
The TPS732xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 12 in the Typical
The TPS732xx does not have active pulldown when
the output is overvoltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if
the load current quickly drops to zero when a
capacitor is connected to the output. The duration of
overshoot can be reduced by adding a load resistor.
The overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
Characteristics section for a graph of IOUT vs VOUT
.
SHUTDOWN
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. VEN below 0.5 V (max)
turns the regulator off and drops the ground pin
current to approximately 10 nA. When shutdown
capability is not required, the Enable pin can be
connected to VIN. When a pullup resistor is used,
and operation down to 1.8 V is required, use pullup
resistor values below 50 kΩ.
(Fixed voltage version)
VOUT
dVńdt +
COUT 80kW ø RLOAD
(4)
DROPOUT VOLTAGE
The TPS732xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
13
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TPS73201-EP, TPS73215-EP
TPS73216-EP, TPS73218-EP, TPS73225-EP
TPS73230-EP, TPS73233-EP, TPS73250-EP
www.ti.com
SGLS346–JUNE 2006
(Adjustable voltage version)
35°C above the maximum expected ambient
condition of your application. This produces
a
VOUT
dVńdt +
worst-case junction temperature of 125°C at the
highest expected ambient temperature and
worst-case load.
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
(5)
REVERSE CURRENT
The internal protection circuitry of the TPS732xx has
been designed to protect against overload
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS732xx into
thermal shutdown will degrade device reliability.
The NMOS pass element of the TPS732xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass
element, the enable pin must be driven low before
the input voltage is removed. If this is not done, the
pass element may be left on due to stored charge on
the gate.
POWER DISSIPATION
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low-K and high-K
boards are shown in the Power Dissipation Ratings
table. Using heavier copper increases the
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves the heat-sink effectiveness.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current
flowing out of the IN pin due to voltage applied on
the OUT pin. There will be additional current flowing
into the OUT pin due to the 80-kΩ internal resistor
divider to ground (see Figure 2 and Figure 3).
For the TPS73201, reverse current may flow when
VFB is more than 1 V above VIN.
Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current times the voltage drop across
the output pass element (VIN to VOUT):
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately 160°C,
allowing the device to cool. When the junction
temperature cools to approximately 140°C, the
output circuitry is again enabled. Depending on
power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
PD + (VIN * VOUT) IOUT
(6)
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure
the required output voltage.
Package Mounting
Solder pad footprint recommendations for the
TPS732xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (AB-132), available from the Texas
Instruments web site at www.ti.com.
Any tendency to activate the thermal protection
circuit indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to 125°C maximum.
To estimate the margin of safety in a complete
design (including heatsink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
14
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2009
PACKAGING INFORMATION
Orderable Device
TPS73201MDBVREP
TPS73215MDBVREP
TPS73216MDBVREP
TPS73218MDBVREP
TPS73225MDBVREP
TPS73230MDBVREP
TPS73233MDBVREP
TPS73250MDBVREP
V62/06644-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06644-02XE
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06644-03XE
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06644-04XE
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06644-05XE
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06644-06XE
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06644-07XE
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/06644-08XE
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2009
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73201-EP, TPS73215-EP, TPS73216-EP, TPS73218-EP, TPS73225-EP, TPS73230-EP, TPS73233-EP,
TPS73250-EP :
Catalog: TPS73201, TPS73215, TPS73216, TPS73218, TPS73225, TPS73230, TPS73233, TPS73250
Automotive: TPS73201-Q1, TPS73225-Q1
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73201MDBVREP
TPS73215MDBVREP
TPS73216MDBVREP
TPS73218MDBVREP
TPS73225MDBVREP
TPS73230MDBVREP
TPS73233MDBVREP
TPS73250MDBVREP
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73201MDBVREP
TPS73215MDBVREP
TPS73216MDBVREP
TPS73218MDBVREP
TPS73225MDBVREP
TPS73230MDBVREP
TPS73233MDBVREP
TPS73250MDBVREP
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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相关型号：
V62/06644-06XE
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