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V62/08607-09XE [TI]

LOW QUIESCENT CURRENT, PROGRAMMABLE DELAY SUPERVISORY CIRCUIT;
V62/08607-09XE
型号： V62/08607-09XE
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

LOW QUIESCENT CURRENT, PROGRAMMABLE DELAY SUPERVISORY CIRCUIT

光电二极管
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TPS3808-EP  
www.ti.com ................................................................................................................................................. SBVS103C–APRIL 2008–REVISED NOVEMBER 2008  
LOW QUIESCENT CURRENT, PROGRAMMABLE DELAY SUPERVISORY CIRCUIT  
1
FEATURES  
SUPPORTS DEFENSE, AEROSPACE,  
AND MEDICAL APPLICATIONS  
2
•
Power-On Reset Generator With Adjustable  
Delay Time: 1.25 ms to 10 s  
•
•
•
•
Controlled Baseline  
One Assembly/Test Site  
One Fabrication Site  
Available in Military (–55°C/125°C)  
Temperature Range(1)  
•
•
•
Very Low Quiescent Current: 2.4 µA Typical  
High Threshold Accuracy: 0.5% Typical  
Fixed Threshold Voltages for Standard Voltage  
Rails from 0.9 V to 5 V and Adjustable Voltage  
Down to 0.4 V Are Available  
•
•
•
Extended Product Life Cycle  
Extended Product-Change Notification  
Product Traceability  
•
•
•
•
Manual Reset (MR) Input  
Open-Drain RESET Output  
Temperature Range: –55°C to 125°C  
Small SOT23 Package  
APPLICATIONS  
•
•
•
•
•
DSP or Microcontroller Applications  
Notebook/Desktop Computers  
PDAs/Hand-Held Products  
Portable/Battery Powered Products  
FPGA/ASIC Applications  
(1) Custom temperature ranges available  
DESCRIPTION/ORDERING INFORMATION  
The TPS3808xxx family of microprocessor supervisory circuits monitors system voltages from 0.4 V to 5.0 V,  
asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the  
manual reset (MR) pin drops to a logic low. The RESET output remains low for the user-adjustable delay time  
after the SENSE voltage and manual reset (MR) return above the respective thresholds.  
The TPS3808 uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay  
time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor,  
or can be user-adjusted between 1.25 ms and 10 s by connecting the CT pin to an external capacitor. The  
TPS3808 has a very low typical quiescent current of 2.4 µA, so it is well-suited to battery-powered applications. It  
is available in a small SOT23 package, and is fully specified over a temperature range of –55°C to +125°C (TJ).  
1.2 V  
3.3 V  
DBV (SOT-23) PACKAGE  
(TOP VIEW)  
6
5
4
1
2
3
RESET  
GND  
MR  
VDD  
VI/O VCORE  
SENSE VDD  
SENSE VDD  
SENSE  
CT  
TPS3808G12  
TPS3808G33  
DSP  
RESET  
MR  
RESET  
GPIO  
GND  
CT  
CT  
GND  
GND  
Typical Application Circuit  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008, Texas Instruments Incorporated  
TPS3808-EP  
SBVS103C–APRIL 2008–REVISED NOVEMBER 2008................................................................................................................................................. www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
PRODUCT(2)  
NOMINAL SUPPLY  
VOLTAGE(3)  
THRESHOLD VOLTAGE (VIT)  
TOP-SIDE MARKING  
TPS3808G01MDBVTEP  
TPS3808G09MDBVTEP(4)  
TPS3808G12MDBVTEP(4)  
TPS3808G125MDBVTEP(4)  
TPS3808G15MDBVTEP(4)  
TPS3808G18MDBVTEP(4)  
TPS3808G25MDBVTEP(4)  
TPS3808G30MDBVTEP(4)  
TPS3808G33MDBVREP  
TPS3808G50MDBVTEP(4)  
Adjustable  
0.9 V  
0.405 V  
0.84 V  
1.12 V  
1.16 V  
1.40 V  
1.67 V  
2.33 V  
2.79 V  
3.07 V  
4.65 V  
NXS  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
CHK  
1.2 V  
1.25 V  
1.5 V  
1.8 V  
2.5 V  
3.0 V  
3.3 V  
5.0 V  
PREVIEW  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com. Devices are shipped on tape and reel with either 250 units per reel (part numbers ending with 'TEP') or 3000  
units per reel (part numbers ending with 'REP').  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(3) Custom threshold voltages from 0.82 V to 3.3 V, 4.4 V to 5.0 V are available through the use of factory EEPROM programming.  
Minimum order quantities apply. Contact factory for details and availability.  
(4) Product Preview. Contact your TI sales representative for availability.  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating junction temperature range, unless otherwise noted.  
TPS3808  
–0.3 to 7.0  
–0.3 to VDD + 0.3  
–0.3 to 7  
5
UNIT  
V
Input voltage range, VDD  
CT voltage range, VCT  
V
Other voltage ranges: VRESET, VMR, VSENSE  
RESET pin current  
V
mA  
°C  
°C  
kV  
V
(2)  
Operating junction temperature range, TJ  
–55 to +150  
–65 to +150  
2
Storage temperature range, Tstg  
ESD rating, HBM  
ESD rating, CDM  
500  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics  
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.  
(2) As a result of the low dissipated power in this device, it is assumed that TJ = TA.  
2
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS3808-EP  
TPS3808-EP  
www.ti.com ................................................................................................................................................. SBVS103C–APRIL 2008–REVISED NOVEMBER 2008  
ELECTRICAL CHARACTERISTICS  
1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –55°C to +125°C), unless  
otherwise noted. Typical values are at TJ = +25°C.  
PARAMETER  
Input supply range  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
VDD  
1.7  
6.5  
V
VDD = 3.3 V, RESET not asserted  
MR, RESET, CT open  
2.4  
2.7  
5.0  
µA  
IDD  
Supply current (current into VDD pin)  
VDD = 6.5 V, RESET not asserted  
MR, RESET, CT open  
6.0  
µA  
1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA  
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1.0 mA  
VOL (max) = 0.2 V, IRESET = 15 µA  
0.3  
0.4  
V
V
V
VOL  
Low-level output voltage  
Power-up reset voltage(1)  
TPS3808G01  
0.8  
–2.0  
–1.7  
–2.0  
±1.0  
±0.5  
±1.0  
1.5  
+2.0  
+1.7  
+2.0  
3.0  
Negative-going input  
threshold accuracy  
VIT  
VIT ≤ 3.3 V  
%
3.3 V < VIT ≤ 5.0 V  
TPS3808G01  
Fixed versions  
VHYS  
RMR  
ISENSE  
IOH  
Hysteresis on VIT pin  
%VIT  
1.0  
2.5  
MR Internal pullup resistance  
70  
90  
kΩ  
nA  
µA  
nA  
TPS3808G01  
VSENSE = VIT  
–25  
25  
Input current at  
SENSE pin  
Fixed versions  
VSENSE = 6.5 V  
1.7  
RESET leakage current  
VRESET = 6.5 V, RESET not asserted  
VIN = 0 V to VDD  
300  
CT pin  
5
5
Input capacitance,  
any pin  
CIN  
pF  
V
Other pins  
VIN = 0 V to 6.5 V  
VIL  
VIH  
MR logic low input  
MR logic high input  
0
0.3 VDD  
VDD  
0.7 VDD  
SENSE  
VIH = 1.05 VIT, VIL = 0.95 VIT  
VIH = 0.7 VDD, VIL = 0.3 VDD  
20  
0.001  
20  
Input pulse width to  
RESET  
tw  
µs  
MR  
CT = Open  
CT = VDD  
CT = 100 pF  
CT = 180 nF  
MR to RESET  
12  
180  
0.75  
0.7  
29  
440  
1.8  
1.8  
ms  
ms  
ms  
s
300  
1.25  
1.2  
td  
RESET delay time  
Propagation delay  
See Timing Diagram  
VIH = 0.7 VDD, VIL = 0.3 VDD  
VIH = 1.05 VIT, VIL = 0.95 VIT  
150  
ns  
tpHL  
High-to-low level  
RESET delay  
SENSE to RESET  
20  
µs  
θJA  
Thermal resistance, junction-to-ambient  
290  
°C/W  
(1) The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15 µs/V.  
Copyright © 2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TPS3808-EP  
TPS3808-EP  
SBVS103C–APRIL 2008–REVISED NOVEMBER 2008................................................................................................................................................. www.ti.com  
FUNCTIONAL BLOCK DIAGRAMS  
VDD  
VDD  
VDD  
TPS3808G01  
VDD  
Adjustable Voltage  
90k  
90k  
RESET  
RESET  
MR  
MR  
SENSE  
Reset  
Logic  
Timer  
Reset  
Logic  
Timer  
R1  
−
−
SENSE  
CT  
CT  
+
+
R2  
0.4V  
VREF  
0.4V  
VREF  
Ω
R1 + R2 = 4M  
GND  
GND  
Fixed Voltage Version  
Adjustable Voltage Version  
Figure 1. Adjustable and Fixed Voltage Versions  
PIN ASSIGNMENTS  
DBV PACKAGE  
SOT23  
(TOP VIEW)  
6
5
4
1
2
3
RESET  
GND  
MR  
VDD  
SENSE  
CT  
Table 1. TERMINAL FUNCTIONS  
TERMINAL  
SOT23 (DBV)  
NAME  
PIN NO.  
DESCRIPTION  
RESET  
1
RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the  
SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains  
low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pullup  
resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher  
than VDD  
.
GND  
MR  
CT  
2
3
4
Ground  
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pullup resistor.  
Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it  
open results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced  
capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the Reset Delay Time section  
for more information.  
SENSE  
VDD  
5
6
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold  
voltage VIT, then RESET is asserted.  
Supply voltage. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin.  
4
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS3808-EP  
TPS3808-EP  
www.ti.com ................................................................................................................................................. SBVS103C–APRIL 2008–REVISED NOVEMBER 2008  
TIMING DIAGRAM  
VDD  
0.8V  
0.0V  
RESET  
tD = Reset Delay  
tD  
tD  
tD  
= Undefined State  
SENSE  
VIT + VHYS  
VIT  
MR  
0.7VDD  
0.3VDD  
Time  
Figure 2. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing  
TRUTH TABLE  
MR  
L
SENSE > VIT  
RESET  
0
1
0
1
L
L
L
H
L
H
H
Copyright © 2008, Texas Instruments Incorporated  
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5
Product Folder Link(s): TPS3808-EP  
TPS3808-EP  
SBVS103C–APRIL 2008–REVISED NOVEMBER 2008................................................................................................................................................. www.ti.com  
TYPICAL CHARACTERISTICS  
At TJ = +25°C, VDD = 3.3 V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted.  
SUPPLY CURRENT  
vs  
SUPPLY VOLTAGE  
RESET TIMEOUT PERIOD  
vs  
CT  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
100  
10  
_
+125 C  
_
+85 C  
−40°C, +25°C, +125°C  
1
_
+25 C  
0.1  
0.01  
_
−40 C  
0.001  
0
1
2
3
4
5
6
7
0.0001  
0.001  
0.01  
0.1  
1
10  
V
DD  
(V)  
µ
CT ( F)  
Figure 3.  
Figure 4.  
NORMALIZED RESET TIMEOUT PERIOD  
vs  
MAXIMUM TRANSIENT DURATION AT SENSE  
TEMPERATURE  
vs  
(CT = OPEN, CT = VDD, CT = Any)  
SENSE THRESHOLD OVERDRIVE VOLTAGE  
100  
10  
1
10  
8
6
4
RESET OCCURS  
ABOVE THE CURVE  
2
0
−2  
−4  
−6  
−8  
−10  
0
5
10  
15  
20  
25 30  
35  
45  
40  
50  
10  
30  
50  
70  
90 110 130  
−50 −30 −10  
Overdrive (%VIT)  
Temperature (°C)  
Figure 5.  
Figure 6.  
NORMALIZED SENSE THRESHOLD VOLTAGE (VIT)  
LOW-LEVEL RESET VOLTAGE  
vs  
vs  
TEMPERATURE  
RESET CURRENT  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1.0  
0.8  
0.6  
0.4  
0.2  
0
−0.2  
−0.4  
−0.6  
VDD = 1.8V  
−0.8  
−1.0  
10  
30  
50  
70  
90 110 130  
−50 −30 −10  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
RESET Current (mA)  
Temperature (°C)  
Figure 7.  
Figure 8.  
6
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS3808-EP  
 
TPS3808-EP  
www.ti.com ................................................................................................................................................. SBVS103C–APRIL 2008–REVISED NOVEMBER 2008  
TYPICAL CHARACTERISTICS (continued)  
At TJ = +25°C, VDD = 3.3 V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted.  
LOW-LEVEL RESET VOLTAGE  
vs  
RESET CURRENT  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
VDD = 3.3V  
VDD = 6.5V  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
RESET Current (mA)  
Figure 9.  
Copyright © 2008, Texas Instruments Incorporated  
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7
Product Folder Link(s): TPS3808-EP  
TPS3808-EP  
SBVS103C–APRIL 2008–REVISED NOVEMBER 2008................................................................................................................................................. www.ti.com  
DEVICE OPERATION  
supply line can be used to allow the reset signal for  
The TPS3808 microprocessor supervisory product  
the microprocessor to have a voltage higher than VDD  
family is designed to assert a RESET signal when  
(up to 6.5 V). The pullup resistor should be no  
either the SENSE pin voltage drops below VIT or the  
smaller than 10 kΩ as a result of the finite impedance  
manual reset (MR) is driven low. The RESET output  
of the RESET line.  
remains asserted for a user-adjustable time after both  
the manual reset (MR) and SENSE voltages return  
above the respective thresholds. A broad range of  
SENSE INPUT  
voltage threshold and reset delay time adjustments  
are available, allowing these devices to be used in a  
wide array of applications. Reset threshold voltages  
can be factory-set from 0.82 V to 3.3 V or from 4.4 V  
to 5.0 V, while the TPS3808G01 can be set to any  
voltage above 0.405 V using an external resistor  
divider. Two preset delay times are also  
user-selectable: connecting the CT pin to VDD results  
in a 300ms reset delay, while leaving the CT pin open  
yields a 20-ms reset delay. In addition, connecting a  
capacitor between CT and GND allows the designer  
to select any reset delay period from 1.25 ms to 10 s.  
The SENSE input provides a terminal at which any  
system voltage can be monitored. If the voltage on  
this pin drops below VIT, then RESET is asserted.  
The comparator has a built-in hysteresis to ensure  
smooth RESET assertions and de-assertions. It is  
good analog design practice to put a 1-nF to 10-nF  
bypass capacitor on the SENSE input to reduce  
sensitivity to transients and layout parasitics.  
The TPS3808G01 can be used to monitor any  
voltage rail down to 0.405 V using the circuit shown  
in Figure 11.  
VIN  
VOUT  
RESET OUTPUT  
VDD  
VIT¢ = (1 + R1 ) 0.405  
A typical application of the TPS3808G25 used with  
the OMAP1510 processor is shown in Figure 10. The  
open-drain RESET output is typically connected to  
the RESET input of a microprocessor. A pullup  
resistor must be used to hold this line high when  
RESET is not asserted. The RESET output is  
undefined for voltage below 0.8 V, but this is normally  
not a problem since most microprocessors do not  
function below this voltage. RESET remains high  
(unasserted) as long as SENSE is above its threshold  
(VIT) and the manual reset (MR) is logic high. If either  
SENSE falls below VIT or MR is driven low, RESET is  
asserted, driving the RESET pin to a low impedance.  
R2  
R1  
TPS3808G01  
SENSE  
RESET  
GND  
R2  
1nF  
Figure 11. Using the TPS3808G01 to Monitor a  
User-Defined Threshold Voltage  
MANUAL RESET (MR) INPUT  
2.5V  
The manual reset (MR) input allows a processor or  
other logic circuits to initiate a reset. A logic low  
(0.3 VDD) on MR causes RESET to assert. After MR  
returns to a logic high and SENSE is above its reset  
threshold, RESET is de-asserted after the user  
defined reset delay expires. Note that MR is internally  
tied to VDD using a 90-kΩ resistor so this pin can be  
left unconnected if MR will not be used.  
V
SENSE  
V
DD  
DDSHV 1, 3, 6, 7, 9  
Ω
1M  
TPS3808G25  
OMAP1510  
MR  
RESET  
RESPWRON  
GND  
CT  
GND  
See Figure 12 for how MR can be used to monitor  
multiple system voltages. Note that if the logic signal  
driving MR does not go fully to VDD, there will be  
some additional current draw into VDD as a result of  
the internal pullup resistor on MR. To minimize  
current draw, a logic-level FET can be used as  
illustrated in Figure 13.  
Figure 10. Typical Application of the TPS3808  
with an OMAP Processor  
Once MR is again logic high and SENSE is above VIT  
+ VHYS (the threshold hysteresis), a delay circuit is  
enabled which holds RESET low for a specified reset  
delay period. Once the reset delay has expired, the  
RESET pin goes to a high impedance state. The  
pullup resistor from the open-drain RESET to the  
8
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TPS3808-EP  
 
 
TPS3808-EP  
www.ti.com ................................................................................................................................................. SBVS103C–APRIL 2008–REVISED NOVEMBER 2008  
affected by the choice of resistor. Figure 14b shows a  
1.2V  
3.3V  
fixed 20-ms delay time by leaving the CT pin open.  
Figure 14c shows a ground referenced capacitor  
connected to CT for a user-defined program time  
between 1.25 ms and 10 s.  
V
V
CORE  
SENSE  
V
SENSE V  
DD  
I/O  
DD  
The capacitor CT should be ≥ 100 pF nominal value  
in order for the TPS3808xxx to recognize that the  
capacitor is present. The capacitor value for a given  
delay time can be calculated using the following  
equation:  
TPS3808G12  
TPS3808G33  
DSP  
RESET  
MR  
RESET  
GPIO  
GND  
CT  
CT  
GND  
GND  
*3  
ƪ
ƫ
CT (nF) + tD (s)*0.5   10 (s)   175  
(1)  
The reset delay time is determined by the time it  
takes an on-chip precision 220-nA current source to  
charge the external capacitor to 1.23 V. When a  
RESET is asserted the capacitor is discharged. When  
the RESET conditions are cleared, the internal  
current source is enabled and begins to charge the  
external capacitor. When the voltage on this capacitor  
reaches 1.23 V, RESET is deasserted. Note that a  
low-leakage type capacitor such as a ceramic should  
be used, and that stray capacitance around this pin  
may cause errors in the reset delay time.  
Figure 12. Using MR to Monitor Multiple System  
Voltages  
3.3V  
V DD SENSE  
90kW  
MR  
TPS3808xxx  
IMMUNITY TO SENSE PIN VOLTAGE  
TRANSIENTS  
GND  
The TPS3808 is relatively immune to short negative  
transients on the SENSE pin. Sensitivity to transients  
is dependent on threshold overdrive, as shown in the  
Maximum Transient Duration at Sense vs Sense  
Threshold Overdrive Voltage graph (Figure 6) in the  
Typical Characteristics section.  
Figure 13. Using an External MOSFET to Minimize  
IDD When MR Signal Does Not Go to VDD  
SELECTING THE RESET DELAY TIME  
The TPS3808 has three options for setting the  
RESET delay time as shown in Figure 14. Figure 14a  
shows the configuration for a fixed 300-ms typical  
delay time by tying CT to VDD; a resistor from 40 kΩ  
to 200 kΩ must be used. Supply current is not  
3.3V  
3.3V  
3.3V  
SENSE VDD  
SENSE VDD  
SENSE VDD  
Ω
50k  
TPS3808G33  
TPS3808G33  
TPS3808G33  
RESET  
CT RESET  
CT RESET  
CT  
CT  
−3  
Delay (s) = C (nF) + 0.5 x 10 (s)  
T
300ms Delay  
20ms Delay  
175  
(b)  
(a)  
(c)  
Figure 14. Configuration Used to Set the RESET Delay Time  
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Product Folder Link(s): TPS3808-EP  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
2-Feb-2009  
PACKAGING INFORMATION  
Orderable Device  
TPS3808G01MDBVTEP  
TPS3808G33MDBVREP  
V62/08607-01XE  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOT-23  
DBV  
6
6
6
6
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOT-23  
SOT-23  
SOT-23  
DBV  
DBV  
DBV  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
V62/08607-09XE  
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS3808G01MDBVTEP SOT-23  
TPS3808G33MDBVREP SOT-23  
DBV  
DBV  
6
6
250  
179.0  
179.0  
8.4  
8.4  
3.2  
3.2  
3.2  
3.2  
1.4  
1.4  
4.0  
4.0  
8.0  
8.0  
Q3  
Q3  
3000  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS3808G01MDBVTEP  
TPS3808G33MDBVREP  
SOT-23  
SOT-23  
DBV  
DBV  
6
6
250  
203.0  
203.0  
203.0  
203.0  
35.0  
35.0  
3000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information  
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a  
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual  
property of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied  
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive  
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional  
restrictions.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all  
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not  
responsible or liable for any such statements.  
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably  
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing  
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and  
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products  
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be  
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in  
such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military  
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at  
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are  
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
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www.ti.com/consumer-apps  
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dsp.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
www.ti.com/security  
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Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
Medical  
Security  
Logic  
Space, Avionics and Defense www.ti.com/space-avionics-defense  
Power Mgmt  
power.ti.com  
Transportation and  
Automotive  
www.ti.com/automotive  
Microcontrollers  
RFID  
microcontroller.ti.com  
www.ti-rfid.com  
Video and Imaging  
Wireless  
www.ti.com/video  
www.ti.com/wireless-apps  
RF/IF and ZigBee® Solutions www.ti.com/lprf  
TI E2E Community Home Page  
e2e.ti.com  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2011, Texas Instruments Incorporated  

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