V62/08626-01XE [TI]
增强型产品超低功耗 NTSC/PAL/SECAM 视频解码器 | PBS | 32 | -55 to 125;
| 型号： | V62/08626-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品超低功耗 NTSC/PAL/SECAM 视频解码器 | PBS | 32 | -55 to 125 消费电路 商用集成电路 解码器 转换器 色度信号转换器 |
| 文件： | 总79页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES213
May 2008
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
SLES213–MAY 2008
www.ti.com
Contents
1
2
TVP5150AM1 Features.......................................................................................................... 7
Features....................................................................................................................... 7
Introduction......................................................................................................................... 8
1.1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Description.................................................................................................................... 8
Applications................................................................................................................... 9
Trademarks................................................................................................................... 9
Document Conventions ..................................................................................................... 9
Ordering Information ........................................................................................................ 9
Functional Block Diagram................................................................................................. 10
Terminal Assignments ..................................................................................................... 11
3
Functional Description........................................................................................................ 14
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Analog Front End........................................................................................................... 14
Composite Processing Block Diagram .................................................................................. 14
Adaptive Comb Filtering................................................................................................... 15
Color Low-Pass Filter...................................................................................................... 15
Luminance Processing .................................................................................................... 16
Chrominance Processing.................................................................................................. 16
Timing Processor........................................................................................................... 16
VBI Data Processor (VDP)................................................................................................ 16
VBI FIFO and Ancillary Data in Video Stream.......................................................................... 17
3.10 Raw Video Data Output ................................................................................................... 18
3.11 Output Formatter ........................................................................................................... 18
3.12 Synchronization Signals................................................................................................... 18
3.13 Active Video (AVID) Cropping ............................................................................................ 20
3.14 Embedded Syncs........................................................................................................... 21
3.15 I2C Host Interface .......................................................................................................... 22
3.15.1 I2C Write Operation.............................................................................................. 23
3.15.2 I2C Read Operation ............................................................................................. 23
3.15.2.1 Read Phase 1 ....................................................................................... 24
3.15.2.2 Read Phase 2 ....................................................................................... 24
3.15.2.3 I2C Timing Requirements .......................................................................... 25
3.16 Clock Circuits ............................................................................................................... 25
3.17 Genlock Control (GLCO) and RTC ...................................................................................... 25
3.17.1 GLCO Interface .................................................................................................. 26
3.17.2 RTC Mode........................................................................................................ 26
3.18 Reset and Power Down ................................................................................................... 27
3.19 Internal Control Registers ................................................................................................. 27
3.20 Register Definitions ........................................................................................................ 30
3.20.1 Video Input Source Selection 1 Register..................................................................... 30
3.20.2 Analog Channel Controls Register ............................................................................ 30
3.20.3 Operation Mode Controls Register............................................................................ 31
3.20.4 Miscellaneous Controls Register .............................................................................. 32
3.20.5 Autoswitch Mask Register...................................................................................... 35
3.20.6 Color Killer Threshold Control Register....................................................................... 35
3.20.7 Luminance Processing Control 1 Register ................................................................... 36
3.20.8 Luminance Processing Control 2 Register ................................................................... 37
3.20.9 Brightness Control Register.................................................................................... 37
3.20.10 Color Saturation Control Register ............................................................................ 38
3.20.11 Hue Control Register........................................................................................... 38
3.20.12 Contrast Control Register...................................................................................... 38
2
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3.20.13 Outputs and Data Rates Select Register.................................................................... 39
3.20.14 Luminance Processing Control 3 Register .................................................................. 40
3.20.15 Configuration Shared Pins Register.......................................................................... 41
3.20.16 Active Video Cropping Start Pixel MSB Register........................................................... 41
3.20.17 Active Video Cropping Start Pixel LSB Register ........................................................... 42
3.20.18 Active Video Cropping Stop Pixel MSB Register........................................................... 42
3.20.19 Active Video Cropping Stop Pixel LSB Register............................................................ 42
3.20.20 Genlock and RTC Register.................................................................................... 43
3.20.21 Horizontal Sync Start Register................................................................................ 43
3.20.22 Vertical Blanking Start Register............................................................................... 44
3.20.23 Vertical Blanking Stop Register............................................................................... 45
3.20.24 Chrominance Control 1 Register ............................................................................. 45
3.20.25 Chrominance Control 2 Register ............................................................................. 46
3.20.26 Interrupt Reset Register B..................................................................................... 47
3.20.27 Interrupt Enable Register B ................................................................................... 48
3.20.28 Interrupt Configuration Register B............................................................................ 49
3.20.29 Video Standard Register....................................................................................... 49
3.20.30 Cb Gain Factor Register ....................................................................................... 50
3.20.31 Cr Gain Factor Register........................................................................................ 50
3.20.32 Macrovision On Counter Register ............................................................................ 50
3.20.33 Macrovision Off Counter Register ............................................................................ 50
3.20.34 656 Revision Select Register ................................................................................. 50
3.20.35 MSB of Device ID Register.................................................................................... 51
3.20.36 LSB of Device ID Register..................................................................................... 51
3.20.37 ROM Major Version Register.................................................................................. 51
3.20.38 ROM Minor Version Register.................................................................................. 51
3.20.39 Vertical Line Count MSB Register............................................................................ 51
3.20.40 Vertical Line Count LSB Register............................................................................. 52
3.20.41 Interrupt Status Register B .................................................................................... 52
3.20.42 Interrupt Active Register B..................................................................................... 53
3.20.43 Status Register #1.............................................................................................. 53
3.20.44 Status Register 2 ............................................................................................... 54
3.20.45 Status Register 3 ............................................................................................... 54
3.20.46 Status Register 4 ............................................................................................... 55
3.20.47 Status Register 5 ............................................................................................... 55
3.20.48 Closed Caption Data Registers ............................................................................... 56
3.20.49 WSS Data Registers ........................................................................................... 56
3.20.50 VPS Data Registers ............................................................................................ 57
3.20.51 VITC Data Registers ........................................................................................... 57
3.20.52 VBI FIFO Read Data Register ................................................................................ 57
3.20.53 Teletext Filter and Mask Registers ........................................................................... 58
3.20.54 Teletext Filter Control Register ............................................................................... 59
3.20.55 Interrupt Status Register A .................................................................................... 60
3.20.56 Interrupt Enable Register A ................................................................................... 61
3.20.57 Interrupt Configuration Register A............................................................................ 62
3.20.58 VDP Configuration RAM Register ............................................................................ 62
3.20.59 VDP Status Register ........................................................................................... 64
3.20.60 FIFO Word Count Register .................................................................................... 65
3.20.61 FIFO Interrupt Threshold Register............................................................................ 65
3.20.62 FIFO Reset Register ........................................................................................... 65
3.20.63 Line Number Interrupt Register ............................................................................... 65
3.20.64 Pixel Alignment Registers ..................................................................................... 66
3.20.65 FIFO Output Control Register................................................................................. 66
Contents
3
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
SLES213–MAY 2008
www.ti.com
3.20.66 Full Field Enable Register ..................................................................................... 66
3.20.67 Line Mode Registers ........................................................................................... 67
3.20.68 Full Field Mode Register....................................................................................... 68
Electrical Specifications...................................................................................................... 69
4
4.1
4.2
4.3
Absolute Maximum Ratings............................................................................................... 69
Recommended Operating Conditions ................................................................................... 69
Electrical Characteristics .................................................................................................. 70
4.3.1
4.3.2
4.3.3
4.3.4
DC Electrical Characteristics................................................................................... 70
Analog Electrical Characteristics .............................................................................. 70
Clocks, Video Data, Sync Timing ............................................................................. 71
I2C Host Port Timing ............................................................................................ 72
4.4
Estimated Device Life...................................................................................................... 72
5
6
Example Register Settings .................................................................................................. 73
5.1
Example 1 ................................................................................................................... 73
5.1.1
Assumptions...................................................................................................... 73
Recommended Settings ........................................................................................ 73
5.1.2
5.2
Example 2 ................................................................................................................... 74
5.2.1
5.2.2
Assumptions...................................................................................................... 74
Recommended Settings ........................................................................................ 74
Application Information....................................................................................................... 75
Application Example ....................................................................................................... 75
6.1
4
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Ultralow-Power NTSC/PAL/SECAM Video Decoder
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List of Figures
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
4-1
4-2
4-3
6-1
Functional Block Diagram........................................................................................................ 10
Terminal Diagrams................................................................................................................ 11
Composite Processing Block Diagram (Comb/Trap Filter Bypassed for SECAM) ....................................... 15
8-Bit 4:2:2, Timing With 2× Pixel Clock (SCLK) Reference ................................................................. 19
Horizontal Synchronization Signals............................................................................................. 20
AVID Application .................................................................................................................. 21
Reference Clock Configurations ................................................................................................ 25
GLCO Timing ...................................................................................................................... 26
RTC Timing ........................................................................................................................ 26
Configuration Shared Pins ....................................................................................................... 34
Horizontal Sync.................................................................................................................... 44
Clocks, Video Data, and Sync Timing.......................................................................................... 71
I2C Host Port Timing.............................................................................................................. 72
TVP5150AM1 Estimated Device Life at Elevated Temperatures .......................................................... 72
Application Example .............................................................................................................. 75
List of Figures
5
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
SLES213–MAY 2008
www.ti.com
List of Tables
2-1
Terminal Functions................................................................................................................ 12
3-1
Data Types Supported by VDP ................................................................................................. 16
Ancillary Data Format and Sequence .......................................................................................... 17
Summary of Line Frequencies, Data Rates, and Pixel Counts ............................................................. 18
EAV and SAV Sequence......................................................................................................... 21
Write-Address Selection.......................................................................................................... 22
I2C Terminal Description ......................................................................................................... 22
Read Address Selection.......................................................................................................... 23
Reset and Power-Down Modes ................................................................................................. 27
Register Summary ................................................................................................................ 27
Analog Channel and Video Mode Selection................................................................................... 30
Digital Output Control............................................................................................................. 33
Clock Delays (SCLKs)............................................................................................................ 44
VBI Configuration RAM for Signals With Pedestal ........................................................................... 63
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
Macrovision is a trademark of Macrovision Corporation.
List of Tables
6
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1
TVP5150AM1 Features
1.1 Features
•
Controlled Baseline
•
•
Complementary 4-Line (3-H Delay) Adaptive
Comb Filters for Both Cross-Luminance and
Cross-Chrominance Noise Reduction
–
–
–
One Assembly Site
One Test Site
One Fabrication Site
Patented Architecture for Locking to Weak,
Noisy, or Unstable Signals
•
•
Extended Temperature Performance of –55°C
to 125°C
•
•
Single 14.31818-MHz Crystal for All Standards
Internal Phase-Locked Loop (PLL) for
Line-Locked Clock and Sampling
Enhanced Diminishing Manufacturing Sources
(DMS) Support
•
•
Subcarrier Genlock Output for Synchronizing
Color Subcarrier External Encoder
•
•
•
Enhanced Product-Change Notification
Qualification Pedigree(1)
Standard Programmable Video Output Formats
Accepts NTSC (M, 4.43), PAL (B, D, G, H, I, M,
N), and SECAM (B, D, G, K, K1, L) Video Data
–
ITU-R BT.656, 8-Bit 4:2:2 With Embedded
Syncs
•
•
Supports ITU-R BT.601 Standard Sampling
–
8-Bit 4:2:2 With Discrete Syncs
High-Speed 9-Bit Analog-to-Digital Converter
(ADC)
•
•
Macrovision™ Copy Protection Detection
Advanced Programmable Video Output
Formats
•
•
Two Composite Inputs or One S-Video Input
Fully Differential CMOS Analog Preprocessing
Channels With Clamping and Automatic Gain
Control (AGC) for Best Signal-to-Noise (S/N)
Performance
–
2× Oversampled Raw Vertical Blanking
Interval (VBI) Data During Active Video
–
Sliced VBI Data During Horizontal Blanking
or Active Video
•
•
•
•
Ultralow Power Consumption
32-Terminal TQFP Package
Power-Down Mode: <1 mW
•
VBI Modes Supported
–
–
Teletext (NABTS, WST)
Closed-Caption Decode With FIFO and
Extended Data Services (EDS)
Brightness, Contrast, Saturation, Hue, and
Sharpness Control Through I2C
–
–
–
Wide Screen Signaling, Video Program
System, CGMS, Vertical Interval Time Code
Gemstar 1x/2x Electronic Program Guide
Compatible Mode
Custom Configuration Mode That Allows
User to Program Slice Engine for Unique
VBI Data Signals
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
•
•
Power-On Reset
Military Temperature Range (TVP5150AM1):
–55°C to 125°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
SLES213–MAY 2008
www.ti.com
2
Introduction
2.1 Description
The TVP5150AM1 device is an ultralow-power NTSC/PAL/SECAM video decoder. Available in a
space-saving 32-terminal TQFP package, the TVP5150AM1 decoder converts NTSC, PAL, and SECAM
video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized architecture
of the TVP5150AM1 decoder allows for ultralow power consumption. The decoder consumes 115 mW of
power in typical operation and consumes less than 1 mW in power-down mode, considerably increasing
battery life in portable applications. The decoder uses just one crystal for all supported standards. The
TVP5150AM1 decoder can be programmed using an I2C serial interface. The decoder uses a 1.8-V
supply for its analog and digital supplies and a 3.3-V supply for its I/O.
The TVP5150AM1 decoder converts baseband analog video into digital YCbCr 4:2:2 component video.
Composite and S-video inputs are supported. The TVP5150AM1 decoder includes one 9-bit
analog-to-digital converter (ADC) with 2× sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from
the 14.31818-MHz crystal or oscillator input) and is line locked. The output formats can be 8-bit 4:2:2 or
8-bit ITU-R BT.656 with embedded synchronization.
The TVP5150AM1 decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or
unstable signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream
video encoders.
Complementary four-line adaptive comb filtering is available for both the luma and chroma data paths to
reduce both cross-luma and cross-chroma artifacts; a chroma trap filter is also available.
Video characteristics including hue, contrast, brightness, saturation, and sharpness may be programmed
using the industry standard I2C serial interface. The TVP5150AM1 decoder generates synchronization,
blanking, lock, and clock signals in addition to digital video outputs. The TVP5150AM1 decoder includes
methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor slices,
parses, and performs error checking on teletext, closed caption, and other data in several formats.
The TVP5150AM1 decoder detects copy-protected input signals according to the Macrovision™ standard
and detects Type 1, 2, 3, and colorstripe pulses.
The main blocks of the TVP5150AM1 decoder include:
•
•
•
•
•
•
•
•
•
•
Robust sync detector
ADC with analog processor
Y/C separation using four-line adaptive comb filter
Chrominance processor
Luminance processor
Video clock/timing processor and power-down control
Output formatter
I2C interface
VBI data processor
Macrovision detection for composite and S-video
8
Introduction
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2.2 Applications
The following is a partial list of suggested applications:
•
•
•
•
•
•
•
•
•
Digital televisions
PDAs
Notebook PCs
Cell phones
Video recorder/players
Internet appliances/web pads
Handheld games
Surveillance
Portable navigation
2.3 Trademarks
TI and MicroStar Junior are trademarks of Texas Instruments.
Macrovision is a trademark of Macrovision Corporation.
CompactPCI is a trademark of PICMG – PCI Industrial Computer Manufacturers Group, Inc.
Intel is a trademark of Intel Corporation.
Other trademarks are the property of their respective owners.
2.4 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are:
•
•
•
•
•
To identify a binary number or field, a lower case b follows the numbers. For example, 000b is a 3-bit
binary field.
To identify a hexadecimal number or field, a lower case h follows the numbers. For example, 8AFh is a
12-bit hexadecimal field.
All other numbers that appear in this document that do not have either a b or h following the number
are assumed to be decimal format.
If the signal or terminal name has a bar above the name (for example, RESETB), this indicates the
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
RSVD indicates that the referenced item is reserved.
2.5 Ordering Information
TA
PACKAGE(1)
Reel of 1000
ORDERABLE PART NUMBER(2)
TOP-SIDE MARKING
5150MEP
–55°C to 125°C
TQFP - PBS
TVP5150AM1MPBSREP
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
SLES213–MAY 2008
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2.6 Functional Block Diagram
Macrovision
Detection
Luminance
Processing
AIP1A
AIP1B
M
U
X
A/D
YOUT[7:0]
YCbCr 8-Bit
4:2:2
AGC
Chrominance
Processing
VBI/Data Slicer
SCL
SDA
I2C
Interface
Host Processor
PDN
XTAL1
XTAL2
FID/GLCO
VSYNC/PALI
INTERQ/GPCL/VBLK
HSYNC
PCLK/SCLK
AVID
Figure 2-1. Functional Block Diagram
10
Introduction
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2.7 Terminal Assignments
The TVP5150AM1 video decoder bridge is packaged in a 32-terminal TQFP package. Figure 2-2 shows
the terminal diagram for the packages. Table 2-1 gives a description of the terminals.
TQFP PACKAGE
(TOP VIEW)
32 31 30 29 28 27 26 25
AIP1A
AIP1B
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VSYNC/PALI
FID/GLCO
SDA
PLL_AGND
PLL_AVDD
XTAL1/OSC
XTAL2
SCL
DVDD
DGND
AGND
YOUT0
YOUT1
RESETB
9 10 11 12 13 14 15 16
Figure 2-2. Terminal Diagrams
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Table 2-1. Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
PBS
Analog Section
AGND
7
1
I
I
Substrate. Connect to analog ground.
Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input
range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the
desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1).
AIP1A
AIP1B
Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input
range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the
desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1).
2
I
CH_AGND
CH_AVDD
PLL_AGND
PLL_AVDD
31
32
3
I
I
I
I
Analog ground
Analog supply. Connect to 1.8-V analog supply.
PLL ground. Connect to analog ground.
PLL supply. Connect to 1.8-V analog supply.
4
A/D reference ground. Connect to analog ground through a 1-µF capacitor. Also, it is
recommended to connect directly to REFP through a 1-µF capacitor (see Figure 6-1).
REFM
30
29
I
I
REFP
A/D reference supply. Connect to analog ground through a 1-µF capacitor (see Figure 6-1).
Digital Section
Active video indicator. This signal is high during the horizontal active time of the video
output. AVID toggling during vertical blanking intervals is controlled by bit 2 of the active
video cropping start pixel LSB register at address 12h (see Section 3.20.17).
AVID
26
O
DGND
DVDD
19
20
I
I
Digital ground
Digital supply. Connect to 1.8-V digital supply.
FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1
indicates the odd field.
FID/GLCO
HSYNC
23
25
O
O
GLCO: This serial output carries color PLL information. A slave device can decode the
information to allow chroma frequency control from the TVP5150AM1 decoder. Data is
transmitted at the SCLK rate in Genlock mode. In RTC mode, SCLK/4 is used.
Horizontal synchronization
INTREQ: Interrupt request output
GPCL/VBLK: General-purpose control logic. This terminal has two functions:
INTREQ/GPCL/
VBLK
•
GPCL: General-purpose output. In this mode the state of GPCL is directly programmed
via I2C.
27
I/O
•
VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical
blanking interval of the output video. The beginning and end times of this signal are
programmable via I2C.
IO_DVDD
10
9
I
Digital supply. Connect to 3.3 V.
PCLK/SCLK
O
System clock at either 1× or 2× the frequency of the pixel clock.
Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value
of the registers.
PDN
28
8
I
I
Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it
resets all the registers and restarts the internal microprocessor.
RESETB
SCL
SDA
21
22
I/O
I/O
I2C serial clock (open drain)
I2C serial data (open drain)
VSYNC: Vertical synchronization signal
PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator:
1 = Noninverted line
VSYNC/PALI
24
O
0 = Inverted line
External clock reference. The user may connect XTAL1 to an oscillator or to one terminal of
a crystal oscillator. The user may connect XTAL2 to the other terminal of the crystal
oscillator or not connect XTAL2 at all. One single 14.31818-MHz crystal or oscillator is
needed for ITU-R BT.601 sampling for all supported standards.
XTAL1/OSC
XTAL2
5
6
I/O
12
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Table 2-1. Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
PBS
12
13
14
15
16
17
18
YOUT[6:0]
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync
I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown register is
needed (>1 kΩ) to program the terminal to the desired address.
1 = Address is 0xBA
YOUT7/I2CSEL
11
I/O
0 = Address is 0xB8
YOUT7: Most-significant bit (MSB) of output decoded ITU-R BT.656 output/YCbCr 4:2:2
output
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Ultralow-Power NTSC/PAL/SECAM Video Decoder
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3
Functional Description
3.1 Analog Front End
The TVP5150AM1 decoder has an analog input channel that accepts two ac-coupled video inputs. The
decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is
needed for most input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination
before the input to the device is 75 Ω. See the application diagram in Figure 6-1 for the recommended
configuration. The two analog input ports can be connected as follows:
•
•
Two selectable composite video inputs or
One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the automatic gain control (AGC) circuit work together to
make sure that the input signal is amplified sufficiently to ensure the proper input range for the ADC.
The ADC has nine bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the
ADC comes from the PLL.
3.2 Composite Processing Block Diagram
The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space.
Figure 3-1 shows the basic architecture of this processing block.
Figure 3-1 shows the luminance/chrominance (Y/C) separation process in the TVP5150AM1 decoder. The
composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color
difference signals Cb and Cr. Cb and Cr are then low pass (LP) filtered to achieve the desired bandwidth
and to reduce crosstalk.
An adaptive four-line comb filter separates CbCr from Y. Chroma is remodulated through another
quadrature modulator and subtracted from the line-delayed composite video to generate luma. Contrast,
brightness, hue, saturation, and sharpness (using the peaking filter) are programmable via I2C.
The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.
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Gain Factor
Peak
Detector
Bandpass
X
Peaking
Composite
Delay
+
Delay
Y
Line
Delay
-
Y
Quadrature
Modulation
Contrast
Brightness
Saturation
Adjust
Cb
Cr
SECAM Luma
Notch
Filter
Cb
Cr
Notch
Filter
SECAM Color
Demodulation
Color
LPF ↓ 2
Composite
Cb
4-Line
Adaptive
Comb
Burst
Accumulator
(Cb)
LP
Filter
Delay
Filter
LP
Filter
Color
LPF ↓ 2
Quadrature
Modulation
Delay
Composite
Cr
Burst
Accumulator
(Cr)
Figure 3-1. Composite Processing Block Diagram (Comb/Trap Filter Bypassed for SECAM)
3.3 Adaptive Comb Filtering
The four-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is
bypassed in the luma path, chroma notch filters are used. TI's patented adaptive four-line comb filter
algorithm reduces artifacts such as hanging dots at color boundaries and detects and properly handles
false colors in high-frequency luminance images such as a multiburst pattern or circle pattern.
3.4 Color Low-Pass Filter
In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true
in case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the
bandwidth of the Cb/Cr signals.
Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input
image. See Section 3.20.25, Chrominance Control #2 Register, for the response of these filters. The filters
have three options that allow three different frequency responses based on the color frequency
characteristics of the input video.
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3.5 Luminance Processing
The luma component is derived from the composite signal by subtracting the remodulated chroma
information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in
the color processing chain. The luma information is then fed into the peaking circuit, which enhances the
high frequency components of the signal, thus improving sharpness.
3.6 Chrominance Processing
For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals
then pass through the gain control stage for chroma saturation adjustment. An adaptive comb filter is
applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts.
An automatic color killer circuit is also included in this block. The color killer suppresses the chroma
processing when the color burst of the video signal is weak or not present. The SECAM standard is similar
to PAL except for the modulation of color, which is FM instead of QAM.
3.7 Timing Processor
The timing processor is a combination of hardware and software running in the internal microprocessor
that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the
analog front end, vertical sync detection, and Macrovision detection.
3.8 VBI Data Processor (VDP)
The TVP5150AM1 VDP slices various data services such as teletext (WST, NABTS), closed caption (CC),
wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable
standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored only
in a FIFO. Table 3-1 lists a summary of the types of VBI data supported according to the video standard. It
supports ITU-R BT. 601 sampling for each.
Table 3-1. Data Types Supported by VDP
LINE MODE REGISTER
(D0h–FCh) BITS [3:0]
NAME
WST SECAM
DESCRIPTION
0000b
Teletext, SECAM
0001b
WST PAL B
WST PAL C
WST, NTSC B
NABTS, NTSC C
NABTS, NTSC D
CC, PAL
Teletext, PAL, System B
Teletext, PAL, System C
Teletext, NTSC, System B
Teletext, NTSC, System C
Teletext, NTSC, System D (Japan)
Closed caption PAL
0010b
0011b
0100b
0101b
0110b
0111b
CC, NTSC
Closed caption NTSC
Wide-screen signal, PAL
Wide-screen signal, NTSC
Vertical interval timecode, PAL
Vertical interval timecode, NTSC
Video program system, PAL
Reserved
1000b
WSS, PAL
1001b
WSS, NTSC
VITC, PAL
1010b
1011b
VITC, NTSC
VPS, PAL 6
Reserved
1100b
1101b
1110b
Reserved
Reserved
1111b
Active Video
Active video/full field
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At power-up the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents
with the lookup table (see Section 3.20.58). This is done through port address C3h. Each read from or
write to this address auto increments an internal counter to the next RAM location. To access the
VDP-CRAM, the line mode registers (D0h to FCh) must be programmed with FFh to avoid a conflict with
the internal microprocessor and the VDP in both writing and reading. Full field mode also must be
disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h to AFh,
both of which are available through the I2C port.
3.9 VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is
output during the horizontal blanking period following the line from which the data was retrieved. Table 3-2
shows the header format and sequence of the ancillary data inserted into the video stream. This format is
also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can
store up to 11 lines of teletext data with the NTSC NABTS standard.
Table 3-2. Ancillary Data Format and Sequence
D7
(MSB)
D0
(LSB)
BYTE NO.
D6
D5
D4
D3
D2
D1
DESCRIPTION
0
1
2
3
4
5
6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ancillary data preamble
1
1
1
1
1
1
1
1
NEP
NEP
NEP
EP
EP
EP
0
1
0
DID2
F2
N2
DID1
F1
N1
DID0
F0
N0
Data ID (DID)
F5
N5
F4
N4
F3
N3
Secondary data ID (SDID)
Number of 32-bit data (NN)
Internal data ID0 (IDID0)
Video line [7:0]
Data
error
1. Data
7
0
0
0
Match 1 Match 2
Video line [9:8]
Internal data ID1 (IDID1)
8
9
Data byte
Data byte
2. Data
3. Data
4. Data
⋮
First word
10
11
⋮
Data byte
Data byte
⋮
m–1. Data
m. Data
Data byte
Data byte
Check sum
Fill byte
Nth word
RSVD
CS[5:0]
4(N+2)–1
1
0
0
0
0
0
0
0
EP:
Even parity for D0–D5
Negated even parity
NEP:
DID:
91h: Sliced data of VBI lines of first field
53h: Sliced data of line 24 to end of first field
55h: Sliced data of VBI lines of second field
97h: Sliced data of line 24 to end of second field
SDID:
NN:
This field holds the data format taken from the line mode register of the corresponding line.
Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords
where each Dword is 4 bytes.
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IDID0:
IDID1:
Transaction video line number [7:0]
Bit 0/1 = Transaction video line number [9:8]
Bit 2 = Match 2 flag
Bit 3 = Match 1 flag
Bit 4 = 1 if an error was detected in the EDC block; 0 if not
Sum of D0–D7 of DID through last data byte.
CS:
Fill byte:
Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the
sync pattern byte. Byte 9 is 1. Data (the first data byte).
3.10 Raw Video Data Output
The TVP5150AM1 decoder can output raw A/D video data at 2x sampling rate for external VBI slicing.
This is transmitted as an ancillary data block during the active horizontal portion of the line and during
vertical blanking.
3.11 Output Formatter
The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface
standard.
Table 3-3. Summary of Line Frequencies, Data Rates, and Pixel Counts
SCLK
FREQUENCY
(MHz)
HORIZONTAL
LINE RATE (kHz)
ACTIVE PIXELS
PER LINE
STANDARDS
PIXELS PER LINE
NTSC (M, 4.43), ITU-R BT.601
PAL (B, D, G, H, I), ITU-R BT.601
PAL (M), ITU-R BT.601
15.73426
15.625
858
864
858
864
864
720
720
720
720
720
27.00
27.00
27.00
27.00
27.00
15.73426
15.625
PAL (N), ITU-R BT.601
SECAM, ITU-R BT.601
15.625
3.12 Synchronization Signals
External (discrete) syncs are provided via the following signals (see Figure 3-2 and Figure 3-3):
•
•
•
•
•
•
VSYNC (vertical sync)
FID/VLK (field indicator or vertical lock indicator)
GPCL/VBLK (general-purpose I/O or vertical blanking indicator)
PALI/HLK (PAL switch indicator or horizontal lock indicator)
HSYNC (horizontal sync)
AVID (active video indicator)
VSYNC, FID, PALI, and VBLK are software set and programmable to the SCLK pixel count. This allows
any possible alignment to the internal pixel count and line count. The default settings for a 525-/625-line
video output are given as an example.
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525 Line
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
262 263 264 265 266 267 268 269 270 271 272 273
282 283 284
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
625 Line
310 311 312 313 314 315 316 317 318 319 320
333 334 335 336
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
622 623 624 625
1
2
3
4
5
6
7
20
21
22
23
Composite
Video
VSYNC
FID
GPCL/VBLK
↔
↔
VBLK Start
VBLK Stop
A. Line numbering conforms to ITU-R BT.470.
Figure 3-2. 8-Bit 4:2:2, Timing With 2× Pixel Clock (SCLK) Reference
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ITU-R BT.656 Timing
…
…
…
NTSC 601 1436 1437 1438 1439 1440 1441
1455 1456
1459 1460
1713 1714 1715
1725 1726 1727
0
0
1
1
2
2
3
3
1583 1584
1587 1588
1711 1712
1723 1724
PAL 601
SECAM
1436 1437 1438 1439 1440 1441
1436 1437 1438 1439 1440 1441
17 17 17 17
24 25 26 27
…
…
…
1479 1480
1607 1608
1719 1720 1721 1722 1723
Y
1
Cb
0
Y
0
Cr
0
ITU 656
Datastream
Cb
359
Y
718
Cr Y
359 719
FF
00
10
80
00
00
XX
10
80
10
FF
HSYNC
AVID
↔
HSYNC Start
↔
↔
AVID Stop
A. AVID rising edge occurs four SCLK cycles early when in the ITU-R BT.656 output mode.
AVID Start
Figure 3-3. Horizontal Synchronization Signals
3.13 Active Video (AVID) Cropping
AVID cropping provides a means to decrease bandwidth of the video output. This is accomplished by
horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The
horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB,
respectively.
Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID
cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and
19h. Figure 3-4 shows an AVID application.
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Active Video Area
AVID Cropped
Area
AVID Start
AVID Stop
HSYNC
Figure 3-4. AVID Application
3.14 Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end
of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V
change on EAV. Table 3-4 gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line
and field counter varies depending on the standard. See ITU-R BT.656 for more information on embedded
syncs.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 3-4. EAV and SAV Sequence
8-BIT DATA
D7 (MSB)
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Preamble
Preamble
Preamble
Status word
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
V
H
P3
P2
P1
P0
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3.15 I2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line
(SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used
for slave address selection. Although the I2C system can be multimastered, the TVP5150AM1 decoder
functions only as a slave device.
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is
free, both lines are high. The slave address select terminal (I2CSEL) enables the use of two
TVP5150AM1 decoders tied to the same I2C bus. At power up, the status of the I2CSEL is polled.
Depending on the write and read addresses to be used for the TVP5150AM1 decoder, I2CSEL can either
be pulled low or high through a resistor. This terminal is multiplexed with YOUT7 and hence must not be
tied directly to ground or IO_DVDD. Table 3-6 summarizes the terminal functions of the I2C-mode host
interface.
Table 3-5. Write-Address
Selection
I2CSEL
WRITE ADDRESS
0
1
B8h
BAh
Table 3-6. I2C Terminal Description
SIGNAL
TYPE
I
DESCRIPTION
I2CSEL (YOUT7)
Slave-address selection
Input/output clock line
Input/output data line
SCL
SDA
I/O (open drain)
I/O (open drain)
Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL except for start and stop conditions. The high or low state of the data line can
change ony with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while
the SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is
high indicates an I2C stop condition.
Every byte placed on the SDA must be eight bits long. The number of bytes that can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
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3.15.1 I2C Write Operation
Data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to the TVP5150AM1 decoder by generating a start condition (S)
followed by the TVP5150AM1 I2C address (see the following illustration), in MSB-first bit order, followed
by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5150AM1 decoder, the
master presents the subaddress of the register, or the first of a block of registers it wants to write, followed
by one or more bytes of data, MSB first. The TVP5150AM1 decoder acknowledges each byte after
completion of each transfer. The I2C master terminates the write operation by generating a stop condition
(P).
Step 1
0
I2C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
0
Step 3
9
I2C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Write register address (master)
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Step 5
9
I2C Acknowledge (slave)
A
Step 6
7
6
5
4
3
2
1
0
I2C Write data (master)
Data
Data
Data
Data
Data
Data
Data
Data
Step 7(1)
9
I2C Acknowledge (slave)
A
Step 8
0
I2C Stop (master)
P
(1) Repeat steps 6 and 7 until all data have been written.
3.15.2 I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C
master initiates a write operation to the TVP5150AM1 decoder by generating a start condition (S) followed
by the TVP5150AM1 I2C address, in MSB-first bit order, followed by a 0 to indicate a write cycle. After
receiving acknowledges from the TVP5150AM1 decoder, the master presents the subaddress of the
register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master
terminates the cycle immediately by generating a stop condition (P).
Table 3-7. Read Address
Selection
I2CSEL
READ-ADDRESS
0
1
B9h
BBh
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The second phase is the data phase. In this phase, an I2C master initiates a read operation to the
TVP5150AM1 decoder by generating a start condition followed by the TVP5150AM1 I2C address (see the
following illustration of a read operation), in MSB-first bit order, followed by a 1 to indicate a read cycle.
After an acknowledge from the TVP5150AM1 decoder, the I2C master receives one or more bytes of data
from the TVP5150AM1 decoder. The I2C master acknowledges the transfer at the end of each byte. After
the last data byte desired has been transferred from the TVP5150AM1 decoder to the master, the master
generates a not acknowledge followed by a stop.
3.15.2.1 Read Phase 1
Step 1
0
I2C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
0
Step 3
9
I2C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Write register address (master)
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Step 5
9
I2C Acknowledge (slave)
A
Step 6
0
I2C Stop (master)
P
3.15.2.2 Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
1
Step 9
9
I2C Acknowledge (slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read data (slave)
Data
Data
Data
Data
Data
Data
Data
Data
Step 11(1)
9
I2C Not Acknowledge (master)
A
Step 12
0
I2C Stop (master)
P
(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
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3.15.2.3 I2C Timing Requirements
The TVP5150AM1 decoder requires delays in the I2C accesses to accommodate its internal processor's
timing. In accordance with I2C specifications, the TVP5150AM1 decoder holds the I2C clock line (SCL) low
to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock
line held-low condition, then the maximum delays always must be inserted where required. These delays
are of variable length; maximum delays are indicated in the following diagram:
Normal register writing addresses 00h to 8Fh (addresses 90h to FFh do not require delays).
Slave
Start
address
(B8h)
Ack
Subaddress
Ack
Data (XXh)
Ack
Wait 64 µs
Stop
The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some
registers.
3.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to
drive the PLL. This may be input to the TVP5150AM1 decoder on terminal 5 (XTAL1), or a crystal of
14.31818-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2).
Figure 3-5 shows the reference clock configurations. For the example crystal circuit shown (a
parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have
the following relationship:
CL1 = CL2 = 2CL – CSTRAY
where CSTRAY is the terminal capacitance with respect to ground. Figure 3-5 shows the reference clock
configurations.
TVP5150AM1
TVP5150AM1
14.31818-MHz
Crystal
C
C
L1
5
6
5
6
14.31818-MHz
TTL Clock
XTAL1
XTAL1
R
L2
XTAL2
XTAL2
A. R depends on crystal specification and may not be required.
Figure 3-5. Reference Clock Configurations
3.17 Genlock Control (GLCO) and RTC
A Genlock control function is provided to support a standard video encoder to synchronize its internal
color oscillator for properly reproduced color with unstable timebase sources such as VCRs.
The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the
subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit
binary number. The frequency of the DTO can be calculated from the following equation:
Fdto = (Fctrl/223) × Fsclk
where Fdto is the frequency of the DTO, Fctrl is the 23-bit DTO frequency control, and Fsclk is the frequency
of the SCLK.
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3.17.1 GLCO Interface
A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO
phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven SCLKs
after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the
phase of the TVP5150AM1 internal subcarrier DCO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to
synchronize its internal color phase DCO to achieve clean line and color lock.
Figure 3-6 shows the timing diagram of the GLCO mode.
SCLK
GLCO
MSB
21
LSB
0
22
>128 SCLK
23 SCLK
7 SCLK
23-Bit Frequency Control
1 SCLK
1 SCLK
DCO Reset Bit
Start Bit
Figure 3-6. GLCO Timing
3.17.2 RTC Mode
Figure 3-7 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower
than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control
bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of
PLL frequency control.
M
S
L
S
B
RTC
B
21
0
128 CLK
16 CLK
2 CLK
44 CLK
1 CLK
22-Bit Fsc Frequency Control
PAL
Switch
2 CLK
Start
Bit
3 CLK
1 CLK
Reset
Bit
Figure 3-7. RTC Timing
26
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3.18 Reset and Power Down
Terminals 8 (RESETB) and 28 (PDN) work together to put the TVP5150AM1 decoder into one of the two
modes. Table 3-8 shows the configuration.
After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB
active low for at least 500 ns. The power supplies must be active and stable for 20 ms before RESETB
becomes inactive.
Table 3-8. Reset and Power-Down Modes
PDN
RESETB
CONFIGURATION
Reserved (unknown state)
Powers down the decoder
Resets the decoder
0
0
1
1
0
1
0
1
Normal operation
3.19 Internal Control Registers
The TVP5150AM1 decoder is initialized and controlled by a set of internal registers that set all device
operating parameters. Communication between the external controller and the TVP5150AM1 decoder is
through I2C. Table 3-9 shows the summary of these registers. The reserved registers must not be written.
Reserved bits in the defined registers must be written with zeros, unless otherwise noted. The detailed
programming information of each register is described in the following sections.
Table 3-9. Register Summary
REGISTER
Video input source selection #1
Analog channel controls
Operation mode controls
Miscellaneous controls
Autoswitch mask
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
DEFAULT
00h
R/W(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15h
00h
01h
DCh
00h
Reserved
Color killer threshold control
Luminance processing control 1
Luminance processing control 2
Brightness control
10h
60h
00h
80h
Color saturation control
Hue control
80h
00h
Contrast control
80h
Outputs and data rates select
Luminance processing control #3
Configuration shared pins
Reserved
47h
00h
08h
Active video cropping start pixel MSB
Active video cropping start pixel LSB
Active video cropping stop pixel MSB
Active video cropping stop pixel LSB
Genlock and RTC
00h
00h
00h
00h
01h
80h
R/W
R/W
R/W
R/W
R/W
R/W
Horizontal sync start
Reserved
(1) R = Read only, W = Write only, R/W = Read and write
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Table 3-9. Register Summary (continued)
REGISTER
Vertical blanking start
ADDRESS
18h
DEFAULT
00h
R/W(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Vertical blanking stop
Chrominance control #1
Chrominance control #2
Interrupt reset register B
Interrupt enable register B
Interrupt configuration register B
Reserved
19h
00h
1Ah
0Ch
1Bh
14h
1Ch
00h
1Dh
00h
1Eh
00h
1Fh–27h
28h
Video standard
00h
R/W
Reserved
29h–2Bh
2Ch
Cb gain factor
R
Cr gain factor
2Dh
R
Macrovision on counter
Macrovision off counter
656 revision select
Reserved
2Eh
0Fh
01h
00h
R/W
R/W
R/W
2Fh
30h
31h–7Fh
80h
MSB of device ID
51h
50h
04h
00h
R
R
R
R
R
R
R
R
R
R
R
R
R
LSB of device ID
81h
ROM major version
ROM minor version
Vertical line count MSB
Vertical line count LSB
Interrupt status register B
Interrupt active register B
Status register 1
82h
83h
84h
85h
86h
87h
88h
Status register 2
89h
Status register 3
8Ah
Status register 4
8Bh
Status register 5
8Ch
Reserved
8Dh–8Fh
90h–93h
94h–99h
9Ah–A6h
A7h–AFh
B0h
Closed caption data
WSS data
R
R
VPS data
R
VITC data
R
VBI FIFO read data
Teletext filter and mask 1
Teletext filter and mask 2
Teletext filter control
Reserved
R
B1h–B5h
B6h–BAh
BBh
00h
00h
00h
R/W
R/W
R/W
BCh–BFh
C0h
Interrupt status register A
Interrupt enable register A
Interrupt configuration register A
VDP configuration RAM data
VDP configuration RAM address low byte
VDP configuration RAM address high byte
VDP status
00h
00h
04h
DCh
0Fh
00h
R/W
R/W
R/W
R/W
R/W
R/W
R
C1h
C2h
C3h
C4h
C5h
C6h
FIFO word count
C7h
R
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Table 3-9. Register Summary (continued)
REGISTER
FIFO interrupt threshold
ADDRESS
C8h
DEFAULT
80h
R/W(1)
R/W
W
FIFO reset
C9h
CAh
CBh
CCh
CDh
CEh
CFh
00h
00h
4Eh
00h
01h
Line number interrupt
Pixel alignment low byte
Pixel alignment high byte
FIFO output control
Reserved
R/W
R/W
R/W
R/W
Full field enable
00h
R/W
R/W
R/W
D0h
D1h–FBh
00h
FFh
Line mode
Full field mode
Reserved
FCh
7Fh
FDh–FFh
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3.20 Register Definitions
3.20.1 Video Input Source Selection 1 Register
Address
Default
00h
00h
7
6
5
4
3
2
1
0
Reserved
Black output
Reserved
Channel 1
source
S-video
selection
selection
Channel 1 source selection
0 = AIP1A selected (default)
1 = AIP1B selected
Table 3-10. Analog Channel and Video Mode Selection
ADDRESS 00
INPUT(S) SELECTED
BIT 1
BIT 0
AIP1A (default)
AIP1B
0
1
0
0
Composite
S-Video
AIP1A (luma), AIP1B
(chroma)
x
1
Black output
0 = Normal operation (default)
1 = Force black screen output (outputs synchronized)
a. Forced to 10h in normal mode
b. Forced to 01h in extended mode
3.20.2 Analog Channel Controls Register
Address
Default
01h
15h
7
6
5
4
3
2
1
0
Reserved
1
Automatic offset control
Automatic gain control
Automatic offset control
00 = Disabled
01 = Automatic offset enabled (default)
10 = Reserved
11 = Offset level frozen to the previously set value
Automatic gain control (AGC)
00 = Disabled (fixed gain value)
01 = AGC enabled (default)
10 = Reserved
11 = AGC frozen to the previously set value
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3.20.3 Operation Mode Controls Register
Address
Default
02h
00h
7
6
5
4
3
2
1
0
Reserved
Color burst
reference
enable
TV/VCR mode
White peak
disable
Color
subcarrier PLL
frozen
Luma peak
disable
Power-down
mode
Color burst reference enable
0 = Color burst reference for AGC disabled (default)
1 = Color burst reference for AGC enabled
TV/VCR mode
00 = Automatic mode determined by the internal detection circuit (default)
01 = Reserved
10 = VCR (nonstandard video) mode
11 = TV (standard video) mode
With automatic detection enabled, unstable or nonstandard syncs on the input video forces the detector
into the VCR mode. This turns off the comb filters and turns on the chroma trap filter.
White peak disable
0 = White peak protection enabled (default)
1 = White peak protection disabled
Color subcarrier PLL frozen
0 = Color subcarrier PLL increments by the internally generated phase increment (default). GLCO pin
outputs the frequency increment.
1 = Color subcarrier PLL stops operating. GLCO pin outputs the frozen frequency increment.
Luma peak disable
0 = Luma peak processing enabled (default)
1 = Luma peak processing disabled
Power-down mode
0 = Normal operation (default)
1 = Power-down mode. A/Ds are turned off and internal clocks are reduced to minimum.
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3.20.4 Miscellaneous Controls Register
Address
Default
03h
01h
7
6
5
4
3
2
1
0
VBKO
GPCL pin
GPCL output
enable
Lock status
(HVLK)
YCbCr output
enable
(TVPOE)
HSYNC,
VSYNC/PALI,
AVID,
Vertical
blanking on/off
Clock output
enable
FID/GLCO
output enable
VBKO (pin 27) function select
0 = GPCL (default)
1 = VBLK
NOTE
If this pin is not configured as an output, it must not be left floating. A 10-kΩ pulldown
resistor is recommended, if not driven externally.
GPCL (data is output based on state of bit 5)
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL output enable
0 = GPCL is inactive (default)
1 = GPCL is output
NOTE
GPCL must not be programmed to be 0 when register 0Fh bit 1 is 1 (GPCL/VBLK). If this
pin is not configured as an output, it must not be left floating. A 10-kΩ pulldown resistor is
recommended, if not driven externally.
Lock status (HVLK) (configured along with register 0Fh, see Figure 3-8 for the relationship between the
configuration shared pins)
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the
field ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh).
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the
vertical lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh).
These are additional functions that are provided for ease of use.
YCbCr output enable
0 = YOUT[7:0] high impedance (default)
1 = YOUT[7:0] active
NOTE
The YOUT[6:0] pins must be driven externally or pulled down with a 10-kΩ resistor.
YOUT7 must be already pulled high or low for the I2C address select.
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HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
NOTE
If these pins are not configured as outputs, then they must not be left floating. 10-kΩ
pulldown resistors are recommended, if not driven externally. If the FID/GLCO pin is
configured as a GLCO output (default), it is always an output, regardless of the status of
this register, and it must not be pulled down or driven externally.
Vertical blanking on/off
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
Clock output enable
0 = SCLK output is high impedance.
1 = SCLK output is enabled (default).
NOTE
When enabling the outputs, ensure the clock output is not accidently disabled.
Table 3-11. Digital Output Control(1)
REGISTER 03h, BIT 3
REGISTER C2h, BIT 2
(VDPOE)
YCbCr OUTPUT
NOTES
(TVPOE)
0
X
1
X
0
1
High impedance
High impedance
Active
After both YCbCr output enable bits are programmed
After both YCbCr output enable bits are programmed
After both YCbCr output enable bits are programmed
(1) VDPOE default is 1, and TVPOE default is 0.
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0F(Bit 2)
VSYNC/PALI
0F(Bit 4)
LOCK24B
VSYNC
0
M
U
X
PALI
0
1
VSYNC/PALI/HLK/HVLK
M
U
X
Pin 24
HLK
0
1
PALI/HLK/HVLK
1
M
U
X
HLK/HVLK
HVLK
HVLK
VLK
1
0
M
U
X
VLK/HVLK
FID
1
0
M
U
X
FID/VLK/HVLK
GLCO
0
1
M
U
X
FID/GLCO/VLK/HVLK
Pin 23
0F(Bit 6)
LOCK23
0F(Bit 3)
03(Bit 4)
HVLK
FID/GLCO
VBLK
GPCL
1
0
M
U
X
VBLK/GPCL
INTREQ
1
0
M
U
X
INTREQ/GPCL//VBLK
Pin 27
SCLK
PCLK
0
M
U
X
PCLK/SCLK
Pin 9
1
03(Bit 7)
VBKO
0F(Bit 1)
INTREQ/GPCL/VBLK
0F(Bit 0)
SCLK/PCLK
Figure 3-8. Configuration Shared Pins
NOTE
Also see the configuration shared pins register at subaddress 0Fh.
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3.20.5 Autoswitch Mask Register
Address
Default
04h
DCh
7
6
5
4
3
2
1
0
Reserved
SEC_OFF
N443_OFF
PALN_OFF
PALM_OFF
Reserved
N443_OFF
0 = NTSC443 is unmasked from the autoswitch process. Autoswitch does switch to NTSC443.
1 = NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443
(default).
PALN_OFF
0 = PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N.
1 = PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N (default).
PALM_OFF
0 = PAL-M is unmasked from the autoswitch process. Autoswitch does switch to PAL-M.
1 = PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M (default).
SEC_OFF
0 = SECAM is unmasked from the autoswitch process. Autoswitch does switch to SECAM (default).
1 = SECAM is masked from the autoswitch process. Autoswitch does not switch to SECAM.
3.20.6 Color Killer Threshold Control Register
Address
Default
06h
10h
7
6
5
4
3
2
1
0
Reserved
Automatic color killer
Color killer threshold
Automatic color killer
00 = Automatic mode (default)
01 = Reserved
10 = Color killer enabled, CbCr terminals forced to a zero color state
11 = Color killer disabled
Color killer threshold
11111 = –30 dB (minimum)
10000 = –24 dB (default)
00000 = –18 dB (maximum)
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3.20.7 Luminance Processing Control 1 Register
Address
Default
07h
60h
7
6
5
4
3
2
1
0
2× luma output
Pedestal not
present
Disable raw
header
Luma bypass
enabled during
vertical
Luminance signal delay with respect to chrominance signal
enable
blanking
2× luma output enable
0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default).
1 = Outputs 2x luma samples during the entire frame. This bit takes precedence over bit 4.
Pedestal not present
0 = 7.5 IRE pedestal is present on the analog video input signal.
1 = Pedestal is not present on the analog video input signal (default).
Disable raw header
0 = Insert 656 ancillary headers for raw data
1 = Disable 656 ancillary headers and instead force dummy ones (0x40) (default)
Luminance bypass enabled during vertical blanking
0 = Disabled. If bit 7, 2× luma output enable, is 0, normal luminance processing occurs and YCbCr
samples are output during the entire frame (default).
1 = Enabled. If bit 7, 2× luma output enable, is 0, normal luminance processing occurs and YCbCr
samples are output during VACTIVE and 2× luma samples are output during VBLK. Luminance bypass
occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
Luma signal delay with respect to chroma signal in pixel clock increments (range –8 to +7 pixel clocks)
1111 = –8 pixel clocks delay
1011 = –4 pixel clocks delay
1000 = –1 pixel clocks delay
0000 = 0 pixel clocks delay (default)
0011 = +3 pixel clocks delay
0111 = +7 pixel clocks delay
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3.20.8 Luminance Processing Control 2 Register
Address
Default
08h
00h
7
6
5
4
3
2
1
0
Reserved
Luminance filter
select
Reserved
Peaking gain
Mac AGC control
Luminance filter select
0 = Luminance comb filter enabled (default)
1 = Luminance chroma trap filter enabled
Peaking gain (sharpness)
00 = 0 (default)
01 = 0.5
10 = 1
11 = 2
Information on peaking frequency:
ITU-R BT.601 sampling rate: all standards
Peaking center frequency is 2.6 MHz.
Mac AGC control
00 = Auto mode
01 = Auto mode
10 = Force Macrovision AGC pulse detection off
11 = Force Macrovision AGC pulse detection on
3.20.9 Brightness Control Register
Address
Default
09h
80h
7
6
5
4
3
2
1
0
Brightness control
Brightness control
1111 1111 = 255 (bright)
1000 0000 = 128 (default)
0000 0000 = 0 (dark)
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3.20.10 Color Saturation Control Register
Address
Default
0Ah
80h
7
6
5
4
3
3
3
2
2
2
1
1
1
0
Saturation control
Saturation control
1111 1111 = 255 (maximum)
1000 0000 = 128 (default)
0000 0000 = 0 (no color)
3.20.11 Hue Control Register
Address
Default
0Bh
00h
7
6
5
4
0
Hue control
Hue control (does not apply to SECAM)
0111 1111 = +180 degrees
0000 0000 = 0 degrees (default)
1000 0000 = –180 degrees
3.20.12 Contrast Control Register
Address
Default
0Ch
80h
7
6
5
4
Contrast control
0
Contrast control
1111 1111 = 255 (maximum contrast)
1000 0000 = 128 (default)
0000 0000 = 0 (minimum contrast)
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3.20.13 Outputs and Data Rates Select Register
Address
Default
0Dh
47h
7
6
5
4
3
2
1
0
Reserved
YCbCr output
code range
CbCr code
format
YCbCr data path bypass
YCbCr output format
YCbCr output code range
0 = ITU-R BT.601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240)
1 = Extended coding range (Y, U, and V range from 1 to 254) (default)
CbCr code format
0 = Offset binary code (2s complement + 128) (default)
1 = Straight binary code (2s complement)
YCbCr data path bypass
00 = Normal operation (default)
01 = Decimation filter output connects directly to the YCbCr output pins. This data is similar to the
digitized composite data, but the HBLANK area is replaced with ITU-R BT.656 digital blanking.
10 = Digitized composite (or digitized S-video luma). A/D output connects directly to YCbCr output
pins.
11 = Reserved
YCbCr output format
000 = 8-bit 4:2:2 YCbCr with discrete sync output
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
111 = 8-bit ITU-R BT.656 interface with embedded sync output (default)
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3.20.14 Luminance Processing Control 3 Register
Address
Default
0Eh
00h
7
6
5
4
3
2
1
0
Reserved
Luminance trap filter select
Luminance filter stop band bandwidth (MHz)
00 = No notch (default)
01 = Notch 1
10 = Notch 2
11 = Notch 3
Luminance filter select [1:0] selects one of the four chroma trap (notch) filters to produce luminance signal
by removing the chrominance signal from the composite video signal. The stopband of the chroma trap
filter is centered at the chroma subcarrier frequency with stopband bandwidth controlled by the two control
bits. See the following table for the stopband bandwidths. The WCF bit is controlled in the chrominance
control 2 register, see Section 3.20.25.
NTSC/PAL/SECAM
WCF
FILTER SELECT
ITU-R BT.601
00
01
10
11
00
01
10
11
1.2244
0.8782
0
0.7297
0.4986
1.4170
1.0303
1
0.8438
0.5537
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3.20.15 Configuration Shared Pins Register
Address
Default
0Fh
08h
7
6
5
4
3
2
1
0
Reserved
LOCK23
Reserved
LOCK24B
FID/GLCO
VSYNC/PALI INTREQ/GPCL/
VBLK
SCLK/PCLK
LOCK23 (pin 23) function select
0 = FID (default, if bit 3 is selected to output FID)
1 = Lock indicator (indicates whether the device is locked vertically)
LOCK24B (pin 24) function select
0 = PALI (default, if bit 2 is selected to output PALI)
1 = Lock indicator (indicates whether the device is locked horizontally)
FID/GLCO (pin 23) function select (also see register 03h for enhanced functionality)
0 = FID
1 = GLCO (default)
VSYNC/PALI (pin 24) function select (also see register 03h for enhanced functionality)
0 = VSYNC (default)
1 = PALI
INTREQ/GPCL/VBLK (pin 27) function select
0 = INTREQ (default)
1 = GPCL or VBLK depending on bit 7 of register 03h
SCLK/PCLK (pin 9) function select
0 = SCLK (default)
1 = PCLK (1x pixel clock frequency)
See Figure 3-8 for the relationship between the configuration shared pins.
3.20.16 Active Video Cropping Start Pixel MSB Register
Address
Default
11h
00h
7
6
5
4
3
2
1
0
AVID start pixel MSB [9:2]
Active video cropping start pixel MSB [9:2]: Set this register first before setting register 12h. The
TVP5150AM1 decoder updates the AVID start values only when register 12h is written to. This start pixel
value is relative to the default values of the AVID start pixel.
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3.20.17 Active Video Cropping Start Pixel LSB Register
Address
Default
12h
00h
7
6
5
4
3
2
1
0
Reserved
AVID active
AVID start pixel LSB [1:0]
AVID active
0 = AVID out active in VBLK (default)
1 = AVID out inactive in VBLK
Active video cropping start pixel LSB [1:0]: The TVP5150AM1 decoder updates the AVID start values
only when this register is written to.
AVID start [9:0] (combined registers 11h and 12h)
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default)
11 1111 1111 = –1
10 0000 0000 = –512
3.20.18 Active Video Cropping Stop Pixel MSB Register
Address
Default
13h
00h
7
6
5
4
3
2
1
0
AVID stop pixel MSB
Active video cropping stop pixel MSB [9:2]: Set this register first before setting the register 14h. The
TVP5150AM1 decoder updates the AVID stop values only when register 14h is written to. This stop pixel
value is relative to the default values of the AVID stop pixel.
3.20.19 Active Video Cropping Stop Pixel LSB Register
Address
Default
14h
00h
7
6
5
4
3
2
1
0
Reserved
AVID stop pixel LSB
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number.
The TVP5150AM1 decoder updates the AVID stop values only when this register is written to.
AVID stop [9:0] (combined registers 13h and 14h)
01 1111 1111 = 511
00 0000 0001 = 13
00 0000 0000 = 0 (default) (see Figure 3-3 and Figure 3-4)
11 1111 1111 = –1
10 0000 0000 = –512
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3.20.20 Genlock and RTC Register
Address
Default
15h
01h
7
6
5
4
3
2
1
0
Reserved
F/V bit control
Reserved
GLCO/RTC
F/V bit control
BIT 5
BIT 4
NUMBER OF LINES
Standard
F BIT
V BIT
ITU-R BT.656
Force to 1
ITU-R BT.656
0
0
Nonstandard even
Nonstandard odd
Standard
Switch at field boundary
Switch at field boundary
ITU-R BT.656
Toggles
ITU-R BT.656
Toggles
0
1
Nonstandard
Standard
Switch at field boundary
ITU-R BT.656
ITU-R BT.656
Pulse mode
1
1
0
1
Nonstandard
Illegal
Switch at field boundary
GLCO/RTC. The following table shows the different modes.
BIT 2
BIT 1
BIT 0
GENLOCK/RTC MODE
GLCO
0
X
0
RTC output mode 0
(default)
0
X
1
1
1
X
X
0
1
GLCO
RTC output mode 1
All other values are reserved.
Figure 3-6 shows the timing of GLCO, and Figure 3-7 shows the timing of RTC.
3.20.21 Horizontal Sync Start Register
Address
Default
16h
80h
7
6
5
4
3
2
1
0
HSYNC start
Horizontal sync (HSYNC) start
1111 1111 = –127 × 4 pixel clocks
1111 1110 = –126 × 4 pixel clocks
1000 0001 = –1 × 4 pixel clocks
1000 0000 = 0 pixel clocks (default)
0111 1111 = 1 × 4 pixel clocks
0111 1110 = 2 × 4 pixel clocks
0000 0000 = 128 × 4 pixel clocks
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BT.656 SAV Code
BT.656 EAV Code
U
Y
V
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
U
Y
YOUT[7:0]
HSYNC
AVID
128 SCLK
Start of
Digital Line
Start of Digital
Active Line
N
hbhs
N
hb
Figure 3-9. Horizontal Sync
Table 3-12. Clock Delays
(SCLKs)
STANDARD
NTSC
Nhbhs
16
Nhb
272
284
280
PAL
20
SECAM
40
Detailed timing information is also available in Section 3.12.
3.20.22 Vertical Blanking Start Register
Address
Default
18h
00h
7
6
5
4
3
2
1
0
Vertical blanking start
Vertical blanking (VBLK) start
0111 1111 = 127 lines after start of vertical blanking interval
0000 0001 = 1 line after start of vertical blanking interval
0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 3-2)
1111 1111 = 1 line before start of vertical blanking interval
1000 0000 = 128 lines before start of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
register determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
register 03h). The setting in this register also determines the duration of the luma bypass function (see
register 07h).
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3.20.23 Vertical Blanking Stop Register
Address
Default
19h
00h
7
6
5
4
3
2
1
0
Vertical blanking stop
Vertical blanking (VBLK) stop
0111 1111 = 127 lines after stop of vertical blanking interval
0000 0001 = 1 line after stop of vertical blanking interval
0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 3-2)
1111 1111 = 1 line before stop of vertical blanking interval
1000 0000 = 128 lines before stop of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
register determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
register 03h). The setting in this register also determines the duration of the luma bypass function (see
register 07h).
3.20.24 Chrominance Control 1 Register
Address
Default
1Ah
0Ch
7
6
5
4
3
2
1
0
Reserved
Color PLL reset Chrominance
adaptive comb
Chrominance
comb filter
Automatic color gain control
filter enable
enable (CE)
(ACE)
Color PLL reset
0 = Color PLL not reset (default)
1 = Color PLL reset
When a 1 is written to this bit, the color PLL phase is reset to zero, and the subcarrier PLL phase reset
bit is transmitted on terminal 23 (GLCO) on the next line (NTSC or PAL).
Chrominance adaptive comb filter enable (ACE)
0 = Disable
1 = Enable (default)
Chrominance comb filter enable (CE)
0 = Disable
1 = Enable (default)
Automatic color gain control (ACGC)
00 = ACGC enabled (default)
01 = Reserved
10 = ACGC disabled
11 = ACGC frozen to the previously set value
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3.20.25 Chrominance Control 2 Register
Address
Default
1Bh
14h
7
6
5
4
3
2
1
0
Reserved
Reserved
WCF
Chrominance filter select
Wideband chroma filter (WCF)
0 = Disable
1 = Enable (default)
Chrominance low pass filter select
00 = No notch (default)
01 = Notch 1
10 = Notch 2
11 = Notch 3
Chrominance output bandwidth (MHz)
NTSC/PAL/SECAM
ITU-R BT.601
WCF
FILTER SELECT
00
01
10
11
00
01
10
11
1.2214
0.8782
0.7297
0.4986
1.4170
1.0303
0.8438
0.5537
0
1
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3.20.26 Interrupt Reset Register B
Address
Default
1Ch
00h
7
6
5
4
3
2
1
0
Software
initialization
reset
Macrovision
detect changed
reset
Reserved
Field rate
changed reset
Line alternation
changed reset
Color lock
changed reset
H/V lock
changed reset
TV/VCR
changed reset
Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt
status register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded
with a 0 have no effect on the interrupt status bits.
Software initialization reset
0 = No effect (default)
1 = Reset software initialization bit
Macrovision detect changed reset
0 = No effect (default)
1 = Reset Macrovision detect changed bit
Field rate changed reset
0 = No effect (default)
1 = Reset field rate changed bit
Line alternation changed reset
0 = No effect (default)
1 = Reset line alternation changed bit
Color lock changed reset
0 = No effect (default)
1 = Reset color lock changed bit
H/V lock changed reset
0 = No effect (default)
1 = Reset H/V lock changed bit
TV/VCR changed reset [TV/VCR mode is determined by counting the total number of lines/frame. The
mode switches to VCR for nonstandard number of lines]
0 = No effect (default)
1 = Reset TV/VCR changed bit
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3.20.27 Interrupt Enable Register B
Address
Default
1Dh
00h
7
6
5
4
3
2
1
0
Software
initialization
occurred
enable
Macrovision
detect changed
Reserved
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for
interrupt B. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the
external pin. Conversely, bits loaded with zeros mask the corresponding interrupt condition from
generating an interrupt on the external pin. This register affects only the external pin, it does not affect the
bits in the interrupt status register. A given condition can set the appropriate bit in the status register and
not cause an interrupt on the external pin. To determine if this device is driving the interrupt pin, either
AND interrupt status register B with interrupt enable register B, or check the state of interrupt B in the
interrupt B active register.
Software initialization occurred enable
0 = Disabled (default)
1 = Enabled
Macrovision detect changed
0 = Disabled (default)
1 = Enabled
Field rate changed
0 = Disabled (default)
1 = Enabled
Line alternation changed
0 = Disabled (default)
1 = Enabled
Color lock changed
0 = Disabled (default)
1 = Enabled
H/V lock changed
0 = Disabled (default)
1 = Enabled
TV/VCR changed
0 = Disabled (default)
1 = Enabled
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3.20.28 Interrupt Configuration Register B
Address
Default
1Eh
00h
7
6
5
4
3
2
1
0
Reserved
Interrupt
polarity B
Interrupt polarity B
0 = Interrupt B is active low (default).
1 = Interrupt B is active high.
Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the Interrupt Configuration
Register A at address C2h.
Interrupt Configuration Register B is used to configure the polarity of interrupt B on the external interrupt
pin. When the interrupt B is configured for active low, the pin is driven low when active and high
impedance when inactive (open-drain). Conversely, when the interrupt B is configured for active high, it is
driven high for active and driven low for inactive.
3.20.29 Video Standard Register
Address
Default
28h
00h
7
6
5
4
3
2
1
0
Reserved
Video standard
Video standard
0000 = Autoswitch mode (default)
0001 = Reserved
0010 = (M) NTSC ITU-R BT.601
0011 = Reserved
0100 = (B, G, H, I, N) PAL ITU-R BT.601
0101 = Reserved
0110 = (M) PAL ITU-R BT.601
0111 = Reserved
1000 = (Combination-N) PAL ITU-R BT.601
1001 = Reserved
1010 = NTSC 4.43 ITU-R BT.601
1011 = Reserved
1100 = SECAM ITU-R BT.601
With the autoswitch code running, the application can force the device to operate in a particular video
standard mode and sample rate by writing the appropriate value into this register.
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3.20.30 Cb Gain Factor Register
Address
2Ch
7
6
5
4
3
2
1
0
Cb gain factor
This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream.
3.20.31 Cr Gain Factor Register
Address
2Dh
7
6
5
4
3
2
1
0
Cr gain factor
This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream.
3.20.32 Macrovision On Counter Register
Address
Default
2Eh
0Fh
7
6
5
4
3
2
1
0
Macrovision off counter
This register allows the user to determine how many consecutive frames in which the Macrovision AGC
pulses are not detected before the decoder decides that the Macrovision AGC pulses are not present.
3.20.33 Macrovision Off Counter Register
Address
Default
2Fh
01h
7
6
5
4
3
2
1
0
Macrovision off counter
This register allows the user to determine how many consecutive frames in which the Macrovision AGC
pulses are not detected before the decoder decides that the Macrovision AGC pulses are not present.
3.20.34 656 Revision Select Register
Address
Default
30h
00h
7
6
5
4
3
2
1
0
Reserved
656 revision
select
656 revision select
0 = Adheres to ITU-R BT.656.4 timing (default)
1 = Adheres to ITU-R BT.656.3 timing
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3.20.35 MSB of Device ID Register
Address
Default
80h
51h
7
6
5
4
3
2
2
2
1
1
1
0
0
0
MSB of device ID
This register identifies the MSB of the device ID. Value = 0x51.
3.20.36 LSB of Device ID Register
Address
Default
81h
50h
7
6
5
4
3
LSB of device ID
This register identifies the LSB of the device ID. Value = 0x50.
3.20.37 ROM Major Version Register
Address
Default
82h
04h
7
6
5
4
3
ROM major version
This register can contain a number from 0x01 to 0xFF.
3.20.38 ROM Minor Version Register
Address
Default
83h
00h
7
6
5
4
3
2
1
0
ROM minor version
This register can contain a number from 0x01 to 0xFF.
3.20.39 Vertical Line Count MSB Register
Address
84h
7
6
5
4
3
2
1
0
Reserved
Vertical line count MSB
Vertical line count bits [9:8]
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3.20.40 Vertical Line Count LSB Register
Address
85h
7
6
5
4
3
2
1
0
Vertical line count LSB
Vertical line count bits [7:0]
Registers 84h and 85h can be read and combined to extract the detected number of lines per frame. This
can be used with nonstandard video signals such as a VCR in fast-forward or rewind modes to
synchronize the downstream video circuitry.
3.20.41 Interrupt Status Register B
Address
86h
7
6
5
4
3
2
1
0
Software
initialization
Macrovision
detect changed
Reserved
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
Software initialization
0 = Software initialization is not ready (default).
1 = Software initialization is ready.
Macrovision detect changed
0 = Macrovision detect status has not changed (default).
1 = Macrovision detect status has changed.
Field rate changed
0 = Field rate has not changed (default).
1 = Field rate has changed.
Line alternation changed
0 = Line alteration has not changed (default).
1 = Line alternation has changed.
Color lock changed
0 = Color lock status has not changed (default).
1 = Color lock status has changed.
H/V lock changed
0 = H/V lock status has not changed (default).
1 = H/V lock status has changed.
TV/VCR changed
0 = TV/VCR status has not changed (default).
1 = TV/VCR status has changed.
Interrupt status register B is polled by the external processor to determine the interrupt source for B
interrupt. After an interrupt condition is set, it can be reset by writing to the interrupt reset register B at
subaddress 1Ch with a 1 in the appropriate bit.
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3.20.42 Interrupt Active Register B
Address
87h
7
6
5
4
3
2
1
0
Reserved
Interrupt B
Interrupt B
0 = Interrupt B is not active on the external terminal (default).
1 = Interrupt B is active on the external terminal.
The interrupt active register B is polled by the external processor to determine if interrupt B is active.
3.20.43 Status Register #1
Address
88h
7
6
5
4
3
2
1
0
Peak white
detect status
Line-alternating
status
Field rate
status
Lost lock detect
Color
subcarrier lock
status
Vertical sync
lock status
Horizontal sync TV/VCR status
lock status
Peak white detect status
0 = Peak white is not detected.
1 = Peak white is detected.
Line-alternating status
0 = Nonline alternating
1 = Line alternating
Field rate status
0 = 60 Hz
1 = 50 Hz
Lost lock detect
0 = No lost lock since status register 1 was last read.
1 = Lost lock since status register 1 was last read.
Color subcarrier lock status
0 = Color subcarrier is not locked.
1 = Color subcarrier is locked.
Vertical sync lock status
0 = Vertical sync is not locked.
1 = Vertical sync is locked.
Horizontal sync lock status
0 = Horizontal sync is not locked.
1 = Horizontal sync is locked.
TV/VCR status. TV mode is determined by detecting standard line-to-line variations and specific chroma
SCH phases based on the standard input video format. VCR mode is determined by detecting variations
in the chroma SCH phases compared to the chroma SCH phases of the standard input video format.
0 = TV
1 = VCR
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3.20.44 Status Register 2
Address
89h
7
6
5
4
3
2
1
0
Reserved
Weak signal
detection
PAL switch
polarity
Field sequence AGC and offset
status frozen status
Macrovision detection
Weak signal detection
0 = No weak signal
1 = Weak signal mode
PAL switch polarity of first line of odd field
0 = PAL switch is 0.
1 = PAL switch is 1.
Field sequence status
0 = Even field
1 = Odd field
AGC and offset frozen status
0 = AGC and offset are not frozen.
1 = AGC and offset are frozen.
Macrovision detection
000 = No copy protection
001 = AGC process present (Macrovision Type 1 present)
010 = Colorstripe process Type 2 present
011 = AGC process and colorstripe process Type 2 present
100 = Reserved
101 = Reserved
110 = Colorstripe process Type 3 present
111 = AGC process and color stripe process Type 3 present
3.20.45 Status Register 3
Address
8Ah
7
6
5
4
3
2
1
0
Front-end AGC gain value (analog and digital)(1)
(1) Represents 8 bits (MSB) of a 10-bit value
This register provides the front-end AGC gain value of both analog and digital gains.
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3.20.46 Status Register 4
Address
8Bh
7
6
5
4
3
2
1
0
Subcarrier to horizontal (SCH) phase
SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step
size 360°/256)
0000 0000 = 0.00°
0000 0001 = 1.41°
0000 0010 = 2.81°
1111 1110 = 357.2°
1111 1111 = 358.6°
3.20.47 Status Register 5
Address
8Ch
7
6
5
4
3
2
1
0
Autoswitch
mode
Reserved
Video standard
Sampling rate
This register contains information about the detected video standard and the sampling rate at which the
device is currently operating. When autoswitch code is running, this register must be tested to determine
which video standard has been detected.
Autoswitch mode
0 = Stand-alone (forced video standard) mode
1 = Autoswitch mode
Video standard
VIDEO STANDARD [3:1]
SR
VIDEO STANDARD
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
(M) NTSC ITU-R BT.601
Reserved
(B, G, H, I, N) PAL ITU-R BT.601
Reserved
(M) PAL ITU-R BT.601
Reserved
PAL-N ITU-R BT.601
Reserved
NTSC 4.43 ITU-R BT.601
Reserved
SECAM ITU-R BT.601
Sampling rate (SR)
0 = Reserved
1 = ITU-R BT.601
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3.20.48 Closed Caption Data Registers
Address
90h–93h
Address
7
6
5
4
3
2
1
0
90h
91h
92h
93h
Closed caption field 1 byte 1
Closed caption field 1 byte 2
Closed caption field 2 byte 1
Closed caption field 2 byte 2
These registers contain the closed caption data arranged in bytes per field.
3.20.49 WSS Data Registers
Address
94h–99h
NTSC
Address
94h
7
6
5
4
3
2
1
0
BYTE
b5
b4
b3
b2
b1
b0
WSS field 1 byte 1
WSS field 1 byte 2
WSS field 1 byte 3
WSS field 2 byte 1
WSS field 2 byte 2
WSS field 2 byte 3
95h
b13
b12
b11
b19
b5
b10
b18
b4
b9
b8
b7
b6
96h
b17
b3
b16
b2
b15
b1
b14
b0
97h
98h
b13
b12
b11
b19
b10
b18
b9
b8
b7
b6
99h
b17
b16
b15
b14
These registers contain the wide screen signaling (WSS) data for NTSC.
For NTSC, the bits are:
Bits 0–1 represent word 0, aspect ratio.
Bits 2–5 represent word 1, header code for word 2.
Bits 6–13 represent word 2, copy control.
Bits 14–19 represent word 3, CRC.
PAL/SECAM
Address
94h
7
6
5
4
3
2
1
0
BYTE
b7
b6
b5
b4
b3
b2
b1
b9
b0
b8
WSS field 1 byte 1
WSS field 1 byte 2
95h
b13
b12
b11
b10
96h
Reserved
97h
b7
b6
b5
b4
b3
b2
b1
b9
b0
b8
WSS field 2 byte 1
WSS field 2 byte 2
98h
b13
b12
b11
b10
99h
Reserved
For PAL/SECAM, the bits are:
Bits 0–3 represent group 1, aspect ratio.
Bits 4–7 represent group 2, enhanced services.
Bits 8–10 represent group 3, subtitles.
Bits 11–13 represent group 4, others.
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3.20.50 VPS Data Registers
Address
9Ah–A6h
Address
7
6
5
4
3
2
1
0
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
VPS byte 1
VPS byte 2
VPS byte 3
VPS byte 4
VPS byte 5
VPS byte 6
VPS byte 7
VPS byte 8
VPS byte 9
VPS byte 10
VPS byte 11
VPS byte 12
VPS byte 13
These registers contain the entire VPS data line except the clock run-in code or the start code.
3.20.51 VITC Data Registers
Address
A7h–AFh
Address
7
6
5
4
3
2
1
0
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
VITC byte 1, frame byte 1
VITC byte 2, frame byte 2
VITC byte 3, seconds byte 1
VITC byte 4, seconds byte 2
VITC byte 5, minutes byte 1
VITC byte 6, minutes byte 2
VITC byte 7, hour byte 1
VITC byte 8, hour byte 2
VITC byte 9, CRC
These registers contain the VITC data.
3.20.52 VBI FIFO Read Data Register
Address
B0h
7
6
5
4
3
2
1
0
FIFO read data
This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data
come directly from the FIFO, while all other forms of VBI data can be programmed to come from the
registers or from the FIFO. Current status of the FIFO can be found at address C6h and the number of
bytes in the FIFO is located at address C7h. If the host port is to be used to read data from the FIFO, then
the output formatter must be disabled at address CDh bit 0. The format used for the VBI FIFO is shown in
Section 3.9.
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3.20.53 Teletext Filter and Mask Registers
Address
Default
B1h–BAh
00h
Address
7
6
5
4
3
2
1
0
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
Filter 1 mask 1
Filter 1 pattern 1
Filter 1 pattern 2
Filter 1 pattern 3
Filter 1 pattern 4
Filter 1 pattern 5
Filter 2 pattern 1
Filter 2 pattern 2
Filter 2 pattern 3
Filter 2 pattern 4
Filter 2 pattern 5
Filter 1 mask 2
Filter 1 mask 3
Filter 1 mask 4
Filter 1 mask 5
Filter 2 mask 1
Filter 2 mask 2
Filter 2 mask 3
Filter 2 mask 4
Filter 2 mask 5
For an NABTS system, the packet prefix consists of five bytes. Each byte contains four data bits (D[3:0])
interlaced with four Hamming protection bits (H[3:0]):
7
6
5
4
3
2
1
0
D[3]
H[3]
D[2]
H[2]
D[1]
H[1]
D[0]
H[0]
Only the data portion D[3:0] from each byte is applied to a teletext filter function with the corresponding
pattern bits P[3:0] and mask bits M[3:0]. Hamming protection bits are ignored by the filter.
For a WST system (PAL or NTSC), the packet prefix consists of two bytes so that two patterns are used.
Patterns 3, 4, and 5 are ignored.
The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1 in the
LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the pattern register to
the first data bit on the transaction. If these match, a true result is returned. A 0 in a bit of mask 1 means
that the filter module must ignore that data bit of the transaction. If all zeros are programmed in the mask
bits, the filter matches all patterns returning a true result (default 00h).
Pattern and mask for each byte and filter are referred as <1,2><P,M><1,2,3,4,5>, where:
<1,2> identifies the filter 1 or 2
<P,M> identifies the pattern or mask
<1,2,3,4,5> identifies the byte number
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3.20.54 Teletext Filter Control Register
Address
Default
BBh
00h
7
6
5
4
3
2
1
0
Reserved
Filter logic
Mode
TTX filter 2
enable
TTX filter 1
enable
Filter logic allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows:
00 = NOR (Default)
01 = NAND
10 = OR
11 = AND
Mode
0 = Teletext WST PAL mode B (2 header bytes) (default)
1 = Teletext NABTS NTSC mode C (5 header bytes)
TTX filter 2 enable
0 = Disabled (default)
1 = Enabled
TTX filter 1 enable
0 = Disabled (default)
1 = Enabled
If the filter matches or if the filter mask is all zeros, a true result is returned.
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3.20.55 Interrupt Status Register A
Address
Default
C0h
00h
7
6
5
4
3
2
1
0
Lock state
interrupt
Lock interrupt
Reserved
FIFO threshold
interrupt
Line interrupt
Data interrupt
The interrupt status register A can be polled by the host processor to determine the source of an interrupt.
After an interrupt condition is set, it can be reset by writing to this register with a 1 in the appropriate bit(s).
Lock state interrupt
0 = TVP5150AM1 is not locked to the video signal (default).
1 = TVP5150AM1 is locked to the video signal.
Lock interrupt
0 = A transition has not occurred on the lock signal (default).
1 = A transition has occurred on the lock signal.
FIFO threshold interrupt
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h
(default).
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt
0 = The video line number has not yet been reached (default).
1 = The video line number programmed in address CAh has occurred.
Data interrupt
0 = No data is available (default).
1 = VBI data is available either in the FIFO or in the VBI data registers.
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3.20.56 Interrupt Enable Register A
Address
Default
C1h
00h
7
6
5
4
3
2
1
0
Reserved
Lock interrupt Cycle complete
enable
Bus error
interrupt enable interrupt enable
Reserved
FIFO threshold
interrupt enable
Line interrupt
enable
Data interrupt
enable
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits
loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt
on the external pin. This register affects only the interrupt on the external terminal; it does not affect the
bits in interrupt status register A. A given condition can set the appropriate bit in the status register and not
cause an interrupt on the external terminal. To determine if this device is driving the interrupt terminal,
either perform a logical AND of interrupt status register A with interrupt enable register A, or check the
state of the interrupt A bit in the interrupt configuration register at address C2h.
Lock interrupt enable
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable
0 = Disabled (default)
1 = Enabled
Line interrupt enable
0 = Disabled (default)
1 = Enabled
Data interrupt enable
0 = Disabled (default)
1 = Enabled
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3.20.57 Interrupt Configuration Register A
Address
Default
C2h
04h
7
6
5
4
3
2
1
0
Reserved
YCbCr enable
(VDPOE)
Interrupt A
Interrupt
polarity A
YCbCr enable (VDPOE)
0 = YCbCr pins are high impedance.
1 = YCbCr pins are active if other conditions are met (default).
Interrupt A (read only)
0 = Interrupt A is not active on the external pin (default).
1 = Interrupt A is active on the external pin.
Interrupt polarity A
0 = Interrupt A is active low (default).
1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When
interrupt A is configured as active low, the terminal is driven low when active and high impedance when
inactive (open collector). Conversely, when the terminal is configured as active high, it is driven high when
active and driven low when inactive.
3.20.58 VDP Configuration RAM Register
Address
Default
C3h
DCh
C4h
0Fh
C5h
00h
Address
7
6
5
4
3
2
1
0
C3h
C4h
C5h
Configuration data
RAM address (7:0)
Reserved
RAM
address 8
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM
is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are
defined for the current VBI standards. An additional two configurations can be used as a custom
programmed mode for unique standards such as Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically
incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal
address counter with a specific start address. This can be used to write a subset of the RAM for only
those standards of interest. Registers D0h–FBh must all be programmed with FFh, before writing or
reading the configuration RAM. Full field mode (CFh) must be disabled as well.
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The suggested RAM contents are shown in Table 3-13. All values are hexadecimal.
Table 3-13. VBI Configuration RAM for Signals With Pedestal
INDEX
WST SECAM
WST SECAM
WST PAL B
ADDRESS
000
010
020
030
040
050
060
070
080
090
0A0
0B0
0C0
0D0
0E0
0F0
100
110
120
130
140
150
160
170
180
190
1A0
1B0
1C0
1D0
0
1
2
3
4
E7
E7
27
27
E7
E7
27
27
E7
E7
A7
A7
04
04
04
04
0
5
6
7
8
9
A
B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
E
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
5B
5B
38
38
0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
2A
2A
2A
2A
55
55
00
00
0
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
C5
C5
3F
3F
0
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
3F
3F
3F
3F
FF
FF
00
00
0
2E
2E
2E
2E
2E
2E
2E
2E
2E
2E
2E
2E
51
51
51
51
71
71
71
71
8F
8F
8F
8F
CE
CE
20
20
20
20
20
20
20
20
20
20
20
20
6E
6E
6E
6E
6E
6E
6E
6E
6D
6D
6D
6D
2B
2B
26
26
2B
2B
22
22
23
23
22
22
23
23
02
02
02
02
42
42
43
43
49
49
49
49
0D
0D
E6
E6
A6
A6
A6
A6
69
69
69
69
69
69
A6
A6
69
69
A6
A6
69
69
A6
A6
69
69
A6
A6
B4
B4
72
72
98
98
93
93
93
93
93
93
7B
7B
8C
8C
CD
CD
7C
7C
85
85
94
94
DA
DA
0E
0E
10
10
0D
0D
0D
0D
0D
0D
0D
0D
09
09
09
09
0F
0F
08
08
08
08
08
08
0B
0B
10
10
10
10
10
10
10
10
15
15
10
10
27
27
27
27
3A
3A
39
39
4C
4C
4C
4C
60
60
WST PAL B
WST PAL C
WST PAL C
WST NTSC
WST NTSC
NABTS, NTSC
NABTS, NTSC
NABTS, NTSC-J
NABTS, NTSC-J
CC, PAL/SECAM
CC, PAL/SECAM
CC, NTSC
CC, NTSC
WSS, PAL/SECAM
WSS, PAL/SECAM
WSS, NTSC C
WSS, NTSC C
VITC, PAL/SECAM
VITC, PAL/SECAM
VITC, NTSC
VITC, NTSC
VPS, PAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
AA
AA
AA
FF
FF
FF
FF
BA
BA
VPS, PAL
Custom 1
Programmable
Programmable
Programmable
Programmable
Custom 1
Custom 2
Custom 2
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3.20.59 VDP Status Register
Address
C6h
7
6
5
4
3
2
1
0
FIFO full error
FIFO empty
TTX available
CC field 1
available
CC field 2
available
WSS available VPS available VITC available
The VDP status register indicates whether data is available in either the FIFO or data registers, and status
information about the FIFO. Reading data from the corresponding register does not clear the status flags
automatically. These flags are only reset by writing a 1 to the respective bit. However, bit 6 is updated
automatically.
FIFO full error
0 = No FIFO full error
1 = FIFO was full during a write to FIFO.
The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if
the FIFO has only ten bytes left and teletext is the current VBI line, the FIFO full error flag is set, but no
data is written because the entire teletext line does not fit. However, if the next VBI line is closed
caption requiring only two bytes of data plus the header, this goes into the FIFO, even if the full error
flag is set.
FIFO empty
0 = FIFO is not empty.
1 = FIFO is empty.
TTX available
0 = Teletext data is not available.
1 = Teletext data is available.
CC field 1 available
0 = Closed caption data from field 1 is not available.
1 = Closed caption data from field 1 is available.
CC field 2 available
0 = Closed caption data from field 2 is not available.
1 = Closed caption data from field 2 is available.
WSS available
0 = WSS data is not available.
1 = WSS data is available.
VPS available
0 = VPS data is not available.
1 = VPS data is available.
VITC available
0 = VITC data is not available.
1 = VITC data is available.
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3.20.60 FIFO Word Count Register
Address
C7h
7
6
5
4
3
2
1
0
Number of words
This register provides the number of words in the FIFO. One word equals two bytes.
3.20.61 FIFO Interrupt Threshold Register
Address
Default
C8h
80h
7
6
5
4
3
2
1
0
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this
value (default 80h). This interrupt must be enabled at address C1h. One word equals two bytes.
3.20.62 FIFO Reset Register
Address
Default
C9h
00h
7
6
5
4
3
2
1
0
Any data
Writing any data to this register resets the FIFO and clears any data present in all VBI read registers.
3.20.63 Line Number Interrupt Register
Address
Default
CAh
00h
7
6
5
4
3
2
1
0
Field 1 enable
Field 2 enable
Line number
This register is programmed to trigger an interrupt when the video line number matches this value in 5:0
bits. This interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt.
Field 1 enable
0 = Disabled (default)
1 = Enabled
Field 2 enable
0 = Disabled (default)
1 = Enabled
Line number default is 00h.
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3.20.64 Pixel Alignment Registers
Address
Default
CBh
4Eh
CCh
00h
Address
7
6
5
4
3
2
1
0
CBh
CCh
Switch pixel [7:0]
Reserved
Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP
controller initiates the program from one line standard to the next line standard; for example, the previous
line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the
previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be
programmed before the current settings are required.
3.20.65 FIFO Output Control Register
Address
Default
CDh
01h
7
6
5
4
3
2
1
0
Reserved
Host access
enable
This register is programmed to allow I2C access to the FIFO or allowing all VDP data to go out the video
port.
Host access enable
0 = Output FIFO data to the video output Y[7:0]
1 = Allow I2C access to the FIFO data (default)
3.20.66 Full Field Enable Register
Address
Default
CFh
00h
7
6
5
4
3
2
1
0
Reserved
Full field enable
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines
in the line mode registers programmed with FFh are sliced with the definition of register FCh. Values other
than FFh in the line mode registers allow a different slice mode for that particular line.
Full field enable
0 = Disable full field mode (default)
1 = Enable full field mode
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3.20.67 Line Mode Registers
Address
Default
D0h
00h
D1h–FBh
FFh
Address
7
6
5
4
3
2
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
Line 6 Field 1
Line 6 Field 2
Line 7 Field 1
Line 7 Field 2
Line 8 Field 1
Line 8 Field 2
Line 9 Field 1
Line 9 Field 2
Line 10 Field 1
Line 10 Field 2
Line 11 Field 1
Line 11 Field 2
Line 12 Field 1
Line 12 Field 2
Line 13 Field 1
Line 13 Field 2
Line 14 Field 1
Line 14 Field 2
Line 15 Field 1
Line 15 Field 2
Line 16 Field 1
Line 16 Field 2
Line 17 Field 1
Line 17 Field 2
Line 18 Field 1
Line 18 Field 2
Line 19 Field 1
Line 19 Field 2
Line 20 Field 1
Line 20 Field 2
Line 21 Field 1
Line 21 Field 2
Line 22 Field 1
Line 22 Field 2
Line 23 Field 1
Line 23 Field 2
Line 24 Field 1
Line 24 Field 2
Line 25 Field 1
Line 25 Field 2
Line 26 Field 1
Line 26 Field 2
Line 27 Field 1
Line 27 Field 2
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These registers program the specific VBI standard at a specific line in the video field.
Bit 7
0 = Disable filtering of null bytes in closed caption modes
1 = Enable filtering of null bytes in closed caption modes (default)
In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, the data
filter passes all data on that line.
Bit 6
0 = Send VBI data to registers only
1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO (default).
Bit 5
0 = Allow VBI data with errors in the FIFO
1 = Do not allow VBI data with errors in the FIFO (default)
Bit 4
0 = Do not enable error detection and correction
1 = Enable error detection and correction (when bits [3:0] = 1 2, 3, and 4 only) (default)
Bits [3:0]
0000 = WST SECAM
0001 = WST PAL B
0010 = WST PAL C
0011 = WST NTSC
0100 = NABTS NTSC
0101 = TTX NTSC
0110 = CC PAL
0111 = CC NTSC
1000 = WSS PAL
1001 = WSS NTSC
1010 = VITC PAL
1011 = VITC NTSC
1100 = VPS PAL
1101 = Custom 1
1110 = Custom 2
1111 = Active video (VDP off) (default)
A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode.
3.20.68 Full Field Mode Register
Address
Default
FCh
7Fh
7
6
5
4
3
2
1
0
Full field mode
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual
line settings take priority over the full field register. This allows each VBI line to be programmed
independently but have the remaining lines in full field mode. The full field mode register has the same
definitions as the line mode registers (default 7Fh).
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4
Electrical Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
IO_DVDD to DGND
–0.5 V to 4.5 V
–0.5 V to 2.3 V
–0.5 V to 2.3 V
–0.5 V to 2.3 V
–0.5 V to 4.5 V
–0.5 V to 2.3 V
–0.2 V to 2.0 V
–0.5 V to 4.5 V
–65°C to 150°C
DVDD to DGND
Supply voltage range
PLL_AVDD to PLL_AGND
CH_AVDD to CH_AGND
Digital input voltage range, VI to DGND
Input voltage range, XTAL1 to PLL_GND
Analog input voltage range AI to CH_AGND
Digital output voltage range, VO to DGND
Storage temperature range, Tstg
4.2 Recommended Operating Conditions
MIN NOM
MAX UNIT
IO_DVDD
DVDD
PLL_AVDD
CH_AVDD
VI(P-P)
Digital I/O supply voltage
Digital supply voltage
3.0
3.3
1.8
1.8
1.8
3.6
1.95
1.95
1.95
0.75
V
V
1.65
Analog PLL supply voltage
Analog core supply voltage
Analog input voltage (ac-coupling necessary)
Digital input voltage high
1.65
V
1.65
0
V
V
VIH
0.7 IO_DVDD
V
VIL
Digital input voltage low
0.3 IO_DVDD
V
VIH_XTAL
VIL_XTAL
IOH
XTAL input voltage high
0.7 PLL_AVDD
V
XTAL input voltage low
0.3 PLL_AVDD
V
High-level output current
2
–2
mA
mA
mA
mA
°C
IOL
Low-level output current
IOH_SCLK
IOL_SCLK
TA
SCLK high-level output current
SCLK low-level output current
Operating free-air temperature
4
–4
–55
125
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4.3 Electrical Characteristics
DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH_AVDD = 1.8 V, IO_DVDD = 3.3 V
For minimum/maximum values TA = -55°C to 125°C, for typical values TA = 25°C (unless otherwise noted)
4.3.1 DC Electrical Characteristics
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS(1)
Color bar input(2)
Color bar input(2)
Color bar input(2)
Color bar input(2)
Color bar input(2)
Color bar input
By design
IDD(IO_D)
IDD(D)
IDD(PLL_A)
IDD(CH_A)
PTOT
3.3-V I/O digital supply current
1.8-V digital supply current
1.8-V analog PLL supply current
1.8-V analog core supply current
Total power dissipation, normal mode
Total power dissipation, power-down mode(3)
Input capacitance
4.8
25.3
5.4
24.4
115
1
10.0 mA
32.9 mA
7.1 mA
36.0 mA
160 mW
mW
PDOWN
Ci
8
pF
VOH
Output voltage high
IOH = 2 mA
0.8 IO_DVDD
0.8 IO_DVDD
V
VOL
Output voltage low
IOL = –2 mA
0.22 IO_DVDD
V
V
VOH_SCLK SCLK output voltage high
IOH = 4 mA
VOL_SCLK
SCLK output voltage low
High-level input current(4)
Low-level input current(4)
IOL = –4 mA
0.22 IO_DVDD
V
IIH
IIL
VI = VIH
±28
±28
µA
µA
VI = VIL
(1) Measured with a load of 15 pF
(2) For typical measurements only
(3) Specified by device characterization
(4) YOUT7 is a bidirectional terminal with an internal pulldown resistor. This terminal may sink more than the specified current when in
RESET mode.
4.3.2 Analog Electrical Characteristics
PARAMETER
Input impedance, analog video inputs
Input capacitance, analog video inputs
Input voltage range(1)
TEST CONDITIONS
MIN
TYP
500
10
MAX UNIT
Zi
By design
By design
kΩ
Ci
pF
Vi(pp)
ΔG
ΔG
DNL
INL
Fr
Ccoupling = 0.1 µF
0
0.75
V
Gain control maximum
Gain control minimum
DC differential nonlinearity
DC integral nonlinearity
Frequency response
12
0
dB
dB
A/D only
±0.5
±1
±1 LSB
A/D only
±2.5 LSB
6 MHz, Specified by design
6 MHz, 1.0 VP-P
50% flat field
–0.9
50
–3
dB
dB
dB
°
SNR
NS
DP
DG
Signal-to-noise ratio
Noise spectrum
50
Differential phase
1.5
0.5
Differential gain
%
(1) The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The recommended termination resistors are 37.4 Ω, as
seen in Section 6.
70
Electrical Specifications
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TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
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SLES213–MAY 2008
4.3.3 Clocks, Video Data, Sync Timing
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX UNIT
Duty cycle, PCLK
50
%
t1
t2
t3
t4
t5
t6
PCLK high time
PCLK low time
PCLK fall time
PCLK rise time
Output hold time
Output delay time
≥80%
≤20%
16.0
16.0
22.0
22.0
ns
ns
ns
ns
ns
ns
80% to 20%
20% to 80%
4
4
2
3
(1) Measured with a load of 15 pF. Specified by design.
t
t
2
1
PCLK
t
t
4
3
V
V
OH
Y, C, AVID,
VS, HS, FID
Valid Data
Valid Data
OL
t
5
t
6
Figure 4-1. Clocks, Video Data, and Sync Timing
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Electrical Specifications
71
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
SLES213–MAY 2008
www.ti.com
4.3.4 I2C Host Port Timing(1)
PARAMETER
MIN
1.3
0.6
0.6
0.6
100
0
TYP
MAX UNIT
t1
Bus free time between Stop and Start
Setup time for a (repeated) Start condition
Hold time (repeated) Start condition
Setup time for a Stop condition
Data setup time
µs
µs
µs
ns
ns
t2
t3
t4
t5
t6
Data hold time
0.9
µs
ns
ns
pF
t7
Rise time, VC1(SDA) and VC0(SCL) signal
Fall time, VC1(SDA) and VC0(SCL) signal
Capacitive load for each bus line
I2C clock frequency
250
t8
250
Cb
fI2C
400
400 kHz
(1) Specified by design for industrial temperature
Stop Start
Stop
VC1 (SDA)
VC0 (SCL)
Data
t
t3
1
t5
t3
t6
t4
t2
t
7
t
8
Figure 4-2. I2C Host Port Timing
4.4 Estimated Device Life
1000
100
Kirkendall Voiding Fail Mode
10
Electromigration Fail Mode
1
85
95
105
115
125
135
145
155
165
Continuous TJ (°C)
Figure 4-3. TVP5150AM1 Estimated Device Life at Elevated Temperatures
72
Electrical Specifications
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TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
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SLES213–MAY 2008
5
Example Register Settings
The following example register settings are provided as a reference. These settings, given the assumed
input connector, video format, and output format, set up the TVP5150AM1 decoder and provide video
output. Example register settings for other features and the VBI data processor are not provided here.
5.1 Example 1
5.1.1 Assumptions
Device: TVP5150AM1
Input connector: Composite (AIP1A)
Video format: NTSC-M, PAL (B, G, H, I), or SECAM
NOTE
NTSC-443, PAL-N, and PAL-M are masked from the autoswitch process by default. See
the autoswitch mask register at address 04h.
Output format: 8-bit ITU-R BT.656 with embedded syncs
5.1.2 Recommended Settings
Recommended I2C writes: For this setup, only one write is required. All other registers are set up by
default.
I2C register address 03h = Miscellaneous controls register address
I2C data 09h = Enables YCbCr output and the clock output
NOTE
HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default. See the
miscellaneous control register at address 03h.
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Example Register Settings
73
TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
SLES213–MAY 2008
www.ti.com
5.2 Example 2
5.2.1 Assumptions
Device: TVP5150AM1
Input connector: S-video (AIP1A (luma), AIP1B (chroma))
Video format: NTSC-M, 443, PAL (B, G, H, I, M, N) or SECAM (B, D, G, K, KI, L)
Output format: 8-bit 4:2:2 YCbCr with discrete sync outputs
5.2.2 Recommended Settings
Recommended I2C writes: This setup requires additional writes to output the discrete sync 4:2:2 data
outputs, the HSYNC, and the VSYNC, and to autoswitch between all video formats mentioned above.
I2C register address 00h = Video input source selection 1 register
I2C data 01h = Selects the S-Video input, AIP1A (luma), and AIP1B (chroma)
<br/>
I2C register address 03h = Miscellaneous controls register address
I2C data 0Dh = Enables the YCbCr output data, HSYNC, VSYNC/PALI, AVID, and FID/GLCO
<br/>
I2C register address 04h = Autoswitch mask register
I2C data C0h = Unmask NTSC-443, PAL-N, and PAL-M from the autoswitch process
<br/>
I2C register address 0Dh = Outputs and data rates select register
I2C data 40h = Enables 8-bit 4:2:2 YCbCr with discrete sync output
74
Example Register Settings
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TVP5150AM1-EP
Ultralow-Power NTSC/PAL/SECAM Video Decoder
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SLES213–MAY 2008
6
Application Information
6.1 Application Example
C2
1 µF
C1
1 µF
C3
1 µF
PDN
PDN
INTERQ/GPCL
INTERQ/GPCL
AVID
AVID
HSYNC
HSYNC
C4
0.1 µF
R1
AVDD
0.1 µF
C11
IO_DVDD
CH1_IN
37.4 Ω
R2
37.4 Ω
R4
1.2K
R3
1.2K
0.1 µF
R5
C5
1
2
3
4
5
6
7
8
24
VSYNC/PALI
FID/GLCO
SDA
VSYNC/PALI
FID/GLCO
AIP1A
VSYNC/PALI
FID/GLCO
SDA
23
22
21
20
19
18
17
CH2_IN
AIP1B
37.4 Ω
PLL_AGND
PLL_AVDD
XTAL1/OSC
XTAL2
AVDD
SCL
DVDD
SCL
TVP5150AM1
R6
DVDD
37.4 Ω
C6
0.1 µF
DGND
C7
0.1 µF
AGND
YOUT0
YOUT1
RESETB
S1
OSC
1
2
OSC_IN
Y1
R
PCLK/SCLK
PCLK/SCLK
RESETB
14.31818 MHz
IO_DVDD
C8
C9
YOUT[7:0]
IO_DVDD
C10
0.1 µF
CL1
CL2
R7
Implies I2C address is BAh. If B8h is to be used,
connect pulldown resistor to digital ground.
10K
A. The use of INTERQ/GPCL/AVID/HSYNC and VSYNC is optional. These are outputs and can be left floating.
B. When OSC is connected through S1, remove the capacitors for the crystal.
C. PDN needs to be high if device has to be always operational.
D. RESETB is operational only when PDN is high. This allows an active low reset to the device.
E. Resistor in parallel with the crystal may or may not be required depending on the crystal used.
Figure 6-1. Application Example
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Application Information
75
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TVP5150AM1MPBSREP TQFP
PBS
32
2000
330.0
16.4
7.2
7.2
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PBS 32
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TVP5150AM1MPBSREP
2000
Pack Materials-Page 2
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