V62/18613-01XE [TI]
采用增强型航天塑料的 2.2V 至 36V 耐辐射微功耗四路比较器 | PW | 14 | -55 to 125;
| 型号： | V62/18613-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用增强型航天塑料的 2.2V 至 36V 耐辐射微功耗四路比较器 | PW | 14 | -55 to 125 放大器 光电二极管 比较器 |
| 文件： | 总23页 (文件大小：1652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
TLV1704-SEP 采用增强型航天塑料的2.2V 至36V 耐辐射微功耗
四路比较器
1 特性
2 应用
• VID V62/18613
• 耐辐射
• 命令和数据处理(C&DH)
• 飞行器驾驶舱显示屏
• 飞行控制单元
– 单粒子闩锁(SEL) 在125°C 下的抗扰度可达
43MeV-cm2/mg
• 卫星电力系统(EPS)
– 在30 krad(Si) 的条件下无ELDRS
– 每个晶圆批次的RLAT 总电离剂量(TID) 高达
20krad(Si)
3 说明
TLV1704-SEP（四路）器件具有宽电源电压范围、轨
到轨输入、低静态电流和低传播延迟。凭借符合行业标
准且在极小型封装内集成的上述特性，此类器件成为当
前市场中的最佳通用比较器。
• 增强型航天塑料
– 受控基线
– 金线
– NiPdAu 铅涂层
– 一个组装和测试基地
– 一个制造基地
– 支持军用（–55°C 至125°C）温度范围
– 延长了产品生命周期
– 延长了产品变更通知
– 产品可追溯性
集电极开路输出带来了能够将输出拉至任意电压轨（最
多可高出负电源 36V）且不受 TLV1704-SEP 电源电压
影响的优势。
此器件是一款微功耗比较器。低输入失调电压、低输入
偏置电流、低电源电流和集电极开路配置使 TLV1704-
SEP 器件能够灵活处理从简单电压检测到驱动单个继
电器的大部分应用。
– 采用增强型模塑化合物实现低释气
• 电源电压范围：2.2V 至36V 或±1.1V 至±18V
• 低静态电流：每个比较器55µA
• 输入共模范围包括两个电源轨
• 低传播延迟：560ns
• 低输入失调电压：300µV
• 集电极开路输出：
器件信息
等级(1)
器件型号
封装
TLV1704AMPWTPSEP
TLV1704AMPWPSEP
20krad(Si) RLAT
TSSOP (14)
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
– 最多可高出负电源电压36V 且不受电源电压影
响
• 小型封装：
– 四通道：TSSOP-14
1200
ê18 V Low-to-High
ê18 V High-to-Low
2.2 V Low-to-High
1000
2.2 V High-to-Low
800
600
400
200
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D001
稳定传播延迟与温度
TLV1704-SEP 用作窗口比较器
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOSE29
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................10
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
8.3 Power Supply Recommendations.............................12
8.4 Layout....................................................................... 13
9 Device and Documentation Support............................14
9.1 Documentation Support............................................ 14
9.2 接收文档更新通知..................................................... 14
9.3 支持资源....................................................................14
9.4 Trademarks...............................................................14
9.5 Electrostatic Discharge Caution................................14
9.6 术语表....................................................................... 14
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Typical Characteristics................................................6
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
Information.................................................................... 15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2018) to Revision A (November 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 将标题从“抗辐射”更新为“耐辐射”...............................................................................................................1
• 使用链接更新了“应用”部分.............................................................................................................................1
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
5 Pin Configuration and Functions
2OUT
1OUT
V+
1
2
3
4
5
6
7
14 3OUT
4OUT
V-
13
12
11
10
9
1INœ
1IN+
4IN+
4INœ
2INœ
3IN+
2IN+
3INœ
8
图5-1. TLV1704-SEP PW Package 14-Pin TSSOP Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
IN+
I
I
Noninverting input.
—
5
1IN+
2IN+
3IN+
4IN+
IN–
Noninverting input, channel 1.
Noninverting input, channel 2.
Noninverting input, channel 3.
Noninverting input, channel 4.
Inverting input.
7
I
9
I
11
I
I
—
4
I
Inverting input, channel 1.
Inverting input, channel 2.
Inverting input, channel 3.
Inverting input, channel 4.
Output.
1IN–
2IN–
3IN–
4IN–
OUT
1OUT
2OUT
3OUT
4OUT
V+
6
I
8
I
10
I
O
O
O
O
O
—
—
—
2
Output, channel 1.
1
Output, channel 2.
14
13
3
Output, channel 3.
Output, channel 4.
Positive (highest) power supply.
Negative (lowest) power supply.
12
V–
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40 (±20)
(VS+) + 0.5
±10
UNIT
V
Supply voltage
Voltage(2)
Signal input pins
V
(VS–) –0.5
Current(2)
mA
mA
°C
Output short-circuit(3)
Continuous
Operating Junction temperature, TJ
Storage temperature, Tstg
125
150
–55
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground; one comparator per package.
6.2 ESD Ratings
VALUE
±1000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.2 (±1.1)
–55
NOM
MAX
36 (±18)
125
UNIT
V
Supply voltage VS = (VS+) –(VS–)
Specified temperature
°C
6.4 Thermal Information
TLV1704-SEP
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
128.1
56.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-board thermal resistance
69.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.1
ψJT
69.3
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
6.5 Electrical Characteristics
at TA = –55°C to 125°C, VS = 2.2 V to 36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
TA = 25°C, VS = 2.2 V
±0.5
±0.3
±3.5
±2.5
±5.5
±20
mV
mV
mV
TA = 25°C, VS = 36 V
TA = –55°C to 125°C
TA = –55°C to 125°C
TA = 25°C
VOS
Input offset voltage
dVOS/dT
PSRR
Input offset voltage drift
±4
15
20
μV/°C
μV/V
μV/V
100
Power-supply rejection ratio
TA = –55°C to 125°C
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
(V+)
V
TA = –55°C to 125°C
(V–)
INPUT BIAS CURRENT
TA = 25°C
5
15
20
nA
nA
nA
IB
Input bias current
TA = –55°C to 125°C
TA = 25°C
IOS
Input offset current
0.5
CLOAD
OUTPUT
Capacitive load drive
See 节6.7
IO ≤4 mA, input overdrive = 100 mV,
VS = 36 V
1100
700
mV
mV
VO
Voltage output swing from rail
IO = 0 mA, input overdrive = 100 mV,
VS = 36 V
ISC
Short circuit sink current
Output leakage current
TA = 25°C
20
70
mA
nA
VIN+ > VIN–, TJ = 25°C
POWER SUPPLY
VS
Specified voltage range
2.2
36
75
V
IO = 0 A , TA = 25°C
55
μA
μA
IQ
Quiescent current (per channel)
100
IO = 0 A, TA = –55°C to 125°C
6.6 Switching Characteristics
at TA = –55°C to 125°C, VS = 2.2 V to 36 V, CL = 15 pF, RPULLUP = 5.1 kΩ, VCM = VS / 2, and VS = VPULLUP (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input overdrive = 100 mV, TA
25°C
=
=
=
=
tpHL
tpLH
tR
Propagation delay time, high-to-low
460
ns
Input overdrive = 100 mV, TA
25°C
Propagation delay time, low-to-high
560
365
240
ns
ns
ns
Input overdrive = 100 mV, TA
25°C
Rise time
Fall time
Input overdrive = 100 mV, TA
25°C
tF
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
75
70
65
60
55
50
45
40
35
6
4
2
0
VS = 2.2 V - lbn
VS = 2.2 V - lbp
VS = ê18 V - lbp
VS = ê18 V - lbn
VS = 2.2 V
VS = ê18 V
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D004
D003
图6-1. Quiescent Current vs Temperature
图6-2. Input Bias Current vs Temperature
1
0.75
0.5
0
œ2
VS = 2.2 V
VS = ê18 V
VS
=
1.1 V
œ4
œ6
œ8
œ10
œ12
œ14
œ16
œ18
0.25
VS
= 18 V
0
-55
0
5
10
Output Current (mA)
15
20
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
C011
D002
图6-4. Output Voltage vs Output Current
图6-3. Input Offset Current vs Temperature
3
2
1
0
3
2
1
0
-1
-1
-2
-3
-2
-3
0
6
12
Common-Mode Voltage (V)
18
24
30
36
0
0.5
1
Common-Mode Voltage (V)
1.5
2
D003
D002
VS = ±18 V
14 typical units shown
VS = 2.2 V
13 typical units shown
图6-5. Offset Voltage vs Common-Mode Voltage
图6-6. Offset Voltage vs Common-Mode Voltage
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
3
1000n
800n
600n
400n
200n
±18 V Low-to-High
±18 V High-to-Low
2.2 V Low-to-High
2.2 V High-to-Low
2
1
0
-1
-2
-3
0
200
400
600
800
1000
Input Overdrive (mV)
C020
0
6
12
18
Supply Voltage (V)
24
30
36
D001
图6-8. Propagation Delay vs Input Overdrive
16 typical units shown
图6-7. Offset Voltage vs Supply Voltage
1200
4.0ꢀ
3.5ꢀ
3.0ꢀ
2.5ꢀ
2.0ꢀ
1.5ꢀ
1.0ꢀ
0.5ꢀ
0.0ꢀ
ê18 V Low-to-High
ê18 V High-to-Low
2.2 V Low-to-High
2.2 V High-to-Low
2.2 V Supply
±18 V Supply
1000
800
600
400
200
tPLH
tPHL
20p
200p
2n
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Output Capacitive Load (F)
C020
D001
图6-9. Propagation Delay vs Capacitive Load
VOD = 100 mV
图6-10. Propagation Delay vs Temperature
,QSXWꢀ9ROWDJHꢀ
2XWSXWꢀ9ROWDJHꢀ
W3/+ꢀ ꢀꢈꢈꢃꢀQVꢀ
W3/+ꢀ ꢀꢈꢃꢃꢀQVꢀ
2XWSXWꢀ9ROWDJHꢀ
,QSXWꢀ9ROWDJHꢀ
7LPHꢀꢁꢂꢆꢃꢀQVꢄGLYꢅꢀ
7LPHꢀꢁꢂꢆꢃꢀQVꢄGLYꢅꢀ
&ꢃꢃꢇꢀ
&ꢃꢃꢇꢀ
VS = 36 V
Overdrive = 100 mV
VS = 36 V
Overdrive = 100 mV
图6-11. Propagation Delay (TpLH
)
图6-12. Propagation Delay (TpHL)
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
6.7 Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, RPULLUP = 5.1 kΩ, and input overdrive = 100 mV (unless otherwise noted)
2XWSXWꢀ9ROWDJHꢀ
,QSXWꢀ9ROWDJHꢀ
W3/+ꢀ ꢀꢂꢈꢃꢀQVꢀ
W3/+ꢀ ꢀꢇꢈꢃꢀQVꢀ
2XWSXWꢀ9ROWDJHꢀ
,QSXWꢀ9ROWDJHꢀ
7LPHꢀꢁꢆꢂꢃꢀQVꢄGLYꢅꢀ
7LPHꢀꢁꢆꢂꢃꢀQVꢄGLYꢅꢀ
&ꢃꢃꢇꢀ
&ꢃꢆꢃꢀ
VS = 2.2 V
Overdrive = 100 mV
VS = 2.2 V
Overdrive = 100
mV
图6-13. Propagation Delay (TpLH
)
图6-14. Propagation Delay (TpHL
)
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
D005
D004
Offset Voltage (mV)
Offset Voltage (mV)
VS = ±18 V
Distribution taken from 2524 comparators
VS = 2.2 V
Distribution taken from 2524 comparators
图6-15. Offset Voltage Production Distribution
图6-16. Offset Voltage Production Distribution
30
VS = 2.2 V
25
20
15
10
5
0
0
6
12
18
24
30
36
Supply Voltage (V)
C016
Sink current
图6-17. Short-Circuit Current vs Supply Voltage
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TLV1704-SEP comparator features rail-to-rail input and output on supply voltages as high as 36 V. The rail-
to-rail input stage enables detection of signals close to the supply and ground. The open-collector configuration
allows the device to be used in wired-OR configurations, such as a window comparator. A low supply current of
55 μA per channel with small, space-saving packages, makes these comparators versatile for use in a wide
range of applications, from portable to industrial.
7.2 Functional Block Diagram
V+
OUT
IN+
IN-
IN+
IN-
V-
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
7.3 Feature Description
7.3.1 Comparator Inputs
The TLV1704-SEP device is a rail-to-rail input comparator, with an input common-mode range that includes the
supply rails. The TLV1704-SEP device is designed to prevent phase inversion when the input pins exceed the
supply voltage. 图 7-1 shows the TLV1704-SEP device response when input voltages exceed the supply,
resulting in no phase inversion.
Output Voltage
Input Voltage
Time (5 ms/div)
C030
图7-1. No Phase Inversion: Comparator Response to Input Voltage (Propagation Delay Included)
7.4 Device Functional Modes
7.4.1 Setting Reference Voltage
Using a stable reference is important when setting the transition point for the TLV1704-SEP device. The
REF3333, as shown in 图 7-2, provides a 3.3-V reference voltage with low drift and only 3.9 μA of quiescent
current.
V
S
REF3333
GND
V
(PULLUP)
V
S+
R
(PULLUP)
+
Device
V
O
_
V
Sœ
V
I
图7-2. Reference Voltage for the TLV1704-SEP
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TLV1704-SEP device can be used in a wide variety of applications, such as zero crossing detectors, window
comparators, over and undervoltage detectors, and high-side voltage sense circuits.
8.2 Typical Application
Comparators are used to differentiate between two different signal levels. For example, a comparator
differentiates between an overtemperature and normal-temperature condition. However, noise or signal variation
at the comparison threshold causes multiple transitions. This application example sets upper and lower
hysteresis thresholds to eliminate the multiple transitions caused by noise.
5 V
Rp
5 kΩ
-
+V
+
Vout
5 V
Vin
5 V
Rx
100 kΩ
Rh
576 kΩ
Ry
100 kΩ
图8-1. Comparator Schematic With Hysteresis
8.2.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 5 V
• Input: 0 V to 5 V
• Lower threshold (VL) = 2.3 V ±0.1 V
• Upper threshold (VH) = 2.7 V ±0.1 V
• VH –VL = 2.4 V ±0.1 V
• Low-power consumption
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
8.2.2 Detailed Design Procedure
Make a small change to the comparator circuit to add hysteresis. Hysteresis uses two different threshold
voltages to avoid the multiple transitions introduced in the previous circuit. The input signal must exceed the
upper threshold (VH) to transition low, or below the lower threshold (VL) to transition high.
图 8-1 illustrates hysteresis on a comparator. Resistor Rh sets the hysteresis level. An open-collector output
stage requires a pullup resistor (Rp). The pullup resistor creates a voltage divider at the comparator output that
introduces an error when the output is at logic high. This error can be minimized if Rh > 100 Rp.
When the output is at a logic high (5 V), Rh is in parallel with Rx (ignoring Rp). This configuration drives more
current into Ry, and raises the threshold voltage (VH) to 2.7 V. The input signal must drive above VH = 2.7 V to
cause the output to transition to logic low (0 V).
When the output is at logic low (0 V), Rh is in parallel with Ry. This configuration reduces the current into Ry, and
reduces the threshold voltage to 2.3 V. The input signal must drive below VL = 2.3 V to cause the output to
transition to logic high (5 V).
For more details on this design and other alternative devices that can be used in place of the TLV1702, refer to
Precision Design TIPD144, Comparator with Hysteresis Reference Design.
8.2.3 Application Curve
图 8-2 shows the upper and lower thresholds for hysteresis. The upper threshold is 2.76 V and the lower
threshold is 2.34 V, both of which are close to the design target.
图8-2. TLV1701 Upper and Lower Threshold With Hysteresis
8.3 Power Supply Recommendations
The TLV1704-SEP device is specified for operation from 2.2 V to 36 V (±1.1 to ±18 V); many specifications apply
from –55°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the 节6.7 section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the 节6.1.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement; see the 节 8.4.1
section.
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
8.4 Layout
8.4.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, maintain the following layout guidelines:
• Use a printed-circuit board (PCB) with a good, unbroken low-inductance ground plane. Proper grounding (use
of ground plane) helps maintain specified performance of the TLV1704-SEP device.
• To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) as close
as possible to VS as shown in 图8-3.
• On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from the output.
• Solder the device directly to the PCB rather than using a socket.
• For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to propagation delay when the impedance is low. Run the topside ground plane between the
output and inputs.
• Run the ground pin ground trace under the device up to the bypass capacitor, shielding the inputs from the
outputs.
8.4.2 Layout Example
Ground
Bypass
Capacitor
1
2
3
14
13
12
1OUT
2OUT
3OUT
4OUT
0.1 μF
Positive Supply
V
Negative Supply or Ground
GND
4IN+
4IN–
3IN+
CC
Only needed
for dual power
supplies
4
5
6
7
2IN–
2IN+
1IN–
1IN+
11
10
9
0.1 μF
Ground
8
3IN–
图8-3. Comparator Board Layout
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
9 Device and Documentation Support
9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Precision Design, Comparator with Hysteresis Reference Design, TIDU020
• REF33xx 3.9-μA, SC70-3, SOT-23-3, and UQFN-8, 30-ppm/°C Drift Voltage Reference, SBOS392
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TLV1704-SEP
TLV1704-SEP
ZHCSJ09A –NOVEMBER 2018 –REVISED NOVEMBER 2022
www.ti.com.cn
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TLV1704-SEP
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV1704AMPWPSEP
TLV1704AMPWTPSEP
V62/18613-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
14
14
14
14
90
250
250
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
1704SEP
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
1704SEP
1704SEP
1704SEP
V62/18613-01XE-T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV1704-SEP :
Automotive : TLV1704-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV1704AMPWTPSEP TSSOP
PW
14
250
180.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TLV1704AMPWTPSEP
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TLV1704AMPWPSEP
V62/18613-01XE-T
PW
PW
TSSOP
TSSOP
14
14
90
90
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明