VSP5010PMR [TI]
12-Bit, 31-MSPS, Dual-Channel CCD ANALOG FRONT-END FOR DIGITAL COPIERS; 12位, 31 - MSPS ,双通道CCD模拟前端数码复印机型号: | VSP5010PMR |
厂家: | TEXAS INSTRUMENTS |
描述: | 12-Bit, 31-MSPS, Dual-Channel CCD ANALOG FRONT-END FOR DIGITAL COPIERS |
文件: | 总25页 (文件大小:711K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
VSP5010
www.ti.com ................................................................................................................................................................................................ SBES014–AUGUST 2008
12-Bit, 31-MSPS, Dual-Channel
CCD ANALOG FRONT-END FOR DIGITAL COPIERS
1
FEATURES
APPLICATIONS
•
•
•
Copiers
Scanners
Facsimiles
2
•
Dual-Channel CCD Processing:
–
–
–
–
Correlated Double Sampler (CDS)
Sample-and-Hold Mode (S/H)
Digital Programmable Amplifier
CCD Offset Correction (OB Loop)
DESCRIPTION
The VSP5010 is a complete application-specific
standard product (ASP) for charge-coupled device
(CCD) line sensor applications such as copiers,
scanners, and facsimiles. The VSP5010 provides two
independent line-processing channels, and performs
analog front-end (AFE) data processing and
analog-to-digital conversion. Each channel features
•
High-Performance ADC:
–
–
–
–
12-Bit Resolution
INL: ±2 LSB
DNL: ±0.5 LSB
No Missing Codes Ensured
correlated
double
sampling
(CDS)
and
•
•
High-Speed Operation:
sample-and-hold (S/H) processing stages, 14
analog-to-digital converter (ADC) blocks, a digital
programmable gain amplifier (DPGA), and an optical
black (OB) correction loop. Data are output in a 12-bit
word; two-channel ADC data are multiplexed and
then output.
–
Sample Rate: 31 MHz (max, Design
Ensured)
–
78-dB SNR (at 0-dB Gain)
Low-Power Consumption:
–
–
–
Low Voltage: 3.0 V to 3.6 V
Low Power: 290 mW (typ at 3.3 V)
Standby Mode: 20 mW (typ)
The VSP5010 operates from a single 3.3-V supply.
The device is available in an LQFP-64 package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008, Texas Instruments Incorporated
VSP5010
SBES014–AUGUST 2008 ................................................................................................................................................................................................ www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
VSP5010PM
Tray, 160 Pieces
VSP5010PM
LQFP-64
PM
–25°C to +85°C
VSP5010PM
VSP5010PMR
Tape and Reel, 1000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
VSP5010
+4.0
UNIT
V
Supply voltage
VCC, VDD
VCC, VDD
Supply voltage differences
Ground voltage differences
Digital input voltage
±0.1
V
AGND, DGND
±0.1
V
–0.3 to (VDD + 0.3)
–0.3 to (VCC + 0.3)
±10
V
Analog input voltage
V
Input current (all pins except supplies)
Ambient temperature under bias
Storage temperature
mA
°C
°C
°C
°C
°C
–40 to +125
–55 to +150
+150
Junction temperature
Lead temperature (soldering, 5s)
Package temperature (IR reflow, peak, 10s)
+260
+235
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
MIN
3
NOM
3.3
MAX
3.6
UNIT
V
Analog supply voltage
VCC
VDD
Digital supply voltage
3
3.3
3.6
V
Analog input voltage, full-scale (0 dB)
Digital input logic family
1
CMOS
Digital input clock frequency
Digital output load capacitance
Operating free-air temperature, TA
System clock
10
30
MHz
pF
30
–25
+85
°C
2
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ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, unless otherwise noted.
VSP5010PM
PARAMETER
TEST CONDITIONS
MIN
TYP
12
2
MAX
UNIT
Bits
RESOLUTION
Resolution
SIGNAL PASS
Signal pass
Channels
MHz
MAXIMUM CONVERSION RATE
Maximum conversion rate
DIGITAL INPUT
30
VT+
VT–
IIH
Positive-going threshold
Negative-going threshold
Logic high, VIN = +3 V
Logic low, VIN = 0 V
1.8
1.1
V
V
Input voltage
±20
±20
µA
µA
Input current
Input limit
IIL
VCC +
0.3
–0.3
V
SYSCLK clock duty cycle
Input capacitance
50
5
%
pF
DIGITAL OUTPUT (Even Channel and Odd Channel)
Logic family
CMOS
Logic coding
Straight Binary
0.4
Multiplexing frequency
60
MHz
V
VOH
Logic high, IOH = –2 mA
Logic low, IOL = 2 mA
2.5
Output voltage
VOL
V
ANALOG INPUT (CCDIN)
Input level for full-scale output
Allowable feed-through level
Input capacitance
DPGA gain = 0 dB
1400
–0.3
mV
V
1.0
15
pF
V
Input limit
3.6
TRANSFER CHARACTERISTICS
CDS mode = 0 dB, DPGA gain = 0 dB
SH mode, DPGA gain = 0 dB
CDS mode = 0 dB, DPGA gain = 0 dB
SH mode, DPGA gain = 0 dB
DPGA gain = 0 dB
±0.5
±1
±1
±4
LSB
LSB
LSB
LSB
Differential nonlinearity (DNL)
Integral nonlinearity (INL)
±0.5
±2
±4
No missing codes
Ensured
Step input settling time
Overload recovery time
Full-scale step input
1
2
Pixel
Step input from 2.0 V to 0 V
Pixels
9
Data latency
Clocks
(fixed)
DPGA gain = 0 dB
78
54
dB
dB
%
Signal-to-noise ratio(1)
DPGA gain = +24 dB
Channel mismatch
±3
CORRELATED DOUBLE SAMPLER (CDS)
Reference level sample settling time
Data level sample settling time
Within 1 LSB, driver impedance = 50 Ω
Within 1 LSB, driver impedance = 50 Ω
8.3
83
ns
ns
(1) SNR = 20 log (16384/output rms noise in LSB), input connected to ground through capacitor.
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ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, unless otherwise noted.
VSP5010PM
PARAMETER
INPUT CLAMP
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Clamp-on resistance
Clamp level
400
1.5
Ω
V
OB CLAMP LOOP
CCD offset correction range
DAC resolution
–300
300
mV
Bits
µA
10
±0.15
±153
40.7
Minimum DAC output current
Maximum DAC output current
Loop time constant
Slew rate
COB pin
COB pin
µA
CCOB = 0.1 µF
µs
CCOB = 0.1 µF, at current DAC full-scale output
Program range
1530
V/s
LSB
LSB
0
510
Optical black clamp level
OB clamp code = 0101 0000b
160
REFERENCE
Positive reference voltage
Negative reference voltage
DIGITAL PROGRAMMABLE AMPLIFIER (DPGA)
Gain program resolution
1.85
1.1
V
V
10
16
8
Bits
V/V
V/V
V/V
V/V
dB
Gain code = 11 1111 1111b
Gain code = 10 0000 0000b
Gain code = 00 0100 0000b
Gain code = 00 0000 0000b
24 dB
18 dB
0 dB
—
Gain
1
0
Gain error
±0.5
SERIAL INTERFACE
Chip address = 2 bits, register address = 4 bits,
and data = 10 bits
Data length
2
Bytes
MHz
Serial clock frequency
10
POWER SUPPLY
Supply voltage
VCC, VDD
3.0
3.3
290
20
3.6
V
VCC = VDD = 3.3 V, fSYSCLK = 30 MHz,
load = 10 pF
mW
mW
Power dissipation
Standby mode
TEMPERATURE RANGE
Operation temperature
Storage temperature
Thermal resistance
–25
–55
+85
°C
°C
+125
θJA
LQFP-64 package
83
°C/W
4
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PIN CONFIGURATION
VSP5010PM
LQFP-64
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
B0 (LSB)
B1
48 BYP_EV
47 CCDIN_EV
46 AGND
3
B2
4
B3
45 VCC
5
B4
44 REFN_EV
43 CM_EV
42 REFP_EV
41 AGND
6
B5
7
CLPOB
SYSCLK
SHD
SHP
B6
8
9
40 VCC
10
11
12
13
14
15
16
39 REFP_OD
38 CM_OD
37 REFN_OD
36 VCC
B7
B8
B9
35 AGND
B10
34 CCDIN_OD
33 BYP_OD
B11 (MSB)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
1
TYPE(1)
DO
DO
DO
DO
DO
DO
DI
DESCRIPTION
B0 (LSB)
B1
ADC output, bit 0 (least significant bit)
ADC output, bit 1
2
B2
3
ADC output, bit 2
B3
4
ADC output, bit 3
B4
5
ADC output, bit 4
B5
6
ADC output, bit 5
CLPOB
SYSCLK
SHD
SHP
B6
7
Optical black clamp pulse
System clock input
8
DI
9
DI
CCD data sampling pulse
CCD reference sampling pulse
ADC output, bit 6
10
11
12
13
14
15
16
17
DI
DO
DO
DO
DO
DO
DO
P
B7
ADC output, bit 7
B8
ADC output, bit 8
B9
ADC output, bit 9
B10
ADC output, bit 10
B11 (MSB)
DGND
ADC output, bit 11 (most significant bit)
Digital ground for digital outputs (B0–B11)
(1) Designators in TYPE: P = power supply and ground; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
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Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
VDD
NO.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TYPE(1)
P
DESCRIPTION
Digital supply for digital outputs (B0–B11)
Analog ground
AGND
P
VCC
DI
DI
DI
DI
DI
DO
P
Analog power supply
AGND
Analog ground
SDI
Serial interface data input
SCLK
Serial interface data shift clock (rising edge trigger)
Serial interface data write pulse (rising edge trigger)
Serial interface register read output
WRT
RDO
AGND
Analog ground
AGND
P
Analog ground
VCC
P
Analog power supply
COB_OD
BYPR_OD
BYPP_OD
BYPM_OD
BYP_OD
CCDIN_OD
AGND
AO
AO
AO
AO
AO
AI
OB loop output voltage (odd); connect 0.1-µF capacitor between ground
Input buffer reference bypass (odd)
CDS positive reference bypass (odd); open or bypass to ground by a 0.1-µF capacitor
CDS negative reference bypass (odd); open or bypass to ground by a 0.1-µF capacitor
CDS common reference bypass (odd); bypass to ground by a 0.1-µF capacitor
CCD signal input (odd)
P
Analog ground
VCC
P
Analog supply
REFN_OD
CM_OD
REFP_OD
VCC
AO
AO
AO
P
ADC negative reference bypass (odd); bypass to ground by a 0.1-µF capacitor
ADC common reference (odd); bypass to ground by a 0.1-µF capacitor
ADC positive reference (odd); bypass to ground by a 0.1-µF capacitor
Analog power supply
AGND
P
Analog ground
REFP_EV
CM_EV
REFN_EV
VCC
AO
AO
AO
P
ADC positive reference bypass (even); bypass to ground by a 0.1-µF capacitor
ADC common reference bypass (even); bypass to ground by a 0.1-µF capacitor
ADC negative reference bypass (even); bypass to ground by a 0.1-µF capacitor
Analog power supply
AGND
P
Analog ground
CCDIN_EV
BYP_EV
BYPM_EV
BYPP_EV
BYPR_EV
COB_EV
VCC
AI
CCD signal input (even)
AO
AO
AO
AO
AO
P
CDS common reference bypass (even); bypass to ground by a 0.1-µF capacitor
CDS negative reference bypass (even); bypass to ground by a 0.1-µF capacitor
CDS positive reference bypass (even); bypass to ground by a 0.1-µF capacitor
Input buffer reference bypass (even); bypass to ground by a 0.1-µF capacitor
OB loop output voltage (even); connect 0.1-µF capacitor between ground
Analog power supply
AGND
P
Analog ground
AGND
P
Analog ground
CDS/SH_SEL
CA1
DI
DI
DI
DI
DI
DI
P
CDS/SH mode select; high = CDS mode, low = SH mode
Chip address 1
CA0
Chip address 0
INPUTCLP
RESET
OUTENB
AGND
Input clamp control (active low)
Asynchronous register reset (active low)
Output enable/disable; high = high impedance, low = output enable
Analog ground
VCC
P
Analog power supply
DGND
P
Digital ground for digital outputs (B0–B11)
6
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FUNCTIONAL BLOCK DIAGRAM
SCLK SDI RDO WRT
BYPP_E
COB_E
BYPM_E BYP_E REFP_E
CM_E
REFN_E
CA0
CA1
Serial
Interface
EVEN Channel
Internal Reference
RESET
Current
DAC
Buffer
Decoder
CCD Out
Signal
Clamp
Output
Register
14-Bit
ADC
Digital
PGA
CDS/SH
CCDIN_EV
OUTENB
CDS/SH SEL
CLPOB
INPUTCLP
SHP
12-Bit
Digital Output
Output
Control
Timing/Control
SHD
SYSCLK
CCDIN_OD
Output
Register
Digital
PGA
14-Bit
ADC
CDS/SH
Clamp
CCD Out
Signal
Current
DAC
Buffer
Decoder
ODD Channel
Internal Reference
BYPP_OD
COB_OD
BYPM_OD BYP_OD
REFP_OD CM_OD
REFN_OD
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N
N + 1
N + 2
CCD
Signal
tCKP
tS
tWP
SHP
(External)
tS
tWD
tPD
tDP
tCKP
SHD
(External)
ADC_Clock
(Internal)
ECH Data
(Internal)
N-8
N-8
N-7
N-7
N-6
OCH Data
(Internal)
N-6
tINHIBIT
tADC
tADC
tCKP
SYSCLK
(External)
MUX Data
(Internal)
N-9(EV)
N-9(OD)
N-8(EV)
N-8(OD)
N-7(EV)
tD1
tD2
MUX Clock
(Internal)
B[11:0]
(External)
N-9(EV)
tOD
N-9(OD)
N-8(EV)
N-8(OD)
Figure 1. VSP5010 CDS Mode Timing Specifications (Even and Odd Channels) 1
TIMING CHARACTERISTICS
SYMBOL
tCKP
tADC
tWP
PARAMETER
Clock period(1)
SYSCLK pulse width(2)
MIN
32
16
6
TYP
MAX
UNIT
ns
ns
SHD pulse width
8.3
8.3
ns
tWD
SHD pulse width
6
ns
tPD
SHP trailing edge to SHD leading edge
SHD trailing edge to SHP leading edge
Sampling delay
8
ns
tDP
8
ns
tS
3.5
ns
tINHIBIT
tD1
Inhibited clock period
10
ns
Internal MUX clock delay 1(3)
Internal MUX clock delay 2(3)
Output delay at data output delay = 0 ns(4)
Output delay at data output delay = 2 ns(4)
Data latency(5)
4
4
ns
tD2
ns
13
ns
tOD
DL
13
ns
(1) Design ensured. A shipment final test is 33 ns.
(2) Design ensured. A shipment final test is 16.7 ns.
(3) See the Serial Interface section.
(4) Load = 25 pF, data output delay = 2 ns indicates that the delay time is set by the Configuration Register of the serial interface. See the
MPX Clock Edge Phase configuration.
(5) Depending on an Internal MUX clock delay and output delay, latency can carry out the decrease of an increase.
8
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CCD
Signal
N
N + 1
N + 2
tWD
tS
tCKP
SHP
(External)
tDS
tADC
tADC
tCKP
SYSCLK
(External)
ECH Data
(Internal)
N-8
N-8
N-7
N-7
N-6
OCH Data
(Internal)
N-6
MUX Data
(Internal)
N-9(OD)
N-9(EV)
N-8(OD)
N-8(EV)
N-7(OD)
tD1
tD2
MUX Clock
(Internal)
B[11:0]
(External)
N-9(OD)
N-9(EV)
N-8(OD)
N-8(EV)
tOD
Figure 2. VSP5010 SH Mode Timing Specifications (Even and Odd Channels) 1
TIMING CHARACTERISTICS
SYMBOL
tCKP
tADC
tWD
PARAMETER
MIN
32
16
6
TYP
MAX
UNIT
ns
Clock period(1)
SYSCLK pulse width(2)
ns
SHD pulse width
8.3
3.5
ns
tS
Sampling delay
ns
tDS
SHD trailing edge to SYSCLK leading edge
Internal MUX clock delay 1(3)
Internal MUX clock delay 2(3)
Output delay at data output delay = 0 ns(4)
Output delay at data output delay = 2 ns(5)
Data latency
–8
+6
ns
tD1
4.5
12.5
13
ns
tD2
ns
ns
tOD
DL
17
ns
9
Clocks
(1) Design ensured. A shipment final test is 33 ns.
(2) Design ensured. A shipment final test is 16.7 ns.
(3) See the Serial Interface section.
(4) Load = 25 pF, data output delay = 0 ns indicates that the delay time is set by the Configuration Register of the serial interface.
(5) Load = 25 pF, data output delay = 2 ns indicates that the delay time is set by the Configuration Register of the serial interface.
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tXH
tXS
WRT
tCKL
tCKH
tCKP
tXW
SCLK
tDH
tDS
MSB
(CA1)
LSB
(D0)
SD
Two Bytes
Figure 3. Serial Interface Timing Specification 1
TIMING CHARACTERISTICS (31-MHz Operation)
SYMBOL
tCKP
tCKH
tCKL
tDS
PARAMETER
Clock period
MIN
100
40
TYP
MAX
UNIT
ns
Clock high pulse width
Clock low pulse width
Data setup time
ns
40
ns
30
ns
tDH
Data hold time
30
ns
tXS
WRTL to SCLK setup time
SCLK to WRT hold time
WRT setup time
15
ns
tXH
15
ns
tXW
15
ns
10
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WRT
tXS
tXS
tXR
tCKL tCKH
tCKH
tXH
tX
1
2
15
16
1
2
9
10
SCLK
tDH
tDA
tCKP
tCKP
MSB
(CA1)
LSB
(D0)
SD
RD
Two Bytes
tRS
tCKH
MSB
(D9)
LSB
(D0)
10 Bits
Figure 4. Serial Interface Timing Specification 2 (Read)
TIMING CHARACTERISTICS
SYMBOL
tCKP
tCKH
tCKL
tDS
PARAMETER
MIN
100
40
TYP
MAX
UNIT
ns
Clock period
Clock high pulse width
Clock low pulse width
Data setup time (write)
Data hold time (write)
WRTL to SCLK setup time
SCLK to WRT hold time
WRT setup time
ns
40
ns
30
ns
tDH
30
ns
tXS
15
ns
tXH
15
ns
tXW
15
ns
tWRW
tRS
Minimum WRT width
Data setup time (reading)
10
ns
30
ns
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APPLICATION INFORMATION
OVERVIEW
The VSP5010 was developed as an analog front-end for charge-coupled device (CCD) line imaging sensor
applications such as copiers, facsimiles, and so forth. The VSP5010 provides two independent EVEN/ODD
channels for processing, with each channel operating at 31 MHz.
Output signals from each EVEN/ODD channel of the CCD image sensor are sampled at the correlated double
sampling (CDS) circuit and then transmitted to a 14-bit, high-precision analog-to-digital converter (ADC). The
ADC output is then amplified by the required gain at a digital programmable gain amplifier (DPGA) and then
rounded to 12-bit data, and output sequentially as EVEN/ODD data that are synchronized with SYSCLK. The
CDS stage can be also used as a sample-and-hold (S/H) step.
Each channel has an optical black level clamp circuit (OB loop) and automatically compensates offsets of the
CCD and CDS/SH during the OB pixel period (CLPOB). The OB level output value can be set at a required value
through the serial interface. DC bias lost in ac coupling is reproduced as an input clamp voltage, which is the
necessary level for internal operation. Input clamp voltage is charged to a capacitor that is connected to CCDIN
during a dummy pixel period (INPUTCLP) by SHP.
Gain setting, operation polarity of each clock, operating mode selection, and so forth are done through the serial
interface by accessing internal registers. Each setting of register values can be reset to its respective default
value by setting RESET to active low.
CORRELATED DOUBLE SAMPLER (CDS) AND SAMPLE/HOLD (S/H) CIRCUIT
The CDS circuit removes low-frequency and/or common-mode noise, such as fluctuations per pixel, from the
CCD image sensor output. Noises longer than one pixel period among the input signals are rejected by a
subtraction operation at the CDS circuit. Figure 5 shows a simplified CDS block diagram.
SHP
C1 = 10 pF
CIN
CCDIN
CCD
OPA
Output
C2 = 10 pF
SHD
INPUTCLP
SHP
VSP5010
VCLAMP
Figure 5. Simplified Block Diagram
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The CDS circuit can be configured as a sample-and-hold (S/H) circuit by the CDS/SH SEL pin. A simplified S/H
circuit block diagram is shown in Figure 6.
In the S/H mode, the input clamp voltage (VCLAMP) is charged by INPUTCLP and the sampling signal (SHD) to
the CIN capacitor. INPUTCLP is activated at the dummy pixel (or OB pixel) of CCD. By these operations, the
dummy pixel (or OB pixel) level voltage is fixed to VCLAMP at the CCDIN terminal.
When sampling for the OB pixel and an effective pixel, the VCLAMP voltage is charged to capacitor C1, and C2
charges the voltage lower than VCLAMP according to the signal voltage from the CCD. As the voltage difference in
C1 and C2 is acquired during the hold period, signals from the CCD are acquired as voltage based on VCLAMP
.
In CDS mode, the signal voltage is received as the voltage difference between the sampled voltage of SHP
(reference level) and SHD (data level); the signal level is not affected even when VCLAMP charges or fluctuates
because of leakage, etc. However, when operated as S/H, the VCLAMP fluctuation is read as an offset error
because the signal is acquired based on VCLAMP. In order to prevent VCLAMP leakage, a buffer is inserted at the
input in S/H mode.
SHD
VCLAMP
C1 = 10 pF
OPA
CIN
CCDIN
CCD
C2 = 10 pF
SHP
Output
INPUTCLP
VSP5010
SHP
VCLAMP
Figure 6. Simplified Sample-and-Hold (S/H) Circuit
INPUT CLAMP (DUMMY PIXEL CLAMP)
Output from the CCD image sensor is ac-coupled with the VSP5010 through a capacitor. The purpose of the
input clamp is to reproduce the dc bias lost by ac coupling, and to supply an optimum dc bias for proper device
operation at the CDS/SH circuit. Refer to Figure 5 and Figure 6 for simplified block diagrams of the input clamp
circuit.
The input signal level is clamped to the internal reference voltage by activating both SHP (during CDS mode;
activate SHD during SH mode) and INPUTCLP during the CCD dummy pixel output period.
HIGH PRECISION A/D CAPACITOR
The ADC block of the VSP5010 consists of a pipeline architecture. This converter has a complete differential
circuit configuration and error correction circuit, and ensures 14-bit resolution.
Circuits that generate the necessary reference voltage at the ADC are built inside the device, and are shown as
REFP (high-potential reference), REFN (low-potential reference), and CM (common-mode voltage) pins outside
the device. In order to assure ADC accuracy, these reference voltage pins must be sufficiently decoupled by a
capacitor (0.1 µF recommended).
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DIGITAL PROGRAMMABLE GAIN AMPLIFIER (DPGA)
The DPGA circuit can control gain values in the range of 0 V/V to 16 V/V by inputting a digital code through the
serial interface. Gain changes linearly in proportion to the code setting, as shown in Figure 7.
18
16
14
12
10
8
6
4
2
0
0
1024
128
256
384
512
640
768
896
Input Gain Control
Figure 7. Block Diagram of CDS and Input Clamp
OPTICAL BLACK LEVEL (OB) LOOP AND OB CLAMP LEVEL
The VSP5010 has a built-in self-calibration circuit (OB loop) that compensates the OB level by using optical black
(OB) pixels output from the CCD image sensor. A block diagram of the OB loop and OB clamp circuit is shown in
Figure 8.
OB Clamp
Level
CDS/SH
CCDIN
DATA
OUT
DPGA
ADC
BYPP2
Current
DAC
Decoder
COB
CPLOB
Figure 8. OB Loop and OB Level Clamp
The CCD offset is compensated by converging this calibration circuit while activating CLPOB during a period
when OB pixels are output from the CCD.
In CDS mode, CCD offset is compensated as a difference between the reference level and the data level of the
OB pixel. In SH mode, VCLAMP is compensated by INPUTCLP as the difference between fixed dummy pixels and
the OB pixels.
These compensated signal levels are recognized as actual OB levels, and outputs are clamped to OB levels set
by the serial interface. These OB levels are the base of black for the effective pixel period thereafter.
The DPGA is a gain stage outside the OB loop; therefore, OB levels are not affected even when the gain
changes.
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The converging time of the OB loop is determined based on the capacitor value connected to the COB terminal
and the output from the current output digital-to-analog converter (DAC) of the loop. The time constant (T) can be
obtained from Equation 1:
T = C/(16384 ´ IMIN
)
(1)
Where:
•
•
C is the capacitor value connected to COB,
IMIN is the minimum current (0.15 µA) of the current DAC, which has a current equivalent to 1 LSB of the
DAC converter output.
When C = 0.1 µF, T is 40.7 µs.
The slew rate (SR) can be obtained from Equation 2:
SR = IMAX/C
(2)
Where:
•
•
C is the capacitor value connected to COB,
IMAX is the maximum current (153 µA) of the current DAC, which is the equivalent current to 1023 LSB of
the DAC converter output.
The OB clamp level (digital output value) can be set externally through the serial interface by inputting a digital
code to the OB clamp level register. The digital code to be input and the corresponding OB clamp level are
shown in Table 2.
Table 2. Input Code and OB Clamp Level to be Set
CLAMP LEVEL (LSB)
CODE
0000 0000b
0000 0001b
—
VSP5010 (12-BIT)
0
2
—
0100 1111b
0101 0000 (default)
0101 0001b
—
158
160
162
—
1011 1111b
1111 1111b
508
510
SETTLING OF OB LOOP AND INPUT CLAMP
Because these capacitors are discharged at start-up and after a long standby state, these two capacitors must
be charged to the proper operational voltage.
The charging time for the input clamp voltage is the logical AND of SHP (SHD in S/H mode) and INPUTCLP. The
actual charging time per line is the duration of the SHP pulse times the number of dummy pixels in the line.
Equally, COB is only charged during the OB pixel period. Therefore, some time is necessary to bring the
VSP5010 into a normal operating state at device start-up.
Though start-up time depends on the number of dummy and pixels per line, at least 500 ms to 1 s should be
allowed.
STANDBY MODE
Normal operation mode and standby mode can be switched by the serial interface.
In standby mode, power consumption can be saved; all operation is suspended other than the interface circuit
and reference voltage supply. During standby mode, additional power consumption may be obtained by
suspending SYSCLK. When restoring a SYSCLK that was suspended during standby mode, more than two
clocks of SYSCLK must be acquired before inputting commands.
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OUTPUT DATA DELAY
Large transient noise occurs when the output data change because several logic lines change simultaneously.
When this transient noise timing overlaps the analog signal sampling timing, it may affect the ADC converting
value. To avoid this effect, changing the timing of the VSP5010 output data can be delayed in approximately 3-ns
steps by serial control.
The delay value set refers to the increase in default time between SYSCLKL and the data output set in the timing
specification.
TEST MODE AND TEST PATTERN
The VSP5010 can be set to test mode by setting the configuration register. During test mode, the test pattern
generated inside will be output with or without a CCD input signal.
There are two test patterns. One is a pattern which outputs the code that is the OB level +128 LSB for a
specified number of pixels (stripe pattern); the other is a pattern which increments the output code from 1 to 4095
by a specified number of LSBs per pixel (gradation pattern). These patterns can be selected by setting the
configuration register through the serial interface.
CHIP ADDRESS
The VSP5010 has two chip address pins, CA0 and CA1. Setting these pins gives a particular address for the
device, and the data-writing device can be selected by the address in serial interface data. By this function, the
serial interface can be used as a common line for up to four devices.
REGISTER READING
Each register data can be read from the RDO pin by setting bit A3 of the serial interface data to '1', and setting
the reading register address to A[2:0].
After writing the address to specify which register is to be read, assert WRT and apply SCLK. The value of the
register is output sequentially on the RD pin. Refer to the Serial Interface Timing Specification 2 (Read) for
details.
While reading registers, the writing function is disabled.
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SERIAL INTERFACE REGISTER DESCRIPTION
The serial interface of the VSP5010 is composed of three signals; SDI, SCLK, and WRT. SDI data are
sequentially stored to the shift register at the rising edge of SCLK, and shift register data are stored to the
parallel latch at the rising edge of WRT.
Serial data are two bytes of fixed length and are composed of a two-bit chip address, a four-bit register address,
and 10-bit data. The chip address can only write register to a device that matches its value to the address set by
CA0 and CA1. By using this two-bit chip address, the serial interface can be shared by other devices.
Both the address (A[3:0]) and the serial data (D[9:0]) start with the MSB (A3, D9) and end with the LSB (A0, D0).
When data with more than two bytes are applied, the final two bytes immediately before the rising edge of WRT
are effective, and any data writtenbefore that are lost.
Register configuration and serial data format are shown in Table 3.
Each register value is defined at the time of device power-on (VCC = 2.1 V (typ)).
Table 3. Serial Interface Command Data Format
MSB
LSB
D0
REGISTERS
CA1 CA0
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
Configuration
X(1)
X
0
0
0
0
0
0
C7
C6
0
C4
0
C2
C1
C0
Standby mode and
Clk Dly
X
X
0
0
0
1
D9
D8
D7
D6
D5
D4
D3
D2
0
S0
DPGA gain EVEN
DPGA gain ODD
X
X
X
X
0
0
0
0
1
1
0
1
G9
G9
G8
G8
G7
G7
G6
G6
G5
G5
G4
G4
G3
G3
G2
G2
G1
G1
G0
G0
OB clamp level
EVEN
X
X
0
1
0
0
0
0
O7
O6
O5
O4
O3
O2
O1
O0
OB clamp level
ODD
X
X
X
X
X
X
X
X
0
0
0
1
1
1
0
1
1
0
0
0
0
X
0
0
0
X
O7
0
O6
0
O5
T5
0
O4
T4
0
O3
0
O2
T2
0
O1
0
O0
T0
0
Test mode
Internal ADCK
monitor
1
1
1
0
0
0
PT1
X
Read out
R2
R1
R0
X
X
X
X
X
X
X
Configuration Register Description (Address = 000h)
Bits C[2:0] Clock Polarity
Bit C0 (INPUTCLP Polarity)
Bit C1 (CLPOB Polarity)
Bit C2 (SHP/SHD Polarity)
0 = Active low (default)
1 = Active high
0 = Active low (default)
1 = Active high
0 = Active low (default)
1 = Active high
Bit C4 Data Output Order
0 = EVEN/ODD (default)
1 = ODD/EVEN
Bits C[7:6] Data Output Delay
Bit C7
Bit C6
0 = Time (0 ns, typ) (default)
0 = Delay time (2 ns, typ)
1 = Delay time (4 ns, typ)
1 = Delay time (6 ns, typ)
0 Delay = time (0 ns, typ) (default)
1 = Delay time (2 ns, typ)
0 = Delay time (4 ns, typ)
1 = Delay time (6 ns, typ)
(1) X = Don't care.
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Standby Mode and MPX Clock Edge Phase Description (Address = 01h)
Bit S0 Standby/Normal Operation Select
0 = Normal operation mode (default)
1 = Standby mode
Bits D[8:1] MPX Clock Edge Phase
Figure 9 illustrates the MPX clock edge phase.
Bits D[5:2] Dlyedge 2 Timing (except constant delay tD1
)
0000b = Delay time (1.6 ns)
1000b = Delay time (8.0 ns) (default, 0.8 ns/step)
1111b = Delay time (13.6 ns)
Bits D[9:6] Dlyedge 1 Timing (except constant delay tD1
)
0000b = Delay time (–2.4 ns)
1000b = Delay time (0 ns) (default, 0.3 ns/step)
1111b = Delay time (2.1 ns)
SysClock (30 MHz)
tD
OutClock (60 MHz)
DlyEdge1
DlyEdge2
Figure 9. MPX Clock Edge Phase
CAUTION:
Please do not use at Delayedge 1 > Delayedge 2
(example: D[5:2] = 0000b and D[9:6] = 1111b)
Delayedge2 should maintain sufficient width to allow proper data output timing.
Internal ADCK Monitor Description (Address = 07h)
Bit D1 PT1
0 = Normal
1 = Internal ADC clock to B0 (ADC output, bit 0, least significant bit)
EVEN Channel Gain Register Description (Address = 02h)
Bits G[9:0] Gain Value
GAIN[9:0] /64 (default = 00 0100 0000b)
ODD Channel Gain Register Description (Address = 03h)
Bits G[9:0] Gain Value
GAIN[9:0] /64 (default = 00 0100 0000b)
EVEN Channel OB Clamp Register Description (Address = 04h)
Bits O[7:0] OB Clamp Level
2 LSB × O[7:0] (default = 0101 0000b)
ODD Channel OB Clamp Register Description (Address = 05h)
Bits O[7:0] OB Clamp Level
2 LSB × O[7:0] (default = 0101 0000b)
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Test Mode Register Description (Address = 06h)
Bit T0 Test Mode Enable/Disable
0 = Disable (default)
1 = Enable
Bit T2 Test Pattern Select
0 = Gradation pattern (default)
1 = Stripe pattern
Bits T[5:4] Test Pattern Data Interval
Bit T5
Bit T4
0 = Stripe pattern (8 pixels), gradation
pattern (2 pixels) (default)
0 = Stripe pattern (8 pixels), gradation pattern (2 pixels) (default)
0 = Stripe pattern (16 pixels),
gradation pattern (4 pixels)
1 = Stripe pattern (16 pixels), gradation pattern (4 pixels)
0 = Stripe pattern (32 pixels), gradation pattern (8 pixels)
1 = Stripe pattern (64 pixels), gradation pattern (16 pixels)
1 = Stripe pattern (32 pixels),
gradation pattern (8 pixels)
1 = Stripe pattern (64 pixels),
gradation pattern (16 pixels)
Register Read Out Description
Bit A[2:0] R[2:0]
2:0 = Set reading register address
POWER SUPPLY, GROUNDING AND DEVICE DECOUPLING RECOMMENDATIONS
The VSP5010 incorporates a very high-precision and high-speed ADC and analog circuitry which are vulnerable
to any extraneous noise from the rails or elsewhere. For this reason, although the VSP5010 has analog and
digital supply pins, it should be treated as an analog component; all supply pins except for VDD should be
powered by the analog supply only. This configuration ensures the most consistent results, because digital power
lines often carry high levels of wideband noise that would otherwise be coupled into the device and degrade the
achievable performance.
Proper grounding, short lead length, and the use of ground planes are also very important for high-frequency
designs. Multilayer printed circuit boards (PCBs) are recommended for the best performance; these types of
boards offer distinct advantages such as minimizing ground impedance, separation of signal layers by ground
layers, and so forth. It is highly recommended that analog and digital ground pins of the VSP5010 be joined
together at the IC and be connected only to the analog ground of the system.
The driver stage of the digital outputs (B[11:0]) is supplied through a dedicated supply VDD (pin 18) and it should
be separated from the other supply pins completely or at least with a ferrite bead.
Because of the high operation speed, the converter also generates high-frequency current transients and noise
that are fed back into the supply and reference lines. This additional interference requires the supply and
reference pins be sufficiently bypassed. In most cases, 0.1-µF ceramic chip capacitors are adequate to decouple
the reference pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum
(1-µF to 22-µF) and ceramic (0.1-µF) capacitors. The effectiveness of the decoupling depends largely on the
proximity to the individual pin. VDD should be decoupled to the proximity of DGND (pin 17 and pin 64).
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
VSP5010PM
VSP5010PMG6
VSP5010PMR
VSP5010PMRG6
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
PM
PM
PM
PM
64
64
64
64
160
160
Green (RoHS
& no Sb/Br)
A42 SNBI Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
A42 SNBI Level-1-260C-UNLIM
A42 SNBI Level-1-260C-UNLIM
A42 SNBI Level-1-260C-UNLIM
1000
1000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
VSP5010PMR
LQFP
PM
64
1000
330.0
25.4
12.8
12.8
1.9
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
LQFP PM 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
VSP5010PMR
1000
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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相关型号:
VSP5010PMRG6
12-Bit, 31-MSPS, Dual-Channel CCD ANALOG FRONT-END FOR DIGITAL COPIERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5324-Q1
汽车类 4 通道 12 位 80MSPS 模数转换器 (ADC)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5324TRGCRQ1
汽车类 4 通道 12 位 80MSPS 模数转换器 (ADC) | RGC | 64 | -40 to 105Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5610
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing GeneratorWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5610RSHR
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing GeneratorWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5611
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing GeneratorWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5611RSHR
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing GeneratorWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5612
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing GeneratorWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5612RSHR
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with Timing GeneratorWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5620
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with LED DriverWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5620RSLR
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with LED DriverWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
VSP5621
16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End with LED DriverWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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