T6LA0B [TOSHIBA]
IC LIQUID CRYSTAL DISPLAY DRIVER, UUC281, TCP-281, Display Driver;
| 型号： | T6LA0B |
| 厂家： | 
TOSHIBA |
| 描述： | IC LIQUID CRYSTAL DISPLAY DRIVER, UUC281, TCP-281, Display Driver 驱动 CD 输出元件 接口集成电路 |
| 文件： | 总13页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T6LA0B
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6LA0B
Gate Driver for TFT LCD Panels
The T6LA0B is a 263 / 256 / 240 / 200-channel output gate
driver for TFT LCD panels.
Unit: mm
User Area Pitch
IN OUT
Features
T6LA0B
•
•
•
•
•
LCD drive output pins : Switchable 263 / 256 / 240 / 200 pins
LCD drive voltage : max 40.0 V
Please contact Toshiba or a distributor for
the latest TCP specification and product
line-up.
Data transfer method : Bidirectional shift register
Operating temperature : −20 to 75°C
Package
: TCP / COF
TCP (Tape Carrier Package)
Application
•
Module for PCs / TV monitors
1
2005-07-14
T6LA0B
Block Diagram
DO/I
DI/O
CPV
Shift register
U/D
MODE1
MODE2
Input circuit unit
OE1
OE2
Control circuit unit
OE3
XDON
V
GG
Output circuit unit
V
EE
V
DD
V
SS
G1 G2 G3
G261 G262 G263
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2005-07-14
T6LA0B
Pin Assignment
G263 281
G262 280
G261 279
1
2
V
V
GG
DD
3
4
5
6
DO/I
OE3
OE2
OE1
CPV
7
8
9
(V
)
SS
U/D
(V
T6LA0B
(chip top view)
10
11
12
13
14
15
16
17
18
)
DD
MODE2
(V
)
SS
MODE1
(V
)
DD
XDON
DI/O
V
V
SS
EE
G3 21
G2 20
G1 19
The above diagram shows the device’s pin configuration only and does not necessarily correspond to the pad
layout on the chip. Please contact Toshiba or our distributors for the latest TCP / COF specification.
3
2005-07-14
T6LA0B
Pin Function
Pin Name
I/O
Function
Vertical shift data I/O pins
These pins are used to input and output shift data. These pins are switched between input and
output by setting the U/D pin as shown below.
U/D
H
DI/O
Input
DO/I
Output
Input
DI/O
DO/I
I/O
L
Output
When set for input
This pin is used to feed data into the shift registers at the first stage of the LCD driver. The data
is latched into the shift registers at the rising edge of CPV.
When set for output
When two or more T6LA0Bs are cascaded, this pin outputs the data to be fed into the next
stage. This data changes state synchronously with the falling edge of CPV.
Transfer direction select pin
This pin specifies the direction in which data is transferred through the shift registers.
The shift register data is shifted synchronously with each rising edge of CPV as follows:
When U/D is high, data is shifted in the direction
U/D
I
U/D = “H”: G1 → G2 → G3 → G4 → ··· → G263
When U / D is low, the direction is reversed to give
U/D = “L”: G263 → G262 → G261 → G260 → ··· → G1
The voltage applied to this pin must be a DC-level voltage that is either high (V ) or low (V ).
DD
SS
Vertical shift clock
CPV
I
I
This is the shift clock for the shift registers. Data is shifted through the shift registers
synchronously with the rising edge of CPV.
Output enable pins
These signals control the data appearing at the LCD panel drive pins (G1 through G263).
OE1 to OE3 doesn’t synchronize with the CPU.
OE1 to OE3
The V voltage is output when OE1 to OE3 is high; normal shift data is output
EE
when OE1 to OE3 is low.
Output channels select pin
This signal selects 263 / 256 / 240 / 200-pin mode for the LCD panel driver.
MODE1
MODE2
LCD drive output pins
H
H
L
H
L
263
256
240
200
MODE1
MODE2
I
H
L
L
The voltage applied to this pin must be a DC-level voltage that is either high (V ) or low (V ).
DD SS
Display-ON input pin
When XDON = low, the V
voltage is output to all output pins irrespective of the shift data
GG
and the content of input data. However, this does not cause the contents of the shift registers to
be cleared. DON operates asynchronously with CPV. If XDON and OE are asserted
simultaneously, DON is given priority over OE . This pin is pulled up on the T6LA0B.
XDON
I
Since all LCD drive outputs output the V
momentarily.
level, a large current may generate them
GG
When 256 / 240 / 200-pin mode, unapplied LCD panel drive pins fixed V
.
EE
LCD panel drive pins
These pins output the shift register data or the voltage applied to V
control signals OE1 to OE3 and XDON. When 256 / 240 / 200-pin mode, unapplied LCD
or V depending on the
EE
GG
G1 to G263
O
panel drive pins fixed V without regard to these control signals.
EE
V
⎯
⎯
Power supply for LCD drive
Power supply for LCD drive
Power supply for the internal logic
GG
V
EE
V
⎯
⎯
DD
The (V ) is the pin for connection.
DD
Power supply for the internal logic
V
SS
The (V ) is the pin for connection.
SS
4
2005-07-14
T6LA0B
Device Operation
(1) Shift data transfer method
Shift Data
Input
Output
Mode
MODE1
MODE2
U/D Pin
Data Transfer Method
Output
DO/I
DI/O
DO/I
DI/O
DO/I
DI/O
DO/I
DI/O
H
L
DI/O
DO/I
DI/O
DO/I
DI/O
DO/I
DI/O
DO/I
G1 → G2 → G3 → G4 → ··· → G263
G263 → G262 → G261 → ··· → G1
H
H
L
H
L
263-out
H
L
G1 → G2 → G3 → G4 → ··· → G128→ G136 → ··· → G263
G263 → G262 → G261 → ···→ G136 → G128 → ··· → G1
G1 → G2 → G3 → G4 → ··· → G120→ G144 → ··· → G263
G263 → G262 → G261 → ···→ G144 → G120 → ··· → G1
G1 → G2 → G3 → G4 → ··· → G100→ G164 → ··· → G263
G263 → G262 → G261 → ···→ G164 → G100 → ··· → G1
256-out
240-out
200-out
H
L
H
L
H
L
L
The input data (DI/O or DO/I) is latched into the internal register synchronously with the rising edge of the
shift clock CPV. At the same time that the data is shifted to the next register at the next rise of CPV, new
vertical shift data is latched into.
In the output operation, the data in the last shift register (G263 or G1) is output synchronously with the
falling edge of CPV. (The output high voltage is the V
level; the output low voltage is the V level.)
SS
DD
5
2005-07-14
T6LA0B
(2) LCD panel drive outputs
The LCD panel drive outputs are controlled by OE1 to OE3 as shown below.
LCD Panel Drive Outputs
LCD Panel Drive Pins Controller by OE1 to OE3
Output Mode
Output Enable Pin
Output
OE1 = “H”
OE2 = “H”
OE3 = “H”
OE1 = “L”
OE2 = “L”
OE3 = “L”
OE1 = “H”
OE2 = “H”
OE3 = “H”
OE1 = “L”
OE2 = “L”
OE3 = “L”
OE1 = “H”
OE2 = “H”
OE3 = “H”
OE1 = “L”
OE2 = “L”
OE3 = “L”
OE1 = “H”
OE2 = “H”
OE3 = “H”
OE1 = “L”
OE2 = “L”
OE3 = “L”
G1, G4, G7, ···, G127, G130, ···, G256, G259, G262
V
G2, G5, G8, ···, G128, G131, ···, G257, G260, G263
G3, G6, G9, ···, G129, G132, ···, G258, G261
G1, G4, G7, ···, G127, G130, ···, G256, G259, G262
G2, G5, G8, ···, G128, G131, ···, G257, G260, G263
G3, G6, G9, ···, G129, G132, ···, G258, G261
G1, G4, G7, ···, G127, G137, ···, G257, G260, G263
G2, G5, G8, ···, G128, G138, ···, G258, G261
G3, G6, G9, ···, G136, G139, ···, G259, G262
G1, G4, G7, ···, G127, G137, ···, G257, G260, G263
G2, G5, G8, ···, G128, G138, ···, G258, G261
G3, G6, G9, ···, G136, G139, ···, G259, G262
G1, G4, G7, ···, G118, G144, ···, G255, G258, G261
G2, G5, G8, ···, G119, G145, ···, G256, G259, G262
G3, G6, G9, ···, G120, G146, ···, G257, G260, G263
G1, G4, G7, ···, G118, G144, ···, G255, G258, G261
G2, G5, G8, ···, G119, G145, ···, G256, G259, G262
G3, G6, G9, ···, G120, G146, ···, G257, G260, G263
G1, G4, G7, ···, G97, G100, ···, G256, G259, G262
G2, G5, G8, ···, G98, G164, ···, G257, G260, G263
G3, G6, G9, ···, G99, G165, ···, G258, G261
EE
263-out
Normal data output
V
EE
256-out
240-out
200-out
Normal data output
V
EE
Normal data output
V
EE
G1, G4, G7, ···, G97, G100, ···, G256, G259, G262
G2, G5, G8, ···, G98, G164, ···, G257, G260, G263
G3, G6, G9, ···, G99, G165, ···, G258, G261
Normal data output
6
2005-07-14
T6LA0B
Timing Diagram 1
( 263-out mode, U/D = High level, MODE1 = High level, MODE2 = High level )
DI/O
(Input)
1
2
3
4
5
263
264
CPV
OE1
OE2
OE3
XDON
G1
G2
G3
G4
G263
DO/I
(Output)
: This part is output which is controlled (fixed to V ) by
pin.
OE
EE
Timing Diagram 2
( 263-out mode, U/D = Low level, MODE1 = High level, MODE2 = High level )
DO/I
(Input)
1
2
3
4
5
263
264
CPV
OE1
OE2
OE3
High level
XDON
G263
G262
G261
G260
G1
DI/O
(Output)
: This part is output which is controlled (fixed to V ) by
EE
pin.
OE
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2005-07-14
T6LA0B
Timing Diagram 3
( 256-out mode, U/D = High level, MODE1 = High level, MODE2 = Low level, XDON = High level )
DI/O
(Input)
1
2
3
4
5
256
257
CPV
OE1
OE2
OE3
G1
G2
G3
G4
G129 to G135
G263
V
EE
DO/I
(Output)
: This part is output which is controlled (fixed to V ) by
pin.
OE
EE
Timing Diagram 4
( 240-out mode, U/D = High level, MODE1 = Low level, MODE2 = High level, XDON = High level )
DI/O
(Input)
1
2
3
4
5
240
241
CPV
OE1
OE2
OE3
G1
G2
G3
G4
G121 to G143
G263
V
EE
DO/I
(Output)
: This part is output which is controlled (fixed to V ) by
EE
pin.
OE
8
2005-07-14
T6LA0B
Timing Diagram 5
( 200-out mode, U/D = High level, MODE1 = Low level, MODE2 = Low level, XDON = High level )
DI/O
(Input)
1
2
3
4
5
200
201
CPV
OE1
OE2
OE3
G1
G2
G3
G4
G101 to G163
G263
V
EE
DO/I
(Output)
: This part is output which is controlled (fixed to V ) by
EE
pin.
OE
9
2005-07-14
T6LA0B
Absolute Maximum Ratings (V = 0 V)
SS
Parameter
Supply voltage (1)
Symbol
Rating
Unit
V
V
−0.3 to 4.0
−0.3 to 42.0
−20.0 to 0.3
−0.3 to 42.0
DD
Supply voltage (2)
Supply voltage (3)
Supply voltage (4)
V
GG
V
EE
V
− V
GG
EE
Input voltage
V
−0.3 to V
+ 0.3
V
IN
DD
Storage temperature
T
stg
−55 to 125
°C
Recommended Operating Conditions (V = 0 V)
SS
Parameter
Supply voltage (1)
Symbol
Rating
Unit
V
V
2.7 to 3.6
10 to 35
DD
Supply voltage (2)
V
GG
Supply voltage (3)
V
−21 to −5
15.0 to 40.0
−20 to 75
DC to 500
1000 (max)
EE
Supply voltage (4)
V
− V
GG
EE
Operating temperature
Operating frequency
Output Load capacitance
T
opr
°C
kHz
f
CPV
C
L
pF/PIN
Electrical Characteristics
DC Characteristics
(V
− V = 26.0 to 40.0 V, V = 2.7 to 3.6 V, V = 0 V, Ta = −20 to 75°C)
DD
GG
EE
SS
Test
circuit
Parameter
Symbol
Test Conditions
Min
Max
Unit
V
Relevant
(Note1)
0.3 ×
Low Level
High Level
Low Level
High Level
V
⎯
⎯
V
IL
IH
SS
V
DD
Input voltage
⎯
0.7 ×
V
V
DD
V
DD
V
SS
0.4
+
V
I
I
= 40 µA
V
SS
OL
OH
OL
DI/O,
DO/I
Output voltage
⎯
⎯
V
V
−
DD
0.4
V
= −40 µA
V
DD
OH
Low Level
High Level
R
V
V
= V + 0.5 V
EE
OL
OH
ION
OUT
OUT
Output
resistance
G1 to
G263
⎯
500
Ω
R
= V
− 0.5 V
⎯
GG
Pull-down resistance
Input leakage current
R
⎯
⎯
⎯
150
1
kΩ
µA
XDON
I
⎯
−1
(Note1)
IN
OE1 to OE3 = Low level
Current consumption (1)
Current consumption (2)
Current consumption (3)
I
⎯
⎯
⎯
50
50
50
V
GG
GG
non-load
(Note2)
OE1 to OE3 = Low level
I
⎯
µA
V
DD
DD
(Note2)
OE1 to OE3 = Low level
non-load (Note2)
I
V
EE
EE
Note1 :These input pins include DI/O, DO/I, CPV, OE1 to OE3
Note2 :fCPV = 50kHz, Shift data input : 60Hz, OE1 to OE3 = "L", XDON = "H", MODE1 / MODE2 = "H"
10
2005-07-14
T6LA0B
AC Characteristics
(V − V = 26.0 to 40.0 V, V = 2.7 to 3.6 V, V = 0 V, Ta = −20 to 75°C)
GG
EE
DD
SS
Test
circuit
Parameter
Symbol
Test Conditions
Min
Max
Unit
Clock frequency
t
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
500
500
200
200
800
100
⎯
500
⎯
kHz
ns
ns
ns
ns
ns
µs
CPV
CPV pulse width (H)
CPV pulse width (L)
Data set-up time
t
CPVH
t
⎯
CPVL
t
t
⎯
sDI
Data hold time
⎯
hDI
OE enable time
t
⎯
wOE
wON
Display-ON pulse width
Output delay time (1)
Output delay time (2)
Output delay time (3)
Output delay time (4)
t
C
C
C
C
C
= 300 pF
⎯
L
L
L
L
L
t
= 50 pF
100
800
800
10
pdDO
ns
t
= 300 pF
= 300 pF
= 300 pF
⎯
pdG
t
t
⎯
pdOE
pdON
⎯
µs
t
t
CPVL
CPVH
CPV
50%
50%
50%
50%
50%
t
t
hDI
sDI
DI/O, DO/I
(Input)
50%
50%
t
t
t
pdG
pdG
V
V
GG
EE
G1
50%
50%
t
pdG
pdG
V
V
GG
EE
G2 to G262
50%
50%
CPV
50%
50%
V
V
GG
EE
G263
t
t
pdDO
pdDO
DO/I, DI/O
(Output)
50%
50%
t
wOE
50%
50%
OE1 to OE3
G1 to G263
t
t
pdOE
pdOE
V
V
GG
EE
50%
50%
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2005-07-14
T6LA0B
t
wON
XDON
50%
50%
t
t
pdON
pdON
V
V
GG
EE
G1 to G263
50%
50%
Power Supply Sequence
Turn power on in the order V
DD
→ V
→ Input signal → V . Turn power off in th reverse order.
EE
GG
It may input V
input signal and V
simultaneously.
EE,
GG
V
GG
V
DD
V
SS
V
EE
12
2005-07-14
T6LA0B
13
2005-07-14
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