TCA62746AFNG [TOSHIBA]

16-Output Constant Current LED Driver with Output Open/Short Detection; 16路输出恒流LED驱动器,具有输出开路/短路检测
TCA62746AFNG
型号: TCA62746AFNG
厂家: TOSHIBA    TOSHIBA
描述:

16-Output Constant Current LED Driver with Output Open/Short Detection
16路输出恒流LED驱动器,具有输出开路/短路检测

显示驱动器 驱动程序和接口
文件: 总25页 (文件大小:470K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TCA62746AFG/AFNG  
TOSHIBA CMOS Integrated Circuit Silicon Monolithic  
TCA62746AFG,TCA62746AFNG  
16-Output Constant Current LED Driver with Output Open/Short Detection  
The TCA62746 series are LED drivers with sink type constant  
TCA62746AFG  
circuit output, making them ideal for controlling LED modules  
and displays.  
The current value of the 16-output is configurable using one  
external resistor.  
In addition, these drivers are equipped with a function for  
detecting the output voltage when the output load LEDs open or  
short, and which then outputs the result as serial data.  
These drivers consist of a 16-constant current output block, a  
16-bit shift register, a 16-bit latch and a 16-bit AND-gate.  
The suffix (G) appended to the part number represents a Lead  
(Pb)-Free product.  
TCA62746AFNG  
Features  
16-output built-in  
Output open detection (OOD) function  
: When in detection mode, outputs the detection results via  
SOUT.  
Output short detection (OSD) function  
: When in detection mode, outputs the detection results via  
SOUT.  
Weight  
SSOP24-P-300-1.00B : 0.32 g (typ.)  
SSOP24-P-300-0.65A : 0.14 g (typ.)  
Output current setting range  
: 2 to 50 mA × 16-constant current output  
Current accuracy (@ R  
= 1.56 k, V = 1.0 V, V  
= 5.0 V)  
EXT  
O
DD  
: Between outputs: ± 1% (typ.)  
Between devices: ± 3% (typ.)  
Control data format: serial-in, parallel-out  
I/O logic: TTL level (Schmitt trigger input)  
Data transfer frequency: f  
= 25 MHz (max)  
MAX  
Power supply voltage: V  
= 4.5 to 5.5 V  
DD  
Operation temperature range: T  
= −40 to 85°C  
opr  
Constant current output voltage: V = 17V (max)  
O
Output delay circuit built-in: Internal data reset circuit for power-on resetting (POR)  
Backward compatible to TB62706B and TB62726A series drivers  
Package: FG type: SSOP24-P-300-1.00B  
FNG type: SSOP24-P-300-0.65A  
Caution  
This device is sensitive to electrostatic discharge. Please handle with care.  
The terminals which are marginal to electro static discharge are shown in the following table.  
(Please refer to page 22 for details.)  
ESD test MM Model Marginal terminals (MM Model Internal Standard ±200V)  
5,6,7,8,9,10,11,12,13,14,15,16,19,20  
* ESD test HBM Model Internal Standard (±2000V) is OK  
1
2007-05-22  
TCA62746AFG/AFNG  
Pin Assignment (top view)  
As shown below, this series has the same pin assignments as the TB62706B and TB62726A series:  
GND  
SIN  
V
DD  
R
EXT  
SCK  
SOUT  
OE  
SLAT  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
OUT5  
OUT6  
OUT7  
OUT15  
OUT14  
OUT13  
OUT12  
OUT11  
OUT10  
OUT9  
OUT8  
Note1: Short circuiting an output pin to a power supply pin (V  
or V  
), or short-circuiting the R  
pin to the GND  
EXT  
DD  
LED*  
pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. Please keep  
this in mind when determining the wiring layout for the power supply and GND pins.  
*VLED: LED power supply  
2
2007-05-22  
TCA62746AFG/AFNG  
Block Diagram  
OUT0  
OUT1  
OUT15  
OSD  
3.0 V  
OOD  
16  
0.3 V  
16  
OUT0  
OUT1  
Constant current outputs  
OUT15  
V
DD  
B.G  
POR  
Delay1  
Delay15  
GND  
OE  
R
EXT  
OE  
OOD/OSD  
controller  
Q0 Q1  
16-bit D-latch  
D0 D1  
Q15  
D15  
R
G
SLAT  
ST-OUT  
SIN  
D0  
Q0 Q1  
16-bit shift register  
ST D0~D15  
Q15  
Q15  
R
SOUT  
SCK  
S
OSD  
OOD  
16-bit  
MUX  
DO  
16  
3
2007-05-22  
TCA62746AFG/AFNG  
Truth Table  
SCK  
SLAT  
OE  
SIN  
OUT0 OUT7 OUT15 *1  
SOUT  
H
L
L
L
L
L
H
Dn  
Dn Dn 7 Dn 15  
No Change  
Dn 15  
Dn 14  
Dn 13  
Dn 13  
Dn 13  
Dn + 1  
Dn + 2  
Dn + 3  
Dn + 3  
H
Dn + 2 Dn 5 Dn 13  
Dn + 2 Dn 5 Dn 13  
OFF  
- *2  
- *2  
Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the  
respective output will be OFF.  
Note2: “-“ is irrelevant to the truth table.  
Timing Chart  
n = 0  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
H
SCK  
SIN  
L
H
L
H
SLAT  
OE  
L
H
L
ON  
OFF  
ON  
OFF  
ON  
OFF  
OUT0  
OUT1  
OUT2  
ON  
OFF  
H
OUT15  
SOUT  
L
Note 1:  
Note 2:  
The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit.  
Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin is set  
to “H” the latch circuit does not hold data. The data will instead pass onto output.  
When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to the  
data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of the data.  
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2007-05-22  
TCA62746AFG/AFNG  
Pin Functions  
Pin No  
Pin Name  
I/O  
Function  
1
2
GND  
SIN  
The ground pin.  
I
The serial data input pin.  
The serial data transfer clock input pin.  
Also used for OOD/OSD mode settings.  
3
4
SCK  
I
I
The latch signal input pin.  
Data is saved at L level.  
SLAT  
Also used for OOD/OSD mode settings.  
5
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
OUT5  
OUT6  
OUT7  
OUT8  
OUT9  
OUT10  
OUT11  
OUT12  
OUT13  
OUT14  
OUT15  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
A sink type constant current output pin.  
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
The constant current output enable signal input pin.  
During the “H” level, the output will be forced off.  
Also used for OOD/OSD mode settings.  
21  
22  
OE  
I
The serial data output pin.  
This pin outputs the OD/OSD detection result data.  
SOUT  
O
23  
24  
R
The constant current value setting resistor connection pin.  
The power supply input pin.  
EXT  
V
DD  
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2007-05-22  
TCA62746AFG/AFNG  
Absolute Maximum Ratings (T = 25°C)  
a
Characteristics  
Symbol  
Rating *1  
Unit  
P o w e r s u p p l y v o l t a g e  
V
0.4 to 6.0  
V
mA  
V
DD  
O u t p u t  
L o g i c i n p u t v o l t a g e  
O u t p u t v o l t a g e  
c u r r e n t  
I
55  
O
V
0.3 to V  
+ 0.3 *2  
IN  
DD  
V
0.3 to 17  
V
O
O p e r a t i n g t e m p e r a t u r e  
S t o r a g e t e m p e r a t u r e  
T
40 to 85  
°C  
°C  
opr  
T
55 to 150  
stg  
T h e r m a l r e s i s t a n c e  
P o w e r d i s s i p a t i o n  
Rth(j-a)  
PD  
94(AFG type When mounted PCB)/120(AFNG type When mounted PCB) *3  
1.32(AFG type When mounted PCB)/1.04(AFNG type When mounted PCB) *3,4  
°C/W  
W
Note1: Voltage is ground referenced.  
Note2: However, do not exceed 6V.  
Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming)  
Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each  
degree (1°C) that the ambient temperature is exceeded (Ta = 25°C).  
Recommended Operating Conditions  
DC Items (Unless otherwise specified, T = −40°C to 85°C)  
a
Characteristics  
Symbol  
Test Conditions  
Min  
Typ.  
Max  
Unit  
P o w e r s u p p l y v o l t a g e  
Output voltage when OFF  
Output voltage when ON  
High level logic input voltage  
Low level logic input voltage  
High level SOUT output current  
Low level SOUT output current  
Constant current output  
V
4.5  
5.5  
16  
4
V
V
DD  
V
OUTn  
OUTn  
O (OFF)  
V
0.7  
2.0  
GND  
V
O (ON)  
V
V
DD  
V
IH  
V
0.8  
1  
1
V
IL  
I
V
DD  
= 5 V  
mA  
mA  
mA  
OH  
I
V
DD  
= 5 V  
OL  
I
OUTn  
2
50  
O
AC Items (Unless otherwise specified, V = 4.5 to 5.5 V, T = 40°C to 85°C)  
DD  
a
Test Conditions  
Characteristics  
Symbol Test Circuits  
Min  
Typ.  
Max  
Unit  
Serial data transfer frequency  
C l o c k p u l s e w i d t h  
L a t c h p u l s e w i d t h  
f
7
7
7
7
7
7
7
7
7
7
7
7
7
7
20  
20  
100  
2
25  
MHz  
ns  
ns  
ns  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK  
t
SCK = “H” or “L”  
SLAT = “H”  
wSCK  
t
wSLAT  
t
OE = “H” or “L” ,R  
= 500 Ω  
wOE1  
wOE2  
EXT  
E n a b l e p u l s e w i d t h  
t
When error is detected *1  
t
t
t
t
5
HOLD1  
HOLD2  
HOLD3  
HOLD4  
5
H
S
o
l
d
t
i
m
m
e
e
10  
10  
5
t
SETUP1  
SETUP2  
SETUP3  
SETUP4  
t
t
t
5
e
t
u
p
t
i
10  
10  
Maximum clock rise time  
Maximum clock fall time  
t
r
*2  
*2  
500  
500  
t
f
Note1: Please refer to page 16 for details of the error detection.  
Note2: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform,  
it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when  
designing your application.  
6
2007-05-22  
TCA62746AFG/AFNG  
Electrical Characteristics (Unless otherwise specified, VDD = 4.5 to 5.5 V and T = 25°C)  
a
Characteristics  
Symbol Test Circuits  
Test Conditions  
= 1 mA, SOUT  
Min  
Typ.  
Max  
Unit  
V
V
DD  
High level logic output voltage  
V
OH  
1
I
I
OH  
0.4  
Low level logic output voltage  
High level logic input current  
Low level logic input current  
V
1
2
3
= +1 mA, SOUT  
0.4  
1
V
OL  
OH  
I
IH  
V
V
V
= V , OE , SIN, SCK  
DD  
µA  
µA  
IN  
IN  
O
I
= GND, SLAT , SIN, SCK  
1  
IL  
= 16 V, No R  
EXT  
SCK = “L”, OE = “H”  
I
I
4
4
0.1  
0.5  
7.0  
mA  
mA  
DD1  
R
= 1.56 k,  
EXT  
All output OFF  
DD2  
R
= 500 ,  
EXT  
All output OFF  
I
I
I
4
4
4
5
5
15  
47  
14.0  
7.0  
mA  
mA  
mA  
mA  
mA  
P o w e r s u p p l y c u r r e n t  
DD3  
DD4  
DD5  
R
= 1.2 k,  
EXT  
All output ON  
R
= 500 ,  
EXT  
All output ON  
14.0  
15.9  
49.8  
V
DD  
= 5.0V, V = 1.0 V,  
O
I
I
14.1  
44.2  
O1  
O2  
OK  
R
EXT  
= 1.56 kΩ  
Constant current output  
V
DD  
= 5.0V, V = 1.0 V,  
O
R
EXT  
= 500 Ω  
V
O
= 16 V, R  
= 1.56 k,  
EXT  
Output OFF leak current  
C o n s t a n t c u r r e n t e r r o r  
I
5
5
5
5
±1  
±1  
±1  
0.5  
±3  
±4  
±4  
µA  
%
All output OFF  
V
DD  
= 5.0V, V = 1.0 V,  
O
I  
O
R
EXT  
= 1.56 k, OUT0 to OUT15  
VDD = 4.5 to 5.5V, V = 1.0 V,  
Constant current power supply  
v o l t a g e r e g u l a t i o n  
O
%V  
DD  
%/V  
%/V  
R
V
= 1.56 k, OUT0 to OUT15  
EXT  
= 5.0V, V = 1.0 to 3.0 V,  
Constant current output voltage  
DD  
O
%V  
O
r
e
g
u
l
a
t
i
o
n
R
=1.56 k, OUT0 to OUT15  
EXT  
OE  
SLAT  
P u l l - u p r e s i s t o r  
P u l l - d o w n r e s i s t o r  
R
3
2
250  
250  
500  
500  
800  
800  
kΩ  
kΩ  
UP  
R
DOWN  
Electrical Characteristics during OOD/OSD Mode  
(Unless otherwise specified, V = 4.5 to 5.5 V and T = 25°C)  
DD  
a
Characteristics  
Symbol Test Circuits  
Test Conditions  
Min  
Typ.  
Max  
Unit  
O
O
O
S
D
D
v
v
o
o
l
l
t
t
a
a
g
g
e
e
V
6
6
R
R
= 464 ~11.5 kΩ  
0.30  
3.0  
0.40  
V
V
OOD  
EXT  
V
= 464 ~11.5 kΩ  
2.85  
OSD  
EXT  
7
2007-05-22  
TCA62746AFG/AFNG  
Switching Characteristics (Unless otherwise specified, T = 25°C and V = 5.0 V)  
a
DD  
Characteristics  
SCK- OUT0  
Symbol Test Circuits  
Test Conditions  
Min  
Typ.  
Max  
Unit  
t
t
t
7
7
7
7
7
7
7
7
7
7
SLAT = “H”, OE = “L”  
5
20  
20  
20  
10  
50  
50  
50  
20  
30  
70  
100  
100  
100  
pLH1  
pLH2  
pLH3  
SLAT - OUT0  
OE - OUT0  
SCK-SOUT  
SCK- OUT0  
SLAT - OUT0  
OE - OUT0  
SCK-SOUT  
OE = “L”  
SLAT = “H”  
t
SLAT = “H”, OE = “L”  
OE = “L”  
pLH  
Propagation  
d e l a y t i m e  
ns  
t
15  
100  
100  
100  
pHL1  
pHL2  
pHL3  
t
t
SLAT = “H”  
t
pHL  
O u t p u t r i s e t i m e  
O u t p u t f a l l t i m e  
t
10 to 90% of voltage waveform  
90 to 10% of voltage waveform  
150  
150  
ns  
ns  
or  
t
of  
OUTn - OUT(n +1)  
O u t p u t d e l a y t i m e  
t
7
7
20  
20  
ns  
ns  
DLY (ON)  
between adjacent outputs  
OUTn - OUT(n +1)  
O u t p u t d e l a y t i m e t  
DLY (OFF)  
between adjacent outputs  
8
2007-05-22  
TCA62746AFG/AFNG  
I/O Equivalent Circuits  
1. SCK, SIN  
2. OE  
V
V
DD  
DD  
(SCK)  
(SIN)  
OE  
GND  
GND  
3. SLAT  
4. SOUT  
V
V
DD  
DD  
SLAT  
GND  
SOUT  
GND  
5. OUT0 to OUT15  
OUT0 to OUT15  
GND  
9
2007-05-22  
TCA62746AFG/AFNG  
Test Circuits  
Test Circuit1: High level logic input voltage / Low level logic input voltage  
V
DD  
SCK  
OUT0  
OUT7  
SIN  
SLAT  
F.G  
OE  
OUT15  
V
V
= V  
DD  
= 0 V  
IH  
IL  
R
EXT  
GND  
SOUT  
t = t = 10 ns  
r
f
(10~90%)  
V
Test Circuit2: High level logic input current / Pull-down resistor  
VIN = V  
DD  
V
DD  
A
SCK  
OUT0  
OUT7  
SIN  
SLAT  
A
A
OE  
A
OUT15  
R
EXT  
GND  
SOUT  
Test Circuit3: Low level logic input current / Pull-up resistor  
V
DD  
A
SCK  
OUT0  
OUT7  
SIN  
SLAT  
A
A
OE  
A
OUT15  
R
EXT  
GND  
SOUT  
10  
2007-05-22  
TCA62746AFG/AFNG  
Test Circuit4: Power supply current  
V
DD  
SCK  
OUT0  
OUT7  
SIN  
SLAT  
F.G  
OE  
OUT15  
A
V
V
= V  
DD  
= 0 V  
IH  
IL  
R
EXT  
GND  
SOUT  
t = t = 10 ns  
r
f
(10~90%)  
Test Circuit5: Constant current output / Output OFF leak current / Constant current error  
Test Circuit5: Constant current power supply voltage regulation / Constant current output voltage regulation  
V
DD  
SCK  
OUT0  
OUT7  
A
A
SIN  
SLAT  
F.G  
OE  
OUT15  
A
V
V
= V  
DD  
= 0 V  
IH  
IL  
R
EXT  
GND  
SOUT  
t = t = 10 ns  
r
f
(10~90%)  
Test Circuit6: OOD voltage / OSD voltage  
SCK  
V
DD  
OUT0  
OUT7  
SIN  
SLAT  
V
V
V
F.G  
OE  
OUT15  
V
V
= V  
DD  
= 0 V  
IH  
IL  
R
EXT  
GND  
SOUT  
t = t = 10 ns  
r
f
(10~90%)  
All output terminals is set to turning on, only one output terminal is connected with the VO2 power supply,  
and VO2 is changed. VOOD/VOSD is confirmed by the error detection result from SOUT.  
11  
2007-05-22  
TCA62746AFG/AFNG  
Test Circuit7: Switching Characteristics  
SCK  
R
L
= 85 Ω  
V
DD  
OUT0  
OUT7  
C
L
SIN  
SLAT  
F.G  
R
C
L
OE  
L
R
L
OUT15  
V
V
= V  
DD  
= 0 V  
IH  
IL  
R
EXT  
GND  
SOUT  
C = 10.5 pF  
L
t = t = 10 ns  
r
f
(10~90%)  
Output Delay Circuit  
This is designed for high speed switching between outputs and is intended to have the effect of reducing  
switching noise by reducing the di/dt when all outputs are ON or OFF at the same time.There is a switching time  
lag (20 ns typ.) between adjacent outputs.  
The equivalent circuit chart of the delay circuit is shown in the following.  
OE  
OUT0  
D0  
×1  
OUT1  
Delay  
D1  
×2  
OUT2  
Delay  
Delay  
D2  
×15  
OUT15  
Delay  
Delay  
D15  
12  
2007-05-22  
TCA62746AFG/AFNG  
Timing Waveforms  
1. SCK, SIN, SOUT  
t
wSCK  
90%  
10%  
90%  
10%  
SCK  
SIN  
50%  
50%  
50%  
t
SETUP1  
t
wSCK  
t
t
f
r
50%  
50%  
50%  
t
HOLD1  
SOUT  
t
/t  
pLH pHL  
2. SCK, SIN, SLAT , OE, OUT0  
SCK  
50%  
50%  
SIN  
t
t
SETUP2  
HOLD2  
50%  
SLAT  
50%  
t
t
wOE1  
wSLAT  
50%  
50%  
OE  
OUT0  
50%  
t
/t  
pHL1 pLH1  
t
/t  
pHL2 pLH2  
3. OUT0  
t
wOE1  
50%  
50%  
OE  
tpLH3  
tpHL3  
90%  
OFF  
ON  
90%  
50%  
10%  
50%  
10%  
OUT0  
t
of  
t
or  
13  
2007-05-22  
TCA62746AFG/AFNG  
4. OOD Mode/OSD Mode  
twsck  
SCK  
50%  
50%  
50%  
t
t
HOLD3  
SETUP3  
50%  
50%  
OE  
t
t
HOLD4  
SETUP4  
50%  
SLAT  
50%  
5. OOD/OSD Read Mode  
SCK  
OE  
50%  
50%  
50%  
50%  
t
wOE2  
14  
2007-05-22  
TCA62746AFG/AFNG  
PWM grayscale control  
This IC is possible to PWM grayscale control by the input of the PWM signal to the EN terminal.  
When PWM grayscale control is done, we recommend the LED power-supply voltage to be set to become the  
satiety region of the constant current characteristic. When using this IC outside the saturation area, PWM grayscale  
control cannot be normally done.  
Switching to Open Circuit Detection (OOD) and Short Circuit Detection (OSD) Modes  
Switching to OSD mode  
1
2
3
4
5
6
SCK  
OE  
H
L
L
L
H
L
H
H
H
L
H
L
SLAT  
The signal sequence set to be in the OSD mode. Here, the SLAT active pulse would not latch any data.  
Switching to OOD mode  
1
2
3
4
5
6
SCK  
OE  
H
L
L
L
H
L
H
L
H
L
H
H
SLAT  
The signal sequence set to be in the OOD mode. Here, the SLAT active pulse would not latch any data.  
15  
2007-05-22  
TCA62746AFG/AFNG  
Reading Error Status Code  
>
n
3
=
1
2
3
SCK  
OE  
MIN 2 µs  
L
H
L
L
H
H
H
H
H
SOUT  
Error status code  
Bit  
15  
Bit Bit Bit Bit Bit  
14 13 12 11 10  
When the above signal sequence is set in the OOD and OSD modes, the error state code can be read through the  
terminal SOUT.  
Error state code of OOD detection mode  
Error state code  
State of output terminal  
Open circuit  
VOOD VO  
VOOD < VO  
0
1
Normal  
Error state code of OSD detection mode  
Error state code  
State of output terminal  
Short circuit  
VOSD VO  
VOSD > VO  
0
1
Normal  
Description  
In the OOD and OSD modes, the state of OE must be switched from “H” to “L”. And, then, This IC would  
execute Open-/Short-circuit Detection as well as enabling output ports to drive current.  
At least three clock must be inputs at the “L” state of OE and the third clock should be at least 2 µs after  
the falling edge of OE . the detected error status into the built-in shift register is done by rising edge of  
this third clock.  
When OE is “L", the serial data cannot be input from the terminal SIN.  
When OE is changed from “L" to “H", the error state code is output from the terminal SOUT  
synchronizing with the clock.  
Switching to Normal Mode  
1
2
3
4
5
6
SCK  
OE  
H
L
L
L
H
L
H
L
H
L
H
L
“L” level  
SLAT  
The signal sequence set to be in the Normal mode.  
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2007-05-22  
TCA62746AFG/AFNG  
Timing chart of error detection mode (OSD mode)  
SOUT, 0  
SIN, 1 SOUT, 1  
TCA62746, 1  
SIN, 2  
TCA62746, 2  
SOUT, 2  
SOUT, N-1  
SIN, 0  
TCA62746, 0  
TCA62746, N-2  
TCA62746, N-1  
SCK  
SLAT  
OE  
N × 16 CLK  
3 CLK or more  
N × 15 CLK  
1
2
3
4
5
6
1
2
3
4
5
6
SCK  
SIN  
SIN, 0  
2
1
0
Don’t care  
2CLK  
N × 16-1  
2 µs  
SLAT  
OE  
SOUT, 0  
SOUT, 1  
15 14  
31 30  
N×16-1  
SOUT, N-1  
E. Switching to Normal  
C. Detection the error  
D. Reading back the error status code  
Error: 0, Normal: 1  
A. Switching to Error detection mode  
B. Setting of output terminal that does the error  
17  
2007-05-22  
TCA62746AFG/AFNG  
Reference data  
*This data is provided for reference only. Thorough evaluation and testing should be implemented when  
designing your application's mass production design.  
Set output current – Duty cycle graph  
IO - Duty  
IO - Duty  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
VDD=5.5V  
VO=1.0V  
Ta=25°C  
ON PCB  
All output ON  
VDD=5.5V  
VO=1.0V  
Ta=55°C  
ON PCB  
All output ON  
TCA62746AFG  
TCA62746AFG  
TCA62746AFNG  
TCA62746AFNG  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
Duty - Turn on rate (%)  
Duty - Turn on rate (%)  
PD - Ta  
IO - Duty  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
60  
50  
40  
30  
20  
10  
0
TCA62746AFG  
TCA62746AFNG  
VDD=5.5V  
VO=1.0V  
Ta=80°C  
ON PCB  
All output ON  
T
TCA62746AFG  
TCA62746AFNG  
ON PCB  
0
20  
40  
60  
80  
100  
0
10  
20  
30  
40  
Ta (  
50  
60  
70  
80  
90  
Duty - Turn on rate (%)  
)
18  
2007-05-22  
TCA62746AFG/AFNG  
Reference data  
*This data is provided for reference only. Thorough evaluation and testing should be implemented when  
designing your application's mass production design.  
Output Current – REXT Resistor  
IO - REXT  
50  
Theoretical value  
IO (A) = (1.23(V) ÷ REXT ()) × 19  
45  
40  
35  
30  
25  
20  
15  
10  
VDD=5.0V  
VO=1.0V  
Ta=25°C  
5
0
0
1
2
3
4
5
6
7
8
9
10 11 12  
REXT (k )  
Constant current characteristic  
IO - VO  
60  
VDD=5.0V  
VO=1.0V  
Ta=25°C  
50  
40  
30  
20  
10  
0
0.0  
0.5  
1.0  
1.5  
VO (V)  
2.0  
2.5  
3.0  
19  
2007-05-22  
TCA62746AFG/AFNG  
Package Dimensions  
Weight: 0.32 g (typ.)  
20  
2007-05-22  
TCA62746AFG/AFNG  
Package Dimensions  
Weight: 0.14 g (typ.)  
21  
2007-05-22  
TCA62746AFG/AFNG  
Serge resisting  
The terminals which are weak to electro static discharge are shown in the following table.  
MM Model ESD test Result  
(Internal Standard ±200V)  
pin  
- Serge  
+ Serge  
Standard  
VDD  
TEST Result  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
200V  
Standard  
VDD  
TEST Result  
200V  
200V  
200V  
200V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
160V  
200V  
200V  
200V  
200V  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
VDD,GND  
GND  
22  
2007-05-22  
TCA62746AFG/AFNG  
Notes on Contents  
1. Block Diagrams  
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for  
explanatory purposes.  
2. Equivalent Circuits  
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory  
purposes.  
3. Timing Charts  
Timing charts may be simplified for explanatory purposes.  
4. Application Circuits  
The application circuits shown in this document are provided for reference purposes only. Thorough  
evaluation is required, especially at the mass production design stage.  
Toshiba does not grant any license to any industrial property rights by providing these examples of  
application circuits.  
5. Test Circuits  
Components in the test circuits are used only to obtain and confirm the device characteristics. These  
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the  
application equipment.  
23  
2007-05-22  
TCA62746AFG/AFNG  
IC Usage Considerations  
Notes on handling of ICs  
[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded,  
even for a moment. Do not exceed any of these ratings.  
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury  
by explosion or combustion.  
[2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of  
over current and/or IC failure. The IC will fully break down when used under conditions that exceed its  
absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs  
from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or  
ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings,  
such as fuse capacity, fusing time and insertion circuit location, are required.  
[3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the  
design to prevent device malfunction or breakdown caused by the current resulting from the inrush  
current at power ON or the negative current resulting from the back electromotive force at power OFF. IC  
breakdown may cause injury, smoke or ignition.  
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the  
protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or  
ignition.  
[4] Do not insert devices in the wrong orientation or incorrectly.  
Make sure that the positive and negative terminals of power supplies are connected properly.  
Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding  
the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by  
explosion or combustion.  
In addition, do not use any device that is applied the current with inserting in the wrong orientation or  
incorrectly even just one time.  
[5] Carefully select external components (such as inputs and negative feedback capacitors) and load  
components (such as speakers), for example, power amp and regulator.  
If there is a large amount of leakage current such as input or negative feedback condenser, the IC output  
DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage,  
overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from  
the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC  
that inputs output DC voltage to a speaker directly.  
24  
2007-05-22  
TCA62746AFG/AFNG  
25  
2007-05-22  

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