QPL6207SR [TRIQUINT]
High-Linearity SDARS LNA;
| 型号： | QPL6207SR |
| 厂家： | 
TRIQUINT SEMICONDUCTOR |
| 描述： | High-Linearity SDARS LNA |
| 文件： | 总7页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QPL6207
High-Linearity SDARS LNA
Product Description
The QPL6207 is a high linearity, ultra-low noise gain block
amplifier in a small 2x2 mm surface-mount package. At 2332
MHz, the amplifier typically provides +34 dBm OIP3. The
amplifier does not require any negative supplies for operation
and can be biased from positive supply rails from 3.3 to 5.25 V.
The device is housed in a lead- free/green/RoHS-compliant
industry-standard 2x2 mm package.
Package: DFN, 8-pin
2.0mm x 2.0mm
The QPL6207 uses a high performance E-pHEMT process. The
low noise amplifier contains an internal active bias to maintain
high performance over temperature.
Feature Overview
High Gain device – Typical value 18.5dB
Ultra-low noise figure, 0.45 dB NF at 2332 MHz
High linearity, +34 dBm Output IP3
Functional Block Diagram
High input power ruggedness, >29 dBm PIN, MAX
Unconditionally stable
Externally controlled Icq with Vbias
Integrated shutdown control pin
3-5 V positive supply voltage: −Vgg not required
Applications
SDARS Active Antenna
Ordering Information
PART NUMBER
QPL6207SB
DESCRIPTION
5 PIECE SAMPLE BAG
25 PIECE SAMPLE BAG
100 PIECE 7” REEL
QPL6207SQ
QPL6207SR
QPL6207TR7
QPL6207PCK-01
2500 PIECE 7” REEL
EVALUATION BOARD + 5 PIECE
SAMPLE BAG
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QPL6207
High-Linearity SDARS LNA
Absolute Maximum Ratings
PARAMETER
RATING
UNITS
Storage Temperature
-65 to 150°
+7
C
V
Supply Voltage (VDD
)
RF Input Power, CW, 50Ω,T = 25°C
+30
dBm
Recommended Operating Conditions
PARAMETER
Supply Voltage (VDD
MIN
TYP
MAX
UNITS
)
+3.3
+3.3
−40
+4.5
+3.6
+5.25
+5.25
+105
+190
V
V
Bias Voltage (Vbias
)
T
°C
°C
CASE
6
T
J
(for >10 hours MTTF)
Electrical Specifications at +25˚C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operational Frequency Range
Gain
2320
17.5
2332
18.5
9.5
2345
20.5
MHz
dB
Input Return Loss
Output Return Loss
Output P1dB
dB
8.5
dB
+20
+34
0.45
dBm
dBm
dB
Output IP3
Pout=+5 dBm/tone, Δf=1 MHz
31
Noise Figure1
0.65
0.63
VDD
On state
0
V
Power Shutdown Control (Pin 6)
Off state (Power down)
On state
1.17
3.3
50
V
mA
mA
µA
2
Current, IDD
Off state (Power down)
3
4
Shutdown pin current, I
V
≥ 1.17 V
140
500
SD
PD
Thermal Resistance, θ
jc
Channel to case
53.4
°C/W
Test conditions unless otherwise noted: VDD = +4.5V, Vbias = +3.6V, Temp=+25°C, 50 Ω system
Note: 1) Noise Figure data has input trace loss de-embedded
2) Icq set by external 3.3K resistor
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QPL6207
High-Linearity SDARS LNA
Pin Configuration and Description
Pin No.
Label
Description
1
Vbias
Sets the Icq bias point for the device.
2
6
RF In
RF Input pin. A DC Block is required.
A high voltage (>1.17V) turns off the device. If the pin is pulled to ground or driven
with a voltage less than 0.63V, then the device will operate under LNA ON state.
Shut Down
RF Output pin. DC bias will also need to be injected through a RF bias
choke/inductor for operation.
7
RF Out / DCBias
NC
3, 4, 5, 8
No electrical connection. Provide grounded land pads for PCB mounting integrity.
RF/DC ground. Use recommended via pattern to minimize inductance and
thermal resistance; see PCB Mounting Pattern for suggested footprint.
Backside Paddle
RF/DC GND
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QPL6207
High-Linearity SDARS LNA
Applications Schematic
Vbias=3.6V
Vdd=4.5V
Icq
R3
40mA
4.6K
50mA
3.3K
60mA
2.55K
70mA
1.9K
80mA
1.55K
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QPL6207
High-Linearity SDARS LNA
Mechanical Information
Marking: Part number – 6207
Trace Code – XXXX
NOTES:
1. All dimensions are in millimeters. Angles are in degrees.
2. Except where noted, this part outline conforms to JEDEC standard MO-220, Issue E (Variation VGGC) for thermally enhanced
plastic very thin fine pitch quad flat no lead package (QFN).
3. Dimension and tolerance formats conform to ASME Y14.4M-1994.
4. The terminal #1 identifier and terminal numbering conform to JESD 95-1 SPP-012.
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QPL6207
High-Linearity SDARS LNA
PCB Mounting Pattern
NOTES:
1. All dimensions are in millimeters. Angles are in degrees.
2. Use 1 oz. copper minimum for top and bottom layer metal.
3. Vias are required under the backside paddle of this device for proper RF/DC grounding and thermal dissipation. We
recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10”).
4. Ensure good package backside paddle solder attach for reliable operation and best electrical performance.
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QPL6207
High-Linearity SDARS LNA
Product Compliance Information
ESD Sensitivity Ratings
Solderability
Compatible with both lead-free (260 °C max. reflow
temperature) and tin/lead (245 °C max. reflow
temperature) soldering processes.
Caution! ESD-Sensitive Device
Package contact plating: NiPdAu
ESD Rating: Class 1B
Value:
Test:
Standard:
Passes ≥ 500 V to < 1000V
Human Body Model (HBM)
JEDEC Standard JESD22-A114
This part is compliant with EU 2002/95/EC RoHS
directive (Restrictions on the Use of Certain
Hazardous Substances in Electrical and Electronic
Equipment).
ESD Rating: Class C2
Value:
Passes ≥ 500 V to <1000V Test:
Charged Device Model (CDM)
JEDEC Standard JESD22-C101
RoHs Compliance
This product also has the following attributes:
Lead Free
Standard:
Halogen Free (Chlorine, Bromine)
Antimony Free
PFOS Free
SVHC Free
MSL Rating
MSL Rating: Level 2
TBBP-A (C15H12Br402) Free
Test:
260°C convection reflow
JEDEC Standard IPC/JEDEC J-STD-020
Standard:
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