4052 [UTC]
ANALOG MULTIPLEXERS /DEMULTIPLEXERS; 模拟多路复用器/多路解复用器
| 型号： | 4052 |
| 厂家： | 
Unisonic Technologies |
| 描述： | ANALOG MULTIPLEXERS /DEMULTIPLEXERS |
| 文件： | 总9页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTC 4052
CMOS
ANALOG MULTIPLEXERS
/DEMULTIPLEXERS
DESCRIPTION
The UTC 4052 analog multiplexers is digitally
–controlled analog switch. The device feature low ON
impedance and very low OFF leakage current. Control
of analog signals up to the complete supply voltage
range can be achieved.
SOP-16
FEATURES
*Triple Diode Protection on Control Inputs
*Switch Function is Break Before Make
*Supply Voltage Range=3.0 Vdc to 18 Vdc
*Analog Voltage Range(VDD-VEE)=3.0 to 18V
*Note:VEE must be≤Vss
*Linearized Transfer Characterisstics
*Low-noise-12nV/√Cycle ,f≥1.0kHz Typical
DIP-16
ABSOLUTE MAXIMUM RATINGS*1
PARAMETER
SYMBOL
VDD
RATING
-0.5 ~ +18.0
-0.5 ~ VDD+0.5
UNIT
V
DC Supply Voltage (Referenced to VEE,Vss≥VEE)
Input or Output Voltage (DC or Transient) (Referenced to
Vin,Vout
V
Vss for Control Inputs and VEE for switch I/O)
Input Current (DC or Transient) per Control Pin
Iin
ISW
mA
mA
±10
±25
Switch Through Current
Power Dissipation *2
700
500
-55 ~ +125
-65 ~ +150
260
PD
mW
DIP-16
SOP-16
Ambient Temperature Range
TA
Tstg
TLEAD
°C
°C
°C
Storage Temperature Range
Lead Temperature (8-Second Soldering)
*1. Maximum Ratings are those values beyond which damage to the device may occur.
*2. Temperature Derating : 7.0 mW/℃ From 65℃ ~ 125℃
1
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
Dual 4-Channel Analog
Multiplexer/Demultiplexer
PIN ASSIGMENT
6
10
9
12
14
15
11
1
INHIBIT
A
B
X0
X1
X2
X3
Y0
1
2
3
4
5
6
7
8
VDD
X2
X1
X
Y0
Y2
Y
16
15
CONTROLS
X
13
COMMONS
OUT/IN
14
13
SWITCHES
IN/OUT
Y3
Y
9
5
2
4
Y1
Y2
Y3
X0
X3
A
Y1
12
11
10
9
INH
VDD=PIN16, VSS=PIN8, VEE=PIN7
VEE
Vss
Note: Control Inputs referenced to Vss.
Analog Inputs and Outputs reference to VEE.
VEE must be <Vss.
B
ELECTRICAL CHARACTERISTICS
-55°C
25°C
125°C
PARAMETER
SYMBOL TEST CONDITIONS
UNIT
V
MIN MAX MIN TYP*3 MAX MIN MAX
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Current Per
Range
VDD
3.0
18 3.0
18
3.0
18
VDD-3.0≥Vss≥VEE
Quiescent Current
Per Package
IDD
Control Inputs:
Vin=Vss or VDD,Switch
I/O : VEE≤VI/O≤≤VDD,
and△Vswitch≤500mV *4
VDD=5.0V
µA
µA
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
VDD=10V
VDD=15V
Total Supply Current
(Dynamic Plus
Quiescent, Per
Package
ID(AV)
TA=25℃only (The
channel component,
(Vin-Vout) /Ron, is not
included.)
VDD=5.0V
(0.07µA/kHz)f+IDD
VDD=10V
Typical (0.20µA/kHz)f+IDD
(0.36µA/kHz)f+IDD
VDD=15V
CONTROL INPUTS-INHIBIT, A, B, C (Voltages Referenced to Vss)
Low-Level Input
Voltage
VIL
Ron=per spec,
Ioff=per spec
VDD=5.0V
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
VDD=10V
VDD=15V
High-Level Input
Voltage
VIH
Ron=per spec,
Ioff=per spec
VDD=5.0V
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
-
-
-
VDD=10V
VDD=15V
2
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
-55°C
25°C
125°C
PARAMETER
SYMBOL TEST CONDITIONS
UNIT
µA
MIN MAX MIN TYP*3 MAX MIN MAX
1.0
Input Leakage
Current
Iin
VDD=15V ,Vin=0 or VDD
±0.1
±10-5 ±0.1
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN –X,Y,Z(Voltages Referenced to VEE)
Recommended
VI/O
Channel On or Off
0
VDD
0
VDD
0
0
VDD
300
Vpp
Peak-to-Peak
Voltage Into or Out of
the Switch
Recommended Static
or Dynamic Voltage
Across the Switch *4
(Figure 3)
Channel On
0
600
0
600
mV
µV
△Vswitch
Output Offset
Voo
Ron
Vin=0V,No Load
10
Voltage
△Vswitch≤500mV *4
Vin=VIL or VIH (Control),
and Vin=0 to VDD(Switch)
VDD=5.0V
ON Resistance
Ω
800
400
220
70
50
45
250
120
80
25
10
10
1050
500
1200
520
VDD=10V
280
300
VDD=15V
70
50
45
135
△ON Resistance
Between Any Two
Channels in the
△Ron VDD=5.0V
VDD=10V
95
Ω
65
VDD=15V
Same Package
±1000
±100
±100
Off-Channel Leakage
Current(Figure 8)
Ioff
VDD=15V ,Vin=VIL or VIH
(Control) Channel to
Channel or Any One
Channel
±0.05
nA
Capacitance,
Switch I/O
Capacitance,
Common O/I
Capacitance,
Feedthrough
(Channel Off)
CI/O
CO/I
CI/O
Inhibit=VDD
Inhibit=VDD
10
32
pF
pF
pF
Pins Not Adjacent
Pins Adjacent
0.15
0.47
*3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential
*performance.
*4. For voltage drops across the switch (△Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD
*current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The
*reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data
*sheet.)
3
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
ELECTRICAL CHARACTERISTICS*5 (CL = 50 pF, TA = 25℃) (VEE ≤VSS unless otherwise indicated)
TYP*6
PARAMETER
SYMBOL
tPLH,tPHL
TEST CONDITIONS
MIN
MAX UNIT
Propagation Delay
Times(Figure 4)
Switch Input to Switch
Output
Propagation Delay
Times(Figure 4)
Inhibit to Output
RL=10kΩ
30
12
10
75
VDD-VEE= 5.0, tPLH,tPHL=(0.17 ns/pF) CL+21.5 ns
VDD-VEE=10, tPLH,tPHL=(0.08 ns/pF) CL+8.0 ns
VDD-VEE=15, tPLH,tPHL=(0.06 ns/pF) CL+7.0 ns
ns
30
25
tPHZ,tPLZ
tPZH,tPZL
RL=10kΩ,VEE=Vss
Output”1” or “0” to High Impedance, or
High Impedance to”1” or “0” Level
VDD-VEE= 5.0
ns
300
155
125
600
310
250
VDD-VEE=10
VDD-VEE=15
Propagation Delay
Times(Figure 4)
tPLN,tPHL
RL=10kΩ,VEE=Vss
VDD-VEE= 5.0
325
130
90
650
ns
Control Input to Output
260
VDD-VEE=10
180
VDD-VEE=15
Second Harmonic
Distortion
Bandwidth (Figure 5)
0.07
%
RL=10kΩ, f=1kHz, Vin=5Vpp, VDD-VEE=10
BW
17
RL=1kΩ, Vin=1/2(VDD-VEE)p-p, CL=50pF,
20 Log (Vout/Vin)=-3dB, VDD-VEE=10
RL=1kΩ, Vin=1/2(VDD-VEE)p-p, Fin=30MHz,
VDD-VEE=10
MHz
dB
Off Channel
-50
Feedthrough Attenuation
(Figure 5)
Channel Separation
-50
75
RL=1kΩ, Vin=1/2(VDD-VEE)p-p, fin=3.0MHz,
VDD-VEE=10
dB
(Figure 6)
Crosstalk ,Control Input
to Common O/I (Figure
7)
R1=1kΩ, RL=10kΩ,
mV
Control tTLH=tTHL=20ns ,Inhibit=Vss), VDD-VEE=10
*5. The formulas given are for the typical characteristics only at 25 ℃.
*6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential
*performance.
4
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
VDD
VDD
VDD
IN/OUT
OUT/IN
VEE
VDD
LEVEL
CONVERTED
CONTROL
OUT/IN
IN/OUT
CONTROL
VEE
Figure 1.Switch Circuit Schematic
16
VDD
INH
A
B
6
10
9
BINARY TO 1-OF-4
DECODER WITH
INHIBIT
LEVEL
TRUTH TABLE
Control Inputs
CONVERTER
Select
ON Switches
8
Vss
7
VEE
Inhibit
B
A
X0 12
X1 14
X2 15
0
0
0
0
0
0
1
1
0
1
0
1
Y0
Y1
Y2
Y3
X0
X1
X2
X3
X
Y
13
3
X
X
1
None
11
X3
* X=Don't Care
Y0
Y1
Y2
Y3
1
5
2
4
Figure 2. Functional Diagram
TEST CIRCUITS
5
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
ON SWITCH
LOAD
A
B
C
PULSE
GENERATOR
CONTROL
SECTION
OF IC
Vout
INH
CL
V
RL
SOURCE
VDD
VEE
VEE
VDD
Figure 4. Propagation Delay Times, Control and Inhibit to Output
Figure 3.→△V Across Switch
A,B,and C inputs used to tum ON or OFF
the switch under tes.
RL
A
B
C
A
B
C
ON
Vout
CL=50pF
OFF
Vout
INH
INH
RL
Vss
CL=50pF
RL
Vin
Vin
VDD
VEE
VDD
VEE
2
2
Figure 6. Channel Separation
Figure 5. Bandwidth and Off-Channe Feedthrough Attenuation
(Adjacent Channels Used For Setup)
6
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
OFF CHANNEL UNDER TEST
VDD
A
B
C
VEE
OTHER
CONTROL
SECTION
OF IC
CHANNEL(S)
Vout
CL=50pF
VEE
INH
VDD
RL
R1
VEE
COMMON
VDD
Figure 7. Crosstalk,Control Input to Common O/I
VDD
Figure 8. Off Channel Leakage
KEITHLEY 160
DIGITAL
MULTIMETER
10K
1kΩ
RANGE
X-Y
PLOTTER
VDD
VEE=VSS
Figure 9. Channel Resistance(RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTIS
350
300
250
350
300
250
200
150
100
200
TA=125℃
150
100
TA=125℃
25℃
-55℃
25℃
-55℃
50
0
50
0
-6.0
6.0
-6.0
0
6.0
0.2 4.0 8.0 10
0
-10 -8.0
-4.0 -2.0
-10 -8.0
-4.0 -2.0
0.2 4.0
8.0 10
Vin,INPUT VOLTAGE (VOLTS)
Figure11.VDD=5.0V,VEE=-5.0V
Vin,INPUT VOLTAGE (VOLTS)
Figure10.VDD=7.5V,VEE=-7.5V
7
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
700
600
350
300
TA=25℃
500
400
250
200
VDD=2.5V
300
200
150
100
5.0V
TA=125℃
7.5V
25℃
100
0
-55℃
50
0
-6.0
0
6.0
-10
-8.0
-4.0 -2.0
Vin, INPUT VOLTAGE (VOLTS)
Figure13 Comparison at 25℃,VDD=-VEE
0.2
4.0
8.0 10
-6.0
0
6.0
-10
-8.0
-4.0 -2.0
0.2
4.0
8.0 10
Vin,INPUT VOLTAGE (VOLTS)
Figure12.VDD=2.5V,VEE=-2.5V
Figure A illustrates use of the on–chip level converter detailed in Figures 2. The 0 ~ 5 V Digital Control
signal is used to directly control a 9 Vp–p analog signal.
The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum
recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD –
VSS = 5 V maximum swing above VSS; VSS – VEE = 5 V maximum swing below VSS. The example shows a ± 4.5 V
signal which allows a 1/2 volt margin at each peak. If voltage transients above VDD and/or below VEE are anticipated
on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small
signal types able to absorb the maximum anticipated current surges during clipping.
The absolute maximum potential difference between VDD and VEE is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference between VDD and VEE.
Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10
V, VSS = + 5 V, and VEE – 3 V is acceptable. See the Table below.
+5V
-5V
VEE
VDD
Vss
+4.5V
+5V
9 Vp-p
SWITCH
I/O
9 Vp-p
ANALOG SIGNAL
COMMON
O/I
ANALOG SIGNAL
GND
-4.5V
4052
EXTERNAL
CMOS
DIGITAL
0 ~ 5V DIGITAL
CIRCUITRY
INHIBIT,
A,B,C
CONTROL SIGNALS
Figure A. Application Example
8
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
UTC 4052
CMOS
VDD
VDD
Dx
Dx
Dx
Dx
ANALOG
I/O
COMMON
O/I
VEE
VEE
Figure B.External Germanium or Schottky Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS
CONTROL INPUTS
MAXIMUM ANALOG
SIGNAL RANGE IN
VOLTS
VDD
VSS
VEE
LOGIC HIGH/LOGIC LOW
IN VOLTS
IN VOLTS
IN VOITS
IN VOLTS
+8/0
+8
+5
0
0
-8
-12
0
+8 ~ -8=16Vp-p
+5 ~–12=17Vp-p
+5 ~ 0=5Vp-p
+5/0
+5
0
+5/0
+5
0
-5
+5/0
+5 ~ -5=10Vp-p
+10 ~ –5=15Vp-p
+10
+5
-5
+10/+5
9
UTC UNISONIC TECHNOLOGIES CO., LTD.
QW-R502-013,A
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