DG2018DN-T1-E4 [VISHAY]
Low Voltage, Dual DPDT and Quad SPDT Analog Switches; 低电压，双路DPDT和四路SPDT模拟开关
| 型号： | DG2018DN-T1-E4 |
| 厂家： | 
VISHAY |
| 描述： | Low Voltage, Dual DPDT and Quad SPDT Analog Switches |
| 文件： | 总10页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG2018, DG2019
Vishay Siliconix
Low Voltage, Dual DPDT and Quad SPDT Analog Switches
DESCRIPTION
FEATURES
The DG2018 and DG2019 are low voltage, single supply
analog switches. The DG2018 is a dual double-pole/double-
throw (DPDT) with two control inputs that each controls a
pair of single-pole/double-throw (SPDT). The DG2019 uses
one control pin to operate four independent SPDT switches.
•
Low voltage operation (1.8 V to 5.5 V)
•
Low on resistance
- RDS(on): 6 Ω at 2.7 V
Low voltage logic compatible
- DG2019: VINH = 1 V
•
•
When operated on a + 3 V supply, the DG2018’s control pins
are compatible with 1.8 V digital logic. The DG2019 has an
available feature of a VL pin that allows a 1.0 V threshold for
the control pin when VL is powered with 1.5 V.
High bandwidth: 180 MHz
• QFN-16 package
BENEFITS
Built on Vishay Siliconix’s low voltage submicron CMOS
process, the DG2018 and DG2019 are ideal for high
performance switching of analog signals; providing low on-
resistance (6 Ω at + 2.7 V), fast speed (Ton, Toff at 42 ns and
16 ns), and a bandwidth that exceeds 180 MHz.
•
•
•
•
•
•
Ideal for both analog and digital signal switching
Reduced power consumption
High accuracy
Reduced PCB space
Fast switching
The DG2018 and DG2019 were designed to offer solutions
that extend beyond audio/video functions, to providing the
performance required for today’s demanding mixed-signal
switching in portable applications.
Low leakage
APPLICATIONS
•
•
•
•
•
Cellular phones
An epitaxial layer prevents latch-up. Brake-before-make is
guaranteed for all SPDT’s. All switches conduct equally well
in both directions when on, and blocks up to the power
supply level when off.
Audio and video signal routing
PCMCIA cards
Battery operated systems
Portable instrumentation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG2018DN
QFN-16 (3 X 3)
TRUTH TABLE
IN1, IN2
COM1 NO1
16 15
V+
14
NC4
13
Logic
NC1 and NC2
NO1 and NO2
0
1
ON
OFF
ON
OFF
IN3, IN4
NC1
IN1, IN2
NO2
COM4
NO4
1
2
3
4
12
11
10
9
Logic
NC3 and NC4
NO3 and NO4
0
1
ON
OFF
ON
OFF
IN3, IN4
NC3
COM2
ORDERING INFORMATION
Temp. Range
Package
Part Number
5
6
7
8
- 40 °C to 85 °C
QFN-16 (3 x 3 mm)
DG2018DN
NC2 GND NO3 COM3
Top View
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
1
DG2018, DG2019
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG2019DN
QFN-16 (3 X 3)
TRUTH TABLE
COM1 NO1
16 15
V+
14
NC4
13
Logic
NC1, 2, 3 and 4
NO1, 2, 3 and 4
0
1
ON
OFF
ON
OFF
NC1
IN
COM4
NO4
1
2
3
4
12
11
10
9
ORDERING INFORMATION
Temp. Range
Package
Part Number
NO2
COM2
V
L
- 40 °C to 85 °C
QFN-16 (3 x 3 mm)
DG2019DN
NC3
5
6
7
8
NC2 GND NO3 COM3
Top View
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Unit
Reference V+ to GND
- 0.3 to + 6
V
IN, COM, NC, NO
- 0.3 to (V+ + 0.3)
Continuous Current (Any terminal)
Peak Current (Pulsed at 1 ms, 10 % Duty Cycle)
Storage Temperature (D Suffix)
50
100
mA
- 65 to 150
850
°C
Power Dissipation (Packages)b
QFN-16 (3 x 3 mm)c
mW
Notes:
a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 4.0 mW/°C above 70 °C.
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2
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
DG2018, DG2019
Vishay Siliconix
SPECIFICATIONS V+ = 3 V
Test Conditions
Otherwise Unless Specified
V+ = 3 V, 10 %,
(DG2018 Only) VIN = 0.5 or 1.4 Ve
Limits
- 40 °C to 85 °C
(DG2019 Only) VL = 1.5 V, VIN = 0.4 or 1.0 Ve
Parameter
Symbol
Temp.a Min.b
Typ.c
Max.b
Unit
Analog Switch
VNO, VNC
VCOM
,
Analog Signal Ranged
Full
0
V+
V
V+ = 2.7 V, VCOM = 0.2 V/1.5 V
INO, INC = 10 mA
Room
Full
6
12
15
RON
On-Resistance
RON
Flatness
Ω
R
ON Flatness
Room
Room
0.5
0.6
0.3
2
3
V+ = 2.7 V
COM = 0 to V+, INO, INC = 10 mA
V
RON Match Between
ΔRON
Channels
INO(off)
INC(off)
Room
Full
- 1
- 10
1
10
V+ = 3.3 V, VNO, VNC = 0.3 V/3 V
VCOM = 3 V/0.3 V
Switch Off Leakage Current
Room
Full
- 1
- 10
1
10
nA
ICOM(off)
ICOM(on)
0.3
0.3
Room
Full
- 1
10
1
10
V+ = 3.3 V, VNO, VNC = VCOM = 0.3 V/3 V
Channel-On Leakage Current
Digital Control
DG2018
Full
Full
Full
Full
Full
Full
1.4
1.0
VINH
Input High Voltage
Input Low Voltage
VL = 1.5 V
VL = 1.5 V
DG2019
DG2018
DG2019
V
0.5
0.4
VINL
Cin
Input Capacitance
Input Current
f = 1 MHz
VIN = 0 or V+
9
pF
µA
IINL or IINH
- 1
1
Dynamic Characteristics
Room
Full
42
16
55
65
tON
Turn-On Time
Turn-Off Time
VNO or VNC = 2.0 V, RL = 300 Ω, CL = 35 pF
Room
Full
25
35
ns
tOFF
td
VNO or VNC = 2.0 V, RL = 50 Ω, CL = 35 pF
CL = 1 nF, VGEN = 0 V, RGEN = 0 Ω
Break-Before-Make Time
Charge Injectiond
Off-Isolationd
Crosstalkd
Bandwidthd
Full
1
QINJ
Room
Room
Room
Room
Room
Room
Room
Room
- 1.46
- 67
- 72
180
9
pC
dB
OIRR
XTALK
RL = 50 Ω, CL = 5 pF, f = 1 MHz
BW
MHz
CNO(off)
CNC(off)
CNO(on)
CNC(on
NO, NC Off Capacitanced
9
VIN = 0 or V+, f = 1 MHz
pF
µA
30
Channel-On Capacitanced
30
Power Supply
VIN = 0 or V+
Power Supply Current
I+
Full
0.01
1.0
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. Typical values are for design aid only, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
3
DG2018, DG2019
Vishay Siliconix
SPECIFICATIONS V+ = 5 V
Test Conditions
Otherwise Unless Specified
V+ = 5 V, 10 %,
(DG2018 Only) VIN = 0.8 or 1.8 Ve
Limits
- 40 °C to 85 °C
(DG2019 Only) VL = 1.5 V, VIN = 0.4 or 1.0 Ve
Parameter
Symbol
Temp.a Min.b
Typ.c
Max.b
Unit
Analog Switch
VNO, VNC
VCOM
,
Analog Signal Ranged
On-Resistance
Full
0
V+
V
Room
Full
4
8
10
RON
V+ = 4.5 V, VCOM = 3 V, INO, INC = 10 mA
RON
Flatness
Ω
R
ON Flatness
Room
Room
0.6
0.6
1.2
1.2
V+ = 4.5 V
VCOM = 0 to V+, INO, INC = 10 mA
RON Match Between Channels
ΔRON
INO(off)
INC(off)
Room
Full
- 1
- 10
1
10
0.03
V+ = 5.5 V
NO, VNC = 1 V/4.5 V, VCOM = 4.5 V/1 V
Switch Off Leakage Currentf
V
Room
Full
- 1
- 10
1
10
nA
ICOM(off)
ICOM(on)
0.03
0.03
Room
Full
- 1
- 10
1
10
Channel-On Leakage Currentf
V+ = 5.5 V, VNO, VNC = VCOM = 1 V/4.5 V
Digital Control
DG2018
Full
Full
Full
Full
Full
Full
1.8
1.0
VINH
Input High Voltage
Input Low Voltage
VL = 1.5 V
VL = 1.5 V
DG2019
DG2018
DG2019
V
0.8
0.4
VINL
Cin
Input Capacitance
Input Current
9
pF
µA
I
INL or IINH
VIN = 0 or V+
1
1
1
Dynamic Characteristics
Room
Full
44
19
48
52
tON
Turn-On Time
Turn-Off Time
VNO or VNC = 3 V, RL = 300 Ω, CL = 35 pF
Room
Full
33
35
ns
tOFF
td
VNO or VNC = 3 V, RL = 50 Ω, CL = 35 pF
CL = 1 nF, VGEN = 0 V, RGEN = 0 Ω
Break-Before-Make Time
Charge Injectiond
Off-Isolationd
Crosstalkd
Bandwidthd
Full
QINJ
Room
Room
Room
Room
Room
Room
Room
Room
- 2.46
- 67
- 72
180
7.5
pC
dB
OIRR
XTALK
RL = 50 Ω, CL = 5 pF, f = 1 MHz
BW
MHz
CNO(off)
CNC(off)
CNO(on)
CNC(on
Source-Off Capacitanced
Channel-On Capacitanced
7.5
VIN = 0 or V+, f = 1 MHz
pF
30
30
Power Supply
Power Supply Range
Power Supply Current
V+
I+
1.8
5.5
1.0
V
VIN = 0 or V+
Full
0.01
µA
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. Typical values are for design aid only, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Not production tested.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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4
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
DG2018, DG2019
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
9
8
7
6
5
4
3
2
1
0
V+ = 2.7 V
85 °C
25 °C
T = 25 °C
COM
I
= 10 mA
8
6
4
2
0
- 40 °C
V+ = 2.7 V
V+ = 3.3 V
V+ = 5.5 V
85 °C
V+ = 5.5 V
25 °C
- 40 °C
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
COM
- Analog Voltage (V)
V
COM
- Analog Voltage (V)
RON vs. Analog Voltage and Temperature
RON vs. VCOM and Supply Voltage
10 mA
1 mA
10 000
1000
100 µA
10 µA
1 µA
V+ = 5.5 V
IN
V
= 0 V
100
10
100 nA
10 nA
1
0
0
2 M
Input Switching Frequency (Hz)
Supply Current vs. Input Switching Frequency
4 M
6 M
8 M
10 M
- 60 - 40 - 20
0
Temperature (°C)
Supply Current vs. Temperature
20
40
60
80
100
150
125
100
75
10 000
1000
V+ = 5 V
V = 3.3 V
+
50
I
COM(off)
I
COM(on)
25
I
, II
NO(off) NC(off)
100
10
0
- 25
- 50
- 75
- 100
- 125
- 150
I
, I
NO(off) NC(off)
I
COM(off)
I
COM(on)
1
- 60 - 40 - 20
0
20
40
60
80
100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
, V , V - Analog Voltage (V)
COM NO NC
Temperature (°C)
Leakage Current vs. Temperature
Leakage vs. Analog Voltage
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
www.vishay.com
5
DG2018, DG2019
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
R
L
= 300 Ω
DG2018
t
V+ = 3.3 V
ON
40
30
20
10
0
ON/OFF
t
V+ = 5.5 V
ON
OFF/ON
t
V+ = 3.3 V
OFF
t
V+ = 5.5 V
OFF
- 60 - 40 - 20
0
20
40
60
80
100
0
1
2
3
4
5
6
-
V
+
Supply Voltage (V)
Temperature (°C)
Switching Time vs. Temperature
and Supply Voltage
Switching Voltage vs. Supply Voltage (V+)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
10
8
DG2019
V
+
= 5.5 V
6
4
V+ = 3.3 V
= 5.5 V
2
V
+
0
V+ = 3.3 V
- 2
- 4
- 6
0
1
2
3
4
5
6
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
COM
- Analog Voltage (V)
V
L
(V)
Charge Injection at Source vs. Analog Voltage
VIN vs. VL (Typ)
10
0
Loss
- 10
- 20
- 30
- 40
- 50
- 60
- 70
- 80
- 90
- 100
V+ = 3.0 V, 5.5 V
R
= 50 Ω, C = 5 pF
L
L
OIRR
X
TALK
- 110
100K
1M
10M
Frequency (Hz)
100M
1G
Insertion Loss, Off Isolation and Crosstalk
vs. Frequency
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6
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
DG2018, DG2019
Vishay Siliconix
TEST CIRCUITS
V+
V+
V
V
INH
t < 5 ns
f
r
Logic
Input
50 %
t < 5 ns
INL
Switch Output
NO or NC
COM
Switch
Input
V
OUT
0.9 x V
OUT
IN
GND
Switch
Output
R
300 Ω
C
L
35 pF
L
0 V
Logic
Input
t
t
OFF
ON
0 V
Logic "1" = Switch On
Logic input waveforms inverted for switches that have
the opposite logic sense.
C
L
(includes fixture and stray capacitance)
R
L
+ R
V
= V
COM
OUT
R
L
ON
Figure 1. Switching Time
V+
ΔV
V+
OUT
R
gen
V
OUT
NC or NO
IN
COM
V
OUT
+
IN
V
gen
C
= 1 nF
L
On
On
Off
Q = ΔV
V
IN
= 0 - V+
GND
x C
OUT
L
IN depends on switch configuration: input polarity
determined by sense of switch.
Figure 2. Charge Injection
Logic
Input
V
V
t < 5 ns
f
INH
r
t < 5 ns
V+
COM
NO
NC
INL
V
O
V
NO
V
NC
R
50 Ω
C
L
35 pF
L
V
NC
= V
NO
V
IN
90 %
O
GND
Switch
Output
0 V
t
D
t
D
C
L
(includes fixture and stray capacitance)
Figure 3. Break-Before-Make Interval
Document Number: 72342
S-82626-Rev. C, 03-Nov-08
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7
DG2018, DG2019
Vishay Siliconix
TEST CIRCUITS
V+
10 nF
V+
NC or NO
0 V, 2.4 V
IN
COM
COM
R
L
GND
Analyzer
V
COM
Off Isolation = 20 log
V
NO/ NC
Figure 4. Off-Isolation
V+
V+
10 nF
COM
Meter
IN
HP4192A
Impedance
Analyzer
0 V, 2.4 V
or Equivalent
NC or NO
GND
f = 1 MHz
Figure 5. Channel Off/On Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?72342.
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Document Number: 72342
S-82626-Rev. C, 03-Nov-08
Package Information
Vishay Siliconix
QFN−16 LEAD (3 X 3)
D2
D2/2
D
Terminal Tip
3
-B-
D/2
L
E/2
e
E
E2
3 x e
4
Exposed Pad
4xb
M
0.10
C
A
B
0.25
C
3
3 x e
TOP VIEW
BOTTOM VIEW
// 0.10
0.08
C
C
A
A1
NX
4
SEATING
PLANE
-C-
A3
SIDE VIEW
NOTES:
1. All dimensions are in millimeters.
2. N is the total number of terminals.
3. Dimension b applies to metallized terminal and is measured between 0.25 and 0.30 mm from terminal tip.
4. Coplanarity applies to the exposed heat sink slug as well as the terminal.
5. The pin #1 identifier may be either a mold or marked feature, it must be located within the zone iindicated.
VARIATION 1
VARIATION 2
MILLIMETERS
Dim
MILLIMETERS
INCHES
INCHES
Min
Nom
Max
Min
0.031
0.007
Nom
Max
0.039
0.012
Min
0.80
0.18
Nom
Max
1.00
0.30
Min
0.031
0.007
Nom
Max
0.039
0.012
0.80
0.18
0.90
0.23
1.00
0.30
0.035
0.009
0.90
0.25
0.035
0.010
A
b
3.00 BSC
1.15
0.118 BSC
0.045
3.00 BSC
1.70
0.118 BSC
0.067
D
D2
E
E2
e
L
1.00
1.00
0.30
1.25
1.25
0.50
0.039
0.039
0.012
0.049
0.049
0.020
1.55
1.55
0.30
1.80
1.80
0.50
0.061
0.061
0.012
0.071
0.071
0.020
3.00 BSC
1.15
0.118 BSC
0.045
3.00 BSC
1.70
0.118 BSC
0.067
0.50 BSC
0.40
0.020 BSC
0.016
0.50 BSC
0.40
0.020 BSC
0.016
ECN: S-32625—Rev. B, 29-Dec-03
DWG: 5899
Document Number: 72208
29-Dec-03
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1
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Revision: 02-Oct-12
Document Number: 91000
1
相关型号：
DG2019DN-E3
IC QUAD 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, QCC16, 3 X 3 MM, QFN-16, Multiplexer or Switch
VISHAY
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