SI4446DY [VISHAY]
N-Channel 40-V (D-S) MOSFET; N通道40 -V （D -S ）的MOSFET
| 型号： | SI4446DY |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 40-V (D-S) MOSFET |
| 文件： | 总9页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
New Product
Si4446DY
Vishay Siliconix
N-Channel 40-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
Qg (Typ.)
I
D (A)d
Definition
TrenchFET® Power MOSFET
100 % Rg
100 % Rg UIS Tested
0.040 at VGS = 10 V
0.045 at VGS = 4.5 V
5.2
4.9
•
•
•
40
8
APPLICATIONS
CCFL Inverter
•
SO-8
D
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
D
G
Top View
S
N-Channel MOSFET
Ordering Information: Si4446DY-T1-E3 (Lead (Pb)-free)
Si4446DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
10 s
Steady State
Unit
VDS
Drain-Source Voltage
Gate-Source Voltage
40
12
V
VGS
TA = 25 °C
A = 70 °C
5.2
4.2
3.9
3.1
Continuous Drain Current (TJ = 150 °C)a
ID
T
IDM
IS
Pulsed Drain Current
30
A
Continuous Source Current (Diode Conduction)a
Avalanche Current
1.7
0.9
IAS
EAS
13
L = 0.1 mH
Single-Pulse Avalanche Energy
8.5
mJ
W
TA = 25 °C
TA = 70 °C
2.0
1.3
1.1
0.7
Maximum Power Dissipationa
PD
TJ, Tstg
Operating Junction and Storage Temperature Range
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
52
Maximum
62.5
Unit
t ≤ 10 s
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
RthJA
RthJF
Steady State
Steady State
90
110
°C/W
32
40
Notes:
a. Surface mounted on 1" x 1" FR4 board.
Document Number: 73661
S09-0322-Rev. B, 02-Mar-09
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1
New Product
Si4446DY
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VGS(th)
ΔVDS/TJ
ΔVGS(th)/TJ
IGSS
VDS = VGS, ID = 250 µA
ID = 250 µA
Gate-Source Threshold Voltage
0.6
1.6
V
mV/°C
nA
V
DS Temperature Coefficient
40
VGS(th) Temperature Coefficient
Gate-Body Leakage
- 3.8
VDS = 0 V, VGS
=
12 V
100
1
VDS = 40 V, VGS = 0 V
IDSS
ID(on)
Zero Gate Voltage Drain Current
On-State Drain Currenta
µA
VDS = 40 V, VGS = 0 V, TJ = 55 °C
10
VDS ≥ 5 V, VGS = 10 V
20
A
VGS = 10 V, ID = 5.2 A
0.033
0.037
18
0.040
0.045
Drain-Source On-State Resistancea
RDS(on)
Ω
VGS = 4.5 V, ID = 4.9 A
Forward Transconductancea
Diode Forward Voltagea
gfs
VDS = 15 V, ID = 5.2 A
IS = 1.7 A, VGS = 0 V
S
V
VSD
0.75
1.2
Dynamicb
Ciss
Coss
Crss
Qg
Input Capacitance
700
76
45
8
VDS = 20 V, VGS = 0 V, f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
pF
12
Qgs
Qgd
Rg
VDS = 20 V, VGS = 4.5 V, ID = 5.2 A
f = 1 MHz
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
1.5
2.4
1.9
7
nC
2.9
11
17
40
13
40
26
Ω
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
V
DD = 15 V, RL = 15 Ω
11
27
8
ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω
Turn-Off DelayTime
Fall Time
ns
Source-Drain Reverse Recovery Time
Body Diode Reverse Recovery Charge
trr
25
17
IF = 1.7 A, dI/dt = 100 A/µs
Qrr
nC
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 73661
S09-0322-Rev. B, 02-Mar-09
New Product
Si4446DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
20
20
16
12
8
V
GS
= 10 V thru 3 V
16
12
8
T
= 125
C
2 V
4
4
25 °C
- 55 °C
0
0
0
1
2
3
4
5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
- Gate-to-Source Voltage (V)
V
- Drain-to-Source Voltage (V)
GS
DS
Output Characteristics
Transfer Characteristics
0.050
0.045
0.040
0.035
0.030
0.025
0.020
1200
1000
800
600
400
200
0
C
iss
V
GS
= 4.5 V
V
GS
= 10 V
C
oss
C
rss
0
4
8
12
16
20
0
5
10
15
20
25
30
35
40
I
D
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
1.8
1.6
1.4
1.2
1.0
0.8
0.6
6
5
4
3
2
1
0
V
D
= 10 V
I
D
= 5.2 A
GS
= 5.2 A
I
V
= 10 V
DS
V
DS
= 20 V
- 50 - 25
0
25
50
75
100 125 150
0
1
2
3
4
5
6
7
8
9
10 11
Q
- Total Gate Charge (nC)
T - Junction Temperature (°C)
g
J
On-Resistance vs. Junction Temperature
Gate Charge
Document Number: 73661
S09-0322-Rev. B, 02-Mar-09
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3
New Product
Si4446DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.20
0.16
0.12
0.08
0.04
0.00
20
I
D
= 5.2 A
10
T
= 150 °C
J
T
= 125 °C
A
T
= 25 °C
J
T
A
= 25 °C
6
1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
2
4
8
10
V
GS
- Gate-to-Source Voltage (V)
V
- Source-to-Drain Voltage (V)
SD
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.4
0.2
100
80
I
D
= 250 µA
60
- 0.0
- 0.2
- 0.4
- 0.6
40
20
0
- 50 - 25
0
25
50
75
100 125 150
0.01
0.001
0.1
1
10
T
- Temperature (°C)
Time (s)
J
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
Limited by R
*
DS(on)
10
1 ms
1
10 ms
100 ms
0.1
T
= 25 °C
C
1 s
10 s
Single Pulse
DC
0.01
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V
GS
> minimum V at which R
is specified
GS
DS(on)
Safe Operating Area
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Document Number: 73661
S09-0322-Rev. B, 02-Mar-09
New Product
Si4446DY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
0.1
Notes:
P
DM
0.1
t
0.05
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 90 C/W
thJA
(t)
3. T - T = P
JM
Z
A
DM thJA
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73661.
Document Number: 73661
S09-0322-Rev. B, 02-Mar-09
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Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
2
5
4
E
H
1
3
S
h x 45
D
C
0.25 mm (Gage Plane)
A
All Leads
0.101 mm
q
e
B
A
1
L
0.004"
MILLIMETERS
Max
INCHES
DIM
A
Min
Min
Max
1.35
0.10
0.35
0.19
4.80
3.80
1.75
0.20
0.51
0.25
5.00
4.00
0.053
0.004
0.014
0.0075
0.189
0.150
0.069
0.008
0.020
0.010
0.196
0.157
A1
B
C
D
E
e
1.27 BSC
0.050 BSC
H
h
5.80
0.25
0.50
0°
6.20
0.50
0.93
8°
0.228
0.010
0.020
0°
0.244
0.020
0.037
8°
L
q
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050
1.27
0.088
2.25
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
0.288
7.3
0.050
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
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1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
0.022
0.050
(0.559)
(1.270)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
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the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
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provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
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