SI4963BDY [VISHAY]
Dual P-Channel 2.5-V (G-S) MOSFET; 双P沟道2.5 -V (G -S )的MOSFET![SI4963BDY](http://pdffile.icpdf.com/pdf1/p00023/img/icpdf/SI4963_114231_icpdf.jpg)
型号: | SI4963BDY |
厂家: | ![]() |
描述: | Dual P-Channel 2.5-V (G-S) MOSFET |
文件: | 总3页 (文件大小:237K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SPICE Device Model Si4963BDY
Vishay Siliconix
Dual P-Channel 2.5-V (G-S) MOSFET
CHARACTERISTICS
· P-Channel Vertical DMOS
· Macro Model (Subcircuit Model)
· Level 3 MOS
· Apply for both Linear and Switching Application
· Accurate over the - 55 to 125°C Temperature Range
· Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the - 55 to 125°C
temperature ranges under the pulsed 0 to 5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72770
20-May-04
www.vishay.com
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SPICE DeviceModel Si4963BDY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Conditions
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Currentb
VGS(th)
ID(on)
1.1
92
V
A
VDS = VGS, ID = - 250 mA
VDS = - 5 V, VGS = - 4.5 V
VGS = - 4.5 V, ID = - 6.5 A
VGS = - 2.5 V, ID = - 2 A
VDS = - 10 V, ID = - 6.5 A
IS = - 1.7 A, VGS = 0 V
0.025
0.041
16
0.025
0.040
18
Drain-Source On-State Resistanceb
rDS(on)
W
Forward Transconductanceb
Diode Forward Voltageb
gfs
S
V
VSD
- 0.80
- 0.75
Dynamica
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Qg
Qgs
Qgd
td(on)
tr
12
2.6
4.6
30
22
65
20
14
2.6
4.6
25
30
70
50
VDS = - 10 V, VGS = - 4.5 V, ID = - 6.5 A
nC
ns
VDD = - 10 V, RL = 10 W
D @ - 1 A, VGEN = - 4.5 V, RG = 6 W
I
Turn-Off Delay Time
Fall Time
td(off)
tf
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width £ 300 ms, duty cycle £ 2%.
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Document Number: 72770
20-May-04
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SPICE Device Model Si4963BDY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72770
20-May-04
www.vishay.com
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