SI7840BDP-T1-GE3 [VISHAY]

Power Field-Effect Transistor, 11A I(D), 30V, 0.0085ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, POWERPAK, SOP-8;
SI7840BDP-T1-GE3
型号: SI7840BDP-T1-GE3
厂家: VISHAY    VISHAY
描述:

Power Field-Effect Transistor, 11A I(D), 30V, 0.0085ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, POWERPAK, SOP-8

开关 脉冲 光电二极管 晶体管
文件: 总12页 (文件大小:303K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Si7840BDP  
Vishay Siliconix  
N-Channel 30-V (D-S) Fast Switching MOSFET  
FEATURES  
PRODUCT SUMMARY  
Halogen-free According to IEC 61249-2-21  
Available  
VDS (V)  
RDS(on) (Ω)  
ID (A)  
16.5  
13  
Qg (Typ.)  
TrenchFET® Power MOSFET  
New Low Thermal Resistance PowerPAK®  
Package with Low 1.07 mm Profile  
0.0085 at VGS = 10 V  
0.0105 at VGS = 4.5 V  
30  
14  
100 % Rg Tested  
PowerPAK SO-8  
APPLICATIONS  
DC/DC Converters  
S
6.15 mm  
5.15 mm  
Optimized for “High-Side” Synchronous Rectifier  
Operations  
1
S
2
S
3
G
4
D
D
8
D
7
D
6
D
5
G
Bottom View  
S
Ordering Information:  
Si7840BDP-T1-E3 (Lead (Pb)-free)  
Si7840BDP-T1-GE3 (Lead (Pb)-free and Halogen-free)  
N-Channel MOSFET  
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted  
A
Parameter  
Symbol  
10 s  
Steady State  
Unit  
VDS  
VGS  
Drain-Source Voltage  
Gate-Source Voltage  
30  
50  
V
20  
TA = 25 °C  
TA = 70 °C  
16.5  
13  
11  
8
Continuous Drain Current (TJ = 150°C)a  
ID  
IDM  
IS  
IAS  
EAS  
Pulsed Drain Current  
Continuous Source Current (Diode Conduction)a  
Avalanche Current  
A
3.7  
1.6  
20  
20  
L = 0.1 mH  
Avalanche Energy  
mJ  
W
TA = 25 °C  
TA = 70 °C  
4.1  
2.6  
1.8  
1.1  
Maximum Power Dissipationa  
PD  
TJ, Tstg  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak Temperature)c, d  
- 55 to 150  
260  
°C  
THERMAL RESISTANCE RATINGS  
Parameter  
Symbol  
Typical  
23  
Maximum  
Unit  
t 10 s  
Steady State  
Steady State  
30  
70  
Maximum Junction-to-Ambienta  
RthJA  
60  
°C/W  
RthJC  
Maximum Junction-to-Case (Drain)  
3.1  
3.6  
Notes:  
a. Surface Mounted on 1" x 1" FR4 board.  
b. t = 10 s.  
c. See Solder Profile (http://www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed  
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and  
is not required to ensure adequate bottom side solder interconnection.  
d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.  
Document Number: 73218  
S09-0272-Rev. C, 16-Feb-09  
www.vishay.com  
1
Si7840BDP  
Vishay Siliconix  
MOSFET SPECIFICATIONS T = 25 °C, unless otherwise noted  
J
Parameter  
Symbol  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Static  
VGS(th)  
IGSS  
VDS = VGS, ID = 250 µA  
Gate Threshold Voltage  
1.0  
3.0  
100  
1
V
VDS = 0 V, VGS  
= 20 V  
Gate-Body Leakage  
nA  
VDS = 30 V, VGS = 0 V  
DS = 30 V, VGS = 0 V, TJ = 55°C  
VDS 5 V, VGS = 10 V  
IDSS  
ID(on)  
Zero Gate Voltage Drain Current  
µA  
A
V
10  
On-State Drain Currenta  
30  
VGS = 10 V, ID = 16.5 A  
0.007  
0.0084  
60  
0.0085  
0.0105  
Drain-Source On-State Resistancea  
RDS(on)  
Ω
V
GS = 4.5 V, ID = 13 A  
Forward Transconductancea  
Diode Forward Voltagea  
Dynamicb  
gfs  
VDS = 15 V, ID = 16.5 A  
IS = 3.7 A, VGS = 0 V  
S
V
VSD  
0.75  
1.1  
21  
Qg  
Qgs  
Qgd  
Rg  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
Gate Resistance  
14  
6
V
DS = 15 V, VGS = 4.5 V, ID = 16.5 A  
nC  
3.5  
0.7  
17  
14  
39  
14  
26  
20  
0.2  
1.2  
26  
21  
60  
21  
40  
Ω
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
V
DD = 15 V, RL = 15 Ω  
ID 1 A, VGEN = 10 V, Rg = 6 Ω  
Turn-Off Delay Time  
Fall Time  
ns  
trr  
Source-Drain Reverse Recovery Time  
Reverse Recovery Charge  
IF = 4.1 A, dI/dt = 100 A/µs  
Qrr  
nC  
Notes:  
a. Pulse test; pulse width 300 µs, duty cycle 2 %.  
b. Guaranteed by design, not subject to production testing.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
40  
32  
24  
16  
8
50  
40  
30  
20  
10  
0
V
= 10 thru 4 V  
GS  
T
C
= 125˚C  
25˚C  
3 V  
- 55˚C  
3.5  
0
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
4.0  
0
1
2
3
4
5
V
-
Gate-to-Source Voltage (V)  
V
-
Drain-to-Source Voltage (V)  
GS  
DS  
Output Characteristics  
Transfer Characteristics  
www.vishay.com  
2
Document Number: 73218  
S09-0272-Rev. C, 16-Feb-09  
Si7840BDP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
2500  
2000  
1500  
1000  
500  
0.012  
0.011  
0.010  
C
iss  
V
= 4.5 V  
GS  
0.009  
0.008  
0.007  
0.006  
0.005  
0.004  
V
= 10 V  
GS  
C
oss  
C
rss  
0
0
5
10  
15  
20  
25  
30  
0
5
10  
15  
20  
25  
30  
35  
40  
V
-
Drain-to-Source Voltage (V)  
I
D
-
Drain Current (A)  
DS  
On-Resistance vs. Drain Current  
Capacitance  
6
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0 .6  
V
= 15 V  
= 16.5 A  
DS  
V
= 10 V  
= 16.5 A  
GS  
5
4
3
2
1
0
I
D
I
D
0
2
4
6
8
10  
12  
14  
16  
- 50 - 25  
0
25  
T - Junction Temperature (°C)  
J
50  
75  
100 125 150  
Q
g
- Total Gate Charge (nC)  
Gate Charge  
On-Resistance vs. Junction Temperature  
0.05  
0.04  
0.03  
0.02  
0.01  
0.00  
40  
I
D
= 16.5 A  
T = 150˚C  
J
10  
T = 25˚C  
J
1
0.0  
0
2
4
6
8
10  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
-
Gate-to-Source Voltage (V)  
V
- Source-to-Drain Voltage (V)  
GS  
SD  
Source-Drain Diode Forward Voltage  
On-Resistance vs. Gate-to-Source Voltage  
Document Number: 73218  
S09-0272-Rev. C, 16-Feb-09  
www.vishay.com  
3
Si7840BDP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
0.4  
50  
40  
0.2  
I
D
= 250 μA  
-0.0  
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
30  
20  
10  
0
-50 -25  
0
25  
50  
75  
100 125 150  
0.001  
0.01  
0.1  
1
10  
100  
600  
T - Temperature (˚C)  
J
Time (s)  
Single Pulse Power  
Threshold Voltage  
100  
Limited by R  
DS(on)*  
10  
1 ms  
10 ms  
1
100 ms  
1 s  
10 s  
dc  
0.1  
T
= 25 °C  
C
Single Pulse  
0.01  
0.1  
1
10  
100  
V
-
Drain-to-Source Voltage (V)  
DS  
* V  
GS  
> minimum V at which R is specified  
GS  
DS(on)  
Safe Operating Area, Junction-to-Case  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
Notes:  
P
DM  
0.1  
0.05  
0.02  
t
1
t
2
t
t
1
2
1. Duty Cycle, D =  
2. Per Unit Base = R  
= 58°C/W  
thJA  
(t)  
Z
3. T  
-
T
= P  
DM thJA  
JM  
A
Single Pulse  
4. Surface Mounted  
0.01  
-
4
-
3
-
2
-
1
10  
10  
10  
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
1
10  
100  
600  
www.vishay.com  
4
Document Number: 73218  
S09-0272-Rev. C, 16-Feb-09  
Si7840BDP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
Single Pulse  
0.01  
-4  
10  
-3  
10  
-2  
10  
-1  
10  
1
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Case  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see www.vishay.com/ppg?73218.  
Document Number: 73218  
S09-0272-Rev. C, 16-Feb-09  
www.vishay.com  
5
Package Information  
www.vishay.com  
Vishay Siliconix  
PowerPAK® SO-8, (Single/Dual)  
L
H
E2  
K
E4  
W
1
1
2
3
4
Z
2
3
4
D
L1  
E3  
A1  
Backside View of Single Pad  
L
H
K
E2  
E4  
2
E1  
E
Detail Z  
1
2
3
4
D1  
D2  
Notes  
1. Inch will govern.  
E3  
2
Dimensions exclusive of mold gate burrs.  
Backside View of Dual Pad  
3. Dimensions exclusive of mold flash and cutting burrs.  
MILLIMETERS  
INCHES  
NOM.  
0.041  
DIM.  
MIN.  
NOM.  
1.04  
MAX.  
1.12  
0.05  
0.51  
0.33  
5.26  
5.00  
3.91  
1.68  
MIN.  
0.038  
0
MAX.  
0.044  
0.002  
0.020  
0.013  
0.207  
0.197  
0.154  
0.066  
A
A1  
b
0.97  
-
-
0.33  
0.23  
5.05  
4.80  
3.56  
1.32  
0.41  
0.013  
0.009  
0.199  
0.189  
0.140  
0.052  
0.016  
c
0.28  
0.011  
D
5.15  
0.203  
D1  
D2  
D3  
D4  
D5  
E
4.90  
0.193  
3.76  
0.148  
1.50  
0.059  
0.57 typ.  
3.98 typ.  
6.15  
0.0225 typ.  
0.157 typ.  
0.242  
6.05  
5.79  
3.48  
3.68  
6.25  
5.99  
3.84  
3.91  
0.238  
0.228  
0.137  
0.145  
0.246  
0.236  
0.151  
0.154  
E1  
E2  
E3  
E4  
e
5.89  
0.232  
3.66  
0.144  
3.78  
0.149  
0.75 typ.  
1.27 BSC  
1.27 typ.  
-
0.030 typ.  
0.050 BSC  
0.050 typ.  
-
K
K1  
H
0.56  
0.51  
0.51  
0.06  
0°  
-
0.022  
0.020  
0.020  
0.002  
0°  
-
0.61  
0.71  
0.71  
0.20  
12°  
0.024  
0.028  
0.028  
0.008  
12°  
L
0.61  
0.024  
L1  
0.13  
0.005  
-
-
W
M
0.15  
0.25  
0.36  
0.006  
0.010  
0.014  
0.125 typ.  
0.005 typ.  
ECN: S17-0173-Rev. L, 13-Feb-17  
DWG: 5881  
Revison: 13-Feb-17  
Document Number: 71655  
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
VISHAY SILICONIX  
www.vishay.com  
Power MOSFETs  
Application Note AN821  
PowerPAK® SO-8 Mounting and Thermal Considerations  
by Wharton McDaniel  
PowerPAK SO-8 SINGLE MOUNTING  
MOSFETs for switching applications are now available with  
die on resistances around 1 mand with the capability to  
handle 85 A. While these die capabilities represent a major  
advance over what was available just a few years ago, it is  
important for power MOSFET packaging technology to keep  
pace. It should be obvious that degradation of a high  
performance die by the package is undesirable. PowerPAK  
is a new package technology that addresses these issues.  
In this application note, PowerPAK’s construction is  
described. Following this mounting information is presented  
including land patterns and soldering profiles for maximum  
reliability. Finally, thermal and electrical performance is  
discussed.  
The PowerPAK single is simple to use. The pin arrangement  
(drain, source, gate pins) and the pin dimensions are the  
same as standard SO-8 devices (see figure 2). Therefore, the  
PowerPAK connection pads match directly to those of the  
SO-8. The only difference is the extended drain connection  
area. To take immediate advantage of the PowerPAK SO-8  
single devices, they can be mounted to existing SO-8 land  
patterns.  
THE PowerPAK PACKAGE  
The PowerPAK package was developed around the SO-8  
package (figure 1). The PowerPAK SO-8 utilizes the same  
footprint and the same pin-outs as the standard SO-8. This  
allows PowerPAK to be substituted directly for a standard  
SO-8 package. Being a leadless package, PowerPAK SO-8  
utilizes the entire SO-8 footprint, freeing space normally  
occupied by the leads, and thus allowing it to hold a larger  
die than a standard SO-8. In fact, this larger die is slightly  
larger than a full sized DPAK die. The bottom of the die  
attach pad is exposed for the purpose of providing a direct,  
low resistance thermal path to the substrate the device is  
mounted on. Finally, the package height is lower than the  
standard SO-8, making it an excellent choice for  
applications with space constraints.  
Standard SO-8  
PowerPAK SO-8  
Fig. 2  
The minimum land pattern recommended to take full  
advantage of the PowerPAK thermal performance see  
Application Note 826, Recommended Minimum Pad  
Patterns With Outline Drawing Access for Vishay Siliconix  
MOSFETs. Click on the PowerPAK SO-8 single in the index  
of this document.  
In this figure, the drain land pattern is given to make full  
contact to the drain pad on the PowerPAK package.  
This land pattern can be extended to the left, right, and top  
of the drawn pattern. This extension will serve to increase  
the heat dissipation by decreasing the thermal resistance  
from the foot of the PowerPAK to the PC board and  
therefore to the ambient. Note that increasing the drain land  
area beyond a certain point will yield little decrease  
in foot-to-board and foot-to-ambient thermal resistance.  
Under specific conditions of board configuration, copper  
weight and layer stack, experiments have found that  
more than about 0.25 in2 to 0.5 in2 of additional copper  
(in addition to the drain land) will yield little improvement in  
thermal performance.  
Fig. 1 PowerPAK 1212 Devices  
Revision: 16-Mai-13  
Document Number: 71622  
1
For technical questions, contact: powermosfettechsupport@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Application Note AN821  
www.vishay.com  
Vishay Siliconix  
PowerPAK® SO-8 Mounting and Thermal Considerations  
For  
the  
lead  
(Pb)-free  
solder  
profile,  
see  
PowerPAK SO-8 DUAL  
www.vishay.com/doc?73257.  
The pin arrangement (drain, source, gate pins) and the pin  
dimensions of the PowerPAK SO-8 dual are the same as  
standard SO-8 dual devices. Therefore, the PowerPAK  
device connection pads match directly to those of the SO-8.  
As in the single-channel package, the only exception is the  
extended drain connection area. Manufacturers can likewise  
take immediate advantage of the PowerPAK SO-8 dual  
devices by mounting them to existing SO-8 dual land  
patterns.  
To take the advantage of the dual PowerPAK SO-8’s  
thermal performance, the minimum recommended land  
pattern can be found in Application Note 826,  
Recommended Minimum Pad Patterns With Outline  
Drawing Access for Vishay Siliconix MOSFETs. Click on the  
PowerPAK 1212-8 dual in the index of this document.  
The gap between the two drain pads is 24 mils. This  
matches the spacing of the two drain pads on the  
PowerPAK SO-8 dual package.  
Fig. 3 Solder Reflow Temperature Profile  
Ramp-Up Rate  
+ 3 °C /s max.  
120 s max.  
REFLOW SOLDERING  
Temperature at 150 - 200 °C  
Temperature Above 217 °C  
Maximum Temperature  
Vishay Siliconix surface-mount packages meet solder reflow  
reliability requirements. Devices are subjected to solder  
60 - 150 s  
255 + 5/- 0 °C  
reflow as  
a
test preconditioning and are then  
reliability-tested using temperature cycle, bias humidity,  
HAST, or pressure pot. The solder reflow temperature profile  
used, and the temperatures and time duration, are shown in  
figures 3 and 4.  
Time at Maximum  
Temperature  
30 s  
Ramp-Down Rate  
+ 6 °C/s max.  
30 s  
260 °C  
3 °C(max)  
6 °C/s (max.)  
217 °C  
150 - 200 °C  
150 s (max.)  
60 s (min.)  
Reflow Zone  
Pre-Heating Zone  
Maximum peak temperature at 240 °C is allowed.  
Fig. 4 Solder Reflow Temperatures and Time Durations  
Revision: 16-Mai-13  
Document Number: 71622  
2
For technical questions, contact: powermosfettechsupport@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Application Note AN821  
www.vishay.com  
Vishay Siliconix  
PowerPAK® SO-8 Mounting and Thermal Considerations  
THERMAL PERFORMANCE  
Introduction  
Because of the presence of the trough, this result suggests  
a minimum performance improvement of 10 °C/W by using  
a PowerPAK SO-8 in a standard SO-8 PC board mount.  
A basic measure of a device’s thermal performance  
is the junction-to-case thermal resistance, RthJC, or the  
junction-to-foot thermal resistance, RthJF This parameter is  
measured for the device mounted to an infinite heat sink and  
is therefore a characterization of the device only, in other  
words, independent of the properties of the object to which  
the device is mounted. Table 1 shows a comparison of  
the DPAK, PowerPAK SO-8, and standard SO-8. The  
PowerPAK has thermal performance equivalent to the  
DPAK, while having an order of magnitude better thermal  
performance over the SO-8.  
The only concern when mounting a PowerPAK on a  
standard SO-8 pad pattern is that there should be no traces  
running between the body of the MOSFET. Where the  
standard SO-8 body is spaced away from the pc board,  
allowing traces to run underneath, the PowerPAK sits  
directly on the pc board.  
Thermal Performance - Spreading Copper  
Designers may add additional copper, spreading copper, to  
the drain pad to aid in conducting heat from a device. It is  
helpful to have some information about the thermal  
performance for a given area of spreading copper.  
TABLE 1 - DPAK AND POWERPAK SO-8  
EQUIVALENT STEADY STATE  
PERFORMANCE  
Figure 6 shows the thermal resistance of a PowerPAK SO-8  
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.  
The two internal layers and the backside layer are solid  
copper. The internal layers were chosen as solid copper to  
model the large power and ground planes common in many  
applications. The top layer was cut back to a smaller area  
and at each step junction-to-ambient thermal resistance  
measurements were taken. The results indicate that an area  
above 0.3 to 0.4 square inches of spreading copper gives no  
PowerPAK  
SO-8  
Standard  
SO-8  
DPAK  
Thermal  
Resistance RthJC  
1.2 °C/W  
1 °C/W  
16 °C/W  
Thermal Performance on Standard SO-8 Pad Pattern  
Because of the common footprint, a PowerPAK SO-8  
can be mounted on an existing standard SO-8 pad pattern.  
The question then arises as to the thermal performance  
of the PowerPAK device under these conditions. A  
characterization was made comparing a standard SO-8 and  
a PowerPAK device on a board with a trough cut out  
underneath the PowerPAK drain pad. This configuration  
restricted the heat flow to the SO-8 land pads. The results  
are shown in figure 5.  
additional  
thermal  
performance  
improvement.  
A
subsequent experiment was run where the copper on the  
back-side was reduced, first to 50 % in stripes to mimic  
circuit traces, and then totally removed. No significant effect  
was observed.  
R
th  
vs. Spreading Copper  
(0 %, 50 %, 100 % Back Copper)  
56  
51  
46  
41  
36  
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board  
SO-8 Pattern, Trough Under Drain  
60  
50  
40  
Si4874DY  
30  
100 %  
Si7446DP  
0 %  
20  
50 %  
10  
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00  
Spreading Copper (sq in)  
0
Fig. 6 Spreading Copper Junction-to-Ambient Performance  
0.0001  
0.01  
1
10000  
100  
Pulse Duration (sec)  
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal  
Path  
Revision: 16-Mai-13  
Document Number: 71622  
3
For technical questions, contact: powermosfettechsupport@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Application Note AN821  
www.vishay.com  
Vishay Siliconix  
PowerPAK® SO-8 Mounting and Thermal Considerations  
Suppose each device is dissipating 2.7 W. Using the  
SYSTEM AND ELECTRICAL IMPACT OF  
PowerPAK SO-8  
junction-to-foot thermal resistance characteristics of the  
PowerPAK SO-8 and the standard SO-8, the die  
temperature is determined to be 107 °C for the PowerPAK  
(and for DPAK) and 148 °C for the standard SO-8. This is a  
2 °C rise above the board temperature for the PowerPAK  
and a 43 °C rise for the standard SO-8. Referring to figure 7,  
a 2 °C difference has minimal effect on RDS(on) whereas a  
In any design, one must take into account the change in  
MOSFET RDS(on) with temperature (figure 7).  
On-Resistance vs. Junction Temperature  
1.8  
43 °C difference has a significant effect on RDS(on)  
.
V
= 10 V  
= 23 A  
GS  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
I
D
Minimizing the thermal rise above the board temperature by  
using PowerPAK has not only eased the thermal design but  
it has allowed the device to run cooler, keep rDS(on) low, and  
permits the device to handle more current than the same  
MOSFET die in the standard SO-8 package.  
CONCLUSIONS  
PowerPAK SO-8 has been shown to have the same thermal  
performance as the DPAK package while having the same  
footprint as the standard SO-8 package. The PowerPAK  
SO-8 can hold larger die approximately equal in size to the  
maximum that the DPAK can accommodate implying no  
sacrifice in performance because of package limitations.  
-50  
-25  
0
25  
50  
75  
100 125 150  
T
J
- Junction Temperature (°C)  
Recommended PowerPAK SO-8 land patterns are provided  
to aid in PC board layout for designs using this new  
package.  
Fig. 7 MOSFET RDS(on) vs. Temperature  
A MOSFET generates internal heat due to the current  
passing through the channel. This self-heating raises the  
junction temperature of the device above that of the PC  
board to which it is mounted, causing increased power  
dissipation in the device. A major source of this problem lies  
in the large values of the junction-to-foot thermal resistance  
of the SO-8 package.  
Thermal considerations have indicated that significant  
advantages can be gained by using PowerPAK SO-8  
devices in designs where the PC board was laid out for  
the standard SO-8. Applications experimental data gave  
thermal performance data showing minimum and  
typical thermal performance in a SO-8 environment, plus  
information on the optimum thermal performance  
obtainable including spreading copper. This further  
emphasized the DPAK equivalency.  
PowerPAK SO-8 minimizes the junction-to-board thermal  
resistance to where the MOSFET die temperature is very  
close to the temperature of the PC board. Consider two  
devices mounted on a PC board heated to 105 °C by other  
components on the board (figure 8).  
PowerPAK SO-8 therefore has the desired small size  
characteristics of the SO-8 combined with the attractive  
thermal characteristics of the DPAK package.  
PowerPAK SO-8  
Standard SO-8  
107 °C  
148 °C  
0.8 °C/W  
PC Board at 105 °C  
16 C/W  
Fig. 8 Temperature of Devices on a PC Board  
Revision: 16-Mai-13  
Document Number: 71622  
4
For technical questions, contact: powermosfettechsupport@vishay.com  
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single  
0.260  
(6.61)  
0.150  
(3.81)  
0.024  
(0.61)  
0.026  
(0.66)  
0.050  
(1.27)  
0.032  
(0.82)  
0.040  
(1.02)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
Document Number: 72599  
Revision: 21-Jan-08  
www.vishay.com  
15  
Legal Disclaimer Notice  
www.vishay.com  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
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typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding  
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a  
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over  
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including but not limited to the warranty expressed therein.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document  
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED  
Revision: 08-Feb-17  
Document Number: 91000  
1

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