SI7960DP [VISHAY]

Dual N-Channel 60-V (D-S) MOSFET; 双N通道60 -V (D -S )的MOSFET
SI7960DP
型号: SI7960DP
厂家: VISHAY    VISHAY
描述:

Dual N-Channel 60-V (D-S) MOSFET
双N通道60 -V (D -S )的MOSFET

文件: 总12页 (文件大小:520K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Si7960DP  
Vishay Siliconix  
Dual N-Channel 60-V (D-S) MOSFET  
FEATURES  
PRODUCT SUMMARY  
Halogen-free According to IEC 61249-2-21  
VDS (V)  
RDS(on) (Ω)  
ID (A)  
9.7  
Available  
TrenchFET® Power MOSFET  
New Low Thermal Resistance PowerPAK®  
Package  
0.021 at VGS = 10 V  
0.025 at VGS = 4.5 V  
60  
8.9  
Dual MOSFET for Space Savings  
PowerPAK SO-8  
S1  
5.15 mm  
6.15 mm  
D
1
1
D
2
G1  
2
S2  
3
G2  
4
D1  
8
D1  
7
G
1
G
2
D2  
6
D2  
5
Bottom View  
S
1
S
2
Ordering Information: Si7960DP-T1-E3 (Lead (Pb)-free)  
Si7960DP-T1-GE3 (Lead (Pb)-free and Halogen-free)  
N-Channel MOSFET  
N-Channel MOSFET  
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted  
A
Parameter  
Symbol  
10 s  
Steady State  
Unit  
VDS  
VGS  
60  
40  
Drain-Source Voltage  
Gate-Source Voltage  
V
20  
TA = 25 °C  
TA = 70 °C  
9.7  
7.8  
6.2  
5.0  
Continuous Drain Current (TJ = 150 °C)a  
ID  
IDM  
IS  
Pulsed Drain Current  
Continuous Source Current (Diode Conduction)a  
Single Avalanche Current  
A
2.9  
1.2  
IAS  
EAS  
23  
27  
L = 0.1 mH  
TA = 25 °C  
mJ  
W
Single Avalanche Energy  
3.5  
2.2  
1.4  
0.9  
Maximum Power Dissipationa  
PD  
TA = 70 °C  
TJ, Tstg  
- 55 to 150  
260  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak Temperature)b, c  
°C  
THERMAL RESISTANCE RATINGS  
Parameter  
Symbol  
RthJA  
Typical  
26  
Maximum  
Unit  
t 10 s  
Steady State  
Steady State  
35  
85  
Maximum Junction-to-Ambienta  
60  
°C/W  
Maximum Junction-to-Case (Drain)  
RthJC  
2.2  
2.7  
Notes:  
a. Surface Mounted on 1" x 1" FR4 board.  
b. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper  
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not  
required to ensure adequate bottom side solder interconnection.  
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.  
Document Number: 73075  
S09-0223-Rev. B, 09-Feb-09  
www.vishay.com  
1
Si7960DP  
Vishay Siliconix  
SPECIFICATIONS T = 25 °C, unless otherwise noted  
J
Parameter  
Symbol  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Static  
VGS(th)  
IGSS  
VDS = VGS, ID = 250 µA  
1
3
V
Gate Threshold Voltage  
VDS = 0 V, VGS  
=
20 V  
100  
1
nA  
Gate-Body Leakage  
VDS = 60 V, VGS = 0 V  
DS = 60 V, VGS = 0 V, TJ = 55 °C  
VDS 5 V, VGS = 10 V  
IDSS  
ID(on)  
Zero Gate Voltage Drain Current  
µA  
A
V
5
On-State Drain Currenta  
30  
VGS = 10 V, ID = 9.7 A  
0.017  
0.020  
33  
0.021  
0.025  
Drain-Source On-State Resistancea  
RDS(on)  
Ω
VGS = 4.5 V, ID = 8.9 A  
Forward Transconductancea  
Diode Forward Voltagea  
Dynamicb  
gfs  
VDS = 15 V, ID = 9.7 A  
IS = 2.9 A, VGS = 0 V  
S
V
VSD  
0.8  
1.2  
75  
Qg  
Qgs  
Qgd  
Rg  
49  
5.7  
8.6  
2
Total Gate Charge  
Gate-Source Charge  
Gate-Drain Charge  
Gate Resistance  
Turn-On Delay Time  
Rise Time  
V
DS = 30 V, VGS = 10 V, ID = 9.7 A  
f = 1 MHz  
nC  
Ω
td(on)  
tr  
td(off)  
tf  
12  
12  
60  
17  
30  
20  
20  
90  
30  
60  
V
DD = 30 V, RL = 30 Ω  
ID 1 A, VGEN = 10 V, RG = 6 Ω  
Turn-Off Delay Time  
Fall Time  
ns  
trr  
IF = 2.9 A, dI/dt = 100 A/µs  
Source-Drain Reverse Recovery Time  
Notes  
a. Pulse test; pulse width 300 µs, duty cycle 2 %.  
b. Guaranteed by design, not subject to production testing.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
40  
35  
30  
25  
20  
15  
10  
5
40  
35  
30  
25  
20  
15  
10  
5
V
GS  
= 10 V thru 4 V  
T
C
= 125 °C  
25 °C  
3 V  
- 55 °C  
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
V
DS  
- Drain-to-Source Voltage (V)  
V
GS  
- Gate-to-Source Voltage (V)  
Output Characteristics  
Transfer Characteristics  
www.vishay.com  
2
Document Number: 73075  
S09-0223-Rev. B, 09-Feb-09  
Si7960DP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
4000  
3500  
3000  
2500  
2000  
1500  
1000  
500  
0.030  
0.025  
C
iss  
V
GS  
= 4.5 V  
0.020  
0.015  
0.010  
0.005  
0.000  
V
GS  
= 10 V  
C
oss  
C
rss  
0
20  
30  
40  
50  
60  
0
10  
0
5
10  
15  
20  
25  
30  
35  
40  
V
DS  
- Drain-to-Source Voltage (V)  
I
- Drain Current (A)  
D
On-Resistance vs. Drain Current  
Capacitance  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
10  
V
= 10 V  
= 9.7 A  
GS  
V
I
= 20 V  
= 9.7 A  
DS  
D
I
D
8
6
4
2
0
- 50 - 25  
0
25  
50  
75  
100 125 150  
0
10  
20  
30  
40  
50  
T - Junction Temperature (°C)  
J
Q
g
- Total Gate Charge (nC)  
Gate Charge  
On-Resistance vs. Junction Temperature  
0.05  
0.04  
0.03  
0.02  
0.01  
0.00  
40  
T
J
= 150 °C  
I
= 9.7 A  
D
10  
T
= 25 °C  
J
1
0.0  
0
2
4
6
8
10  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
GS  
- Gate-to-Source Voltage (V)  
V
SD  
- Source-to-Drain Voltage (V)  
Source-Drain Diode Forward Voltage  
On-Resistance vs. Gate-to-Source Voltage  
Document Number: 73075  
S09-0223-Rev. B, 09-Feb-09  
www.vishay.com  
3
Si7960DP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
100  
80  
0.6  
0.4  
0.2  
I
= 250 µA  
D
0 . 0  
- 0.2  
- 0.4  
- 0.6  
- 0.8  
- 1.0  
- 1.2  
- 1.4  
60  
40  
20  
0
0.001  
0.01  
0.1  
10  
100  
600  
1
- 50 - 25  
0
25  
50  
75  
100 125 150  
Time (s)  
T
J
- Temperature (°C)  
Single Pulse Power  
Threshold Voltage  
100  
Limited by R  
*
I
Limited  
DS(on)  
DM  
10  
1
100 µs  
1 ms  
I
D(on)  
10 ms  
Limited  
100 ms  
T
= 25 °C  
A
1 s  
0.1  
Single Pulse  
10 s  
DC  
BVDSS Limited  
10  
0.01  
0.1  
1
100  
V
DS  
- Drain-to-Source Voltage (V)  
>
* V  
GS  
minimum V at which R  
is specified  
GS  
DS(on)  
Safe Operating Area, Junction-to-Ambient  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
Notes:  
P
DM  
0.1  
0.05  
t
1
t
2
t
t
1
2
1. Duty Cycle, D =  
0.02  
2. Per Unit Base = R  
= 60 °C/W  
thJA  
(t)  
3. T -T = P  
Z
JM  
A
DM thJA  
Single Pulse  
10  
4. Surface Mounted  
0.01  
-4  
-3  
-2  
-1  
10  
10  
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Ambient  
1
10  
100  
600  
www.vishay.com  
4
Document Number: 73075  
S09-0223-Rev. B, 09-Feb-09  
Si7960DP  
Vishay Siliconix  
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted  
2
1
Duty Cycle = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
Single Pulse  
0.01  
-4  
-3  
-2  
-1  
10  
10  
10  
Square Wave Pulse Duration (s)  
Normalized Thermal Transient Impedance, Junction-to-Case  
10  
1
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon  
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and  
reliability data, see www.vishay.com/ppg?73075.  
Document Number: 73075  
S09-0223-Rev. B, 09-Feb-09  
www.vishay.com  
5
Package Information  
Vishay Siliconix  
PowerPAK® SO-8, (SINGLE/DUAL)  
L
H
E2  
K
E4  
W
1
1
2
3
4
Z
2
3
4
D
L1  
E3  
A1  
Backside View of Single Pad  
L
H
K
E2  
E4  
2
E1  
E
Detail Z  
1
2
3
4
D1  
D2  
Notes  
1. Inch will govern.  
E3  
2
Dimensions exclusive of mold gate burrs.  
Backside View of Dual Pad  
3. Dimensions exclusive of mold flash and cutting burrs.  
MILLIMETERS  
INCHES  
NOM.  
0.041  
DIM.  
A
MIN.  
0.97  
0.00  
0.33  
0.23  
5.05  
4.80  
3.56  
1.32  
NOM.  
1.04  
MAX.  
1.12  
0.05  
0.51  
0.33  
5.26  
5.00  
3.91  
1.68  
MIN.  
0.038  
0.000  
0.013  
0.009  
0.199  
0.189  
0.140  
0.052  
MAX.  
0.044  
0.002  
0.020  
0.013  
0.207  
0.197  
0.154  
0.066  
A1  
b
-
-
0.41  
0.016  
c
0.28  
0.011  
D
5.15  
0.203  
D1  
D2  
D3  
D4  
D5  
E
4.90  
0.193  
3.76  
0.148  
1.50  
0.059  
0.57 TYP.  
3.98 TYP.  
6.15  
0.0225 TYP.  
0.157 TYP.  
0.242  
6.05  
5.79  
3.48  
3.68  
6.25  
5.99  
3.84  
3.91  
0.238  
0.228  
0.137  
0.145  
0.246  
0.236  
0.151  
0.154  
E1  
E2  
E3  
E4  
e
5.89  
0.232  
3.66  
0.144  
3.78  
0.149  
0.75 TYP.  
1.27 BSC  
1.27 TYP.  
-
0.030 TYP.  
0.050 BSC  
0.050 TYP.  
-
K
K1  
H
0.56  
0.51  
0.51  
0.06  
0°  
-
0.022  
0.020  
0.020  
0.002  
0°  
-
0.61  
0.71  
0.71  
0.20  
12°  
0.024  
0.028  
0.028  
0.008  
12°  
L
0.61  
0.024  
L1  
θ
0.13  
0.005  
-
-
W
M
0.15  
0.25  
0.36  
0.006  
0.010  
0.014  
0.125 TYP.  
0.005 TYP.  
ECN: T10-0055-Rev. J, 15-Feb-10  
DWG: 5881  
Document Number: 71655  
Revison: 15-Feb-10  
www.vishay.com  
1
AN821  
Vishay Siliconix  
®
PowerPAK SO-8 Mounting and Thermal Considerations  
Wharton McDaniel  
MOSFETs for switching applications are now available  
PowerPAK SO-8 SINGLE MOUNTING  
with die on resistances around 1 mΩ and with the  
capability to handle 85 A. While these die capabilities  
represent a major advance over what was available  
just a few years ago, it is important for power MOSFET  
packaging technology to keep pace. It should be obvi-  
ous that degradation of a high performance die by the  
package is undesirable. PowerPAK is a new package  
technology that addresses these issues. In this appli-  
cation note, PowerPAK’s construction is described.  
Following this mounting information is presented  
including land patterns and soldering profiles for max-  
imum reliability. Finally, thermal and electrical perfor-  
mance is discussed.  
The PowerPAK single is simple to use. The pin  
arrangement (drain, source, gate pins) and the pin  
dimensions are the same as standard SO-8 devices  
(see Figure 2). Therefore, the PowerPAK connection  
pads match directly to those of the SO-8. The only dif-  
ference is the extended drain connection area. To take  
immediate advantage of the PowerPAK SO-8 single  
devices, they can be mounted to existing SO-8 land  
patterns.  
THE PowerPAK PACKAGE  
The PowerPAK package was developed around the  
SO-8 package (Figure 1). The PowerPAK SO-8 uti-  
lizes the same footprint and the same pin-outs as the  
standard SO-8. This allows PowerPAK to be substi-  
tuted directly for a standard SO-8 package. Being a  
leadless package, PowerPAK SO-8 utilizes the entire  
SO-8 footprint, freeing space normally occupied by the  
leads, and thus allowing it to hold a larger die than a  
standard SO-8. In fact, this larger die is slightly larger  
than a full sized DPAK die. The bottom of the die attach  
pad is exposed for the purpose of providing a direct,  
low resistance thermal path to the substrate the device  
is mounted on. Finally, the package height is lower  
than the standard SO-8, making it an excellent choice  
for applications with space constraints.  
Standard SO-8  
PowerPAK SO-8  
Figure 2.  
The minimum land pattern recommended to take full  
advantage of the PowerPAK thermal performance see  
Application Note 826, Recommended Minimum Pad  
Patterns With Outline Drawing Access for Vishay Sili-  
conix MOSFETs. Click on the PowerPAK SO-8 single  
in the index of this document.  
In this figure, the drain land pattern is given to make full  
contact to the drain pad on the PowerPAK package.  
This land pattern can be extended to the left, right, and  
top of the drawn pattern. This extension will serve to  
increase the heat dissipation by decreasing the ther-  
mal resistance from the foot of the PowerPAK to the  
PC board and therefore to the ambient. Note that  
increasing the drain land area beyond a certain point  
will yield little decrease in foot-to-board and foot-to-  
ambient thermal resistance. Under specific conditions  
of board configuration, copper weight and layer stack,  
experiments have found that more than about 0.25 to  
2
0.5 in of additional copper (in addition to the drain  
land) will yield little improvement in thermal perfor-  
mance.  
Figure 1. PowerPAK 1212 Devices  
Document Number 71622  
28-Feb-06  
www.vishay.com  
1
AN821  
Vishay Siliconix  
PowerPAK SO-8 DUAL  
For the lead (Pb)-free solder profile, see http://  
www.vishay.com/doc?73257.  
The pin arrangement (drain, source, gate pins) and the  
pin dimensions of the PowerPAK SO-8 dual are the  
same as standard SO-8 dual devices. Therefore, the  
PowerPAK device connection pads match directly to  
those of the SO-8. As in the single-channel package,  
the only exception is the extended drain connection  
area. Manufacturers can likewise take immediate  
advantage of the PowerPAK SO-8 dual devices by  
mounting them to existing SO-8 dual land patterns.  
To take the advantage of the dual PowerPAK SO-8’s  
thermal performance, the minimum recommended  
land pattern can be found in Application Note 826,  
Recommended Minimum Pad Patterns With Outline  
Drawing Access for Vishay Siliconix MOSFETs. Click  
on the PowerPAK 1212-8 dual in the index of this doc-  
ument.  
Ramp-Up Rate  
+ 6 °C /Second Maximum  
The gap between the two drain pads is 24 mils. This  
matches the spacing of the two drain pads on the Pow-  
erPAK SO-8 dual package.  
Temperature at 155 15 °C  
120 Seconds Maximum  
Temperature Above 180 °C  
Maximum Temperature  
Time at Maximum Temperature  
Ramp-Down Rate  
70 - 180 Seconds  
240 + 5/- 0 °C  
20 - 40 Seconds  
+ 6 °C/Second Maximum  
REFLOW SOLDERING  
Vishay Siliconix surface-mount packages meet solder  
reflow reliability requirements. Devices are subjected  
to solder reflow as a test preconditioning and are then  
reliability-tested using temperature cycle, bias humid-  
ity, HAST, or pressure pot. The solder reflow tempera-  
ture profile used, and the temperatures and time  
duration, are shown in Figures 3 and 4.  
Figure 3. Solder Reflow Temperature Profile  
10 s (max)  
210 - 220 °C  
3 °C(max)  
4 °C/s (max)  
183 °C  
140 - 170 °C  
50 s (max)  
3 °C(max)  
60 s (min)  
Reflow Zone  
Pre-Heating Zone  
Maximum peak temperature at 240 °C is allowed.  
Figure 3. Solder Reflow Temperatures and Time Durations  
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2
Document Number 71622  
28-Feb-06  
AN821  
Vishay Siliconix  
THERMAL PERFORMANCE  
Introduction  
Because of the presence of the trough, this result sug-  
gests a minimum performance improvement of 10 °C/W  
by using a PowerPAK SO-8 in a standard SO-8 PC  
board mount.  
A basic measure of a device’s thermal performance is  
the junction-to-case thermal resistance, Rθ , or the  
junction-to-foot thermal resistance, Rθ . This parameter  
jc  
jf  
is measured for the device mounted to an infinite heat  
sink and is therefore a characterization of the device  
only, in other words, independent of the properties of the  
object to which the device is mounted. Table 1 shows a  
comparison of the DPAK, PowerPAK SO-8, and stan-  
dard SO-8. The PowerPAK has thermal performance  
equivalent to the DPAK, while having an order of magni-  
tude better thermal performance over the SO-8.  
The only concern when mounting a PowerPAK on a  
standard SO-8 pad pattern is that there should be no  
traces running between the body of the MOSFET.  
Where the standard SO-8 body is spaced away from the  
pc board, allowing traces to run underneath, the Power-  
PAK sits directly on the pc board.  
Thermal Performance - Spreading Copper  
Designers may add additional copper, spreading cop-  
per, to the drain pad to aid in conducting heat from a  
device. It is helpful to have some information about the  
thermal performance for a given area of spreading cop-  
per.  
TABLE 1.  
DPAK and PowerPAK SO-8  
Equivalent Steady State Performance  
DPAK  
PowerPAK  
SO-8  
Standard  
SO-8  
Thermal  
Resistance Rθjc  
1.2 °C/W  
1.0 °C/W  
16 °C/W  
Figure 6 shows the thermal resistance of a PowerPAK  
SO-8 device mounted on a 2-in. 2-in., four-layer FR-4  
PC board. The two internal layers and the backside layer  
are solid copper. The internal layers were chosen as  
solid copper to model the large power and ground  
planes common in many applications. The top layer was  
cut back to a smaller area and at each step junction-to-  
ambient thermal resistance measurements were taken.  
The results indicate that an area above 0.3 to 0.4 square  
inches of spreading copper gives no additional thermal  
performance improvement. A subsequent experiment  
was run where the copper on the back-side was  
reduced, first to 50 % in stripes to mimic circuit traces,  
and then totally removed. No significant effect was  
observed.  
Thermal Performance on Standard SO-8 Pad Pattern  
Because of the common footprint, a PowerPAK SO-8  
can be mounted on an existing standard SO-8 pad pat-  
tern. The question then arises as to the thermal perfor-  
mance of the PowerPAK device under these conditions.  
A characterization was made comparing a standard SO-8  
and a PowerPAK device on a board with a trough cut out  
underneath the PowerPAK drain pad. This configuration  
restricted the heat flow to the SO-8 land pads. The  
results are shown in Figure 5.  
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board  
SO-8 Pattern, Trough Under Drain  
R
vs. Spreading Copper  
th  
(0 %, 50 %, 100 % Back Copper)  
60  
50  
56  
51  
46  
41  
36  
40  
Si4874DY  
30  
Si7446DP  
20  
100 %  
10  
0 %  
50 %  
0
0.0001  
0.01  
1
10000  
100  
Pulse Duration (sec)  
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00  
Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path  
Figure 6. Spreading Copper Junction-to-Ambient Performance  
Document Number 71622  
28-Feb-06  
www.vishay.com  
3
AN821  
Vishay Siliconix  
SYSTEM AND ELECTRICAL IMPACT OF  
PowerPAK SO-8  
In any design, one must take into account the change in  
Suppose each device is dissipating 2.7 W. Using the  
junction-to-foot thermal resistance characteristics of the  
PowerPAK SO-8 and the standard SO-8, the die tem-  
perature is determined to be 107 °C for the PowerPAK  
(and for DPAK) and 148 °C for the standard SO-8. This  
is a 2 °C rise above the board temperature for the Pow-  
erPAK and a 43 °C rise for the standard SO-8. Referring  
to Figure 7, a 2 °C difference has minimal effect on  
MOSFET r  
with temperature (Figure 7).  
DS(on)  
On-Resistance vs. Junction Temperature  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
r
whereas a 43C difference has a significant effect  
V
I
= 10 V  
GS  
DS(on)  
= 23 A  
D
on r  
.
DS(on)  
Minimizing the thermal rise above the board tempera-  
ture by using PowerPAK has not only eased the thermal  
design but it has allowed the device to run cooler, keep  
r
low, and permits the device to handle more cur-  
DS(on)  
rent than the same MOSFET die in the standard SO-8  
package.  
CONCLUSIONS  
PowerPAK SO-8 has been shown to have the same  
thermal performance as the DPAK package while hav-  
ing the same footprint as the standard SO-8 package.  
The PowerPAK SO-8 can hold larger die approximately  
equal in size to the maximum that the DPAK can accom-  
modate implying no sacrifice in performance because of  
package limitations.  
Recommended PowerPAK SO-8 land patterns are pro-  
vided to aid in PC board layout for designs using this  
new package.  
-50  
-25  
0
25  
50  
75  
100 125 150  
T
- Junction Temperature (°C)  
J
Figure 7. MOSFET rDS(on) vs. Temperature  
A MOSFET generates internal heat due to the current  
passing through the channel. This self-heating raises  
the junction temperature of the device above that of the  
PC board to which it is mounted, causing increased  
power dissipation in the device. A major source of this  
problem lies in the large values of the junction-to-foot  
thermal resistance of the SO-8 package.  
Thermal considerations have indicated that significant  
advantages can be gained by using PowerPAK SO-8  
devices in designs where the PC board was laid out for  
the standard SO-8. Applications experimental data gave  
thermal performance data showing minimum and typical  
thermal performance in a SO-8 environment, plus infor-  
mation on the optimum thermal performance obtainable  
including spreading copper. This further emphasized the  
DPAK equivalency.  
PowerPAK SO-8 minimizes the junction-to-board ther-  
mal resistance to where the MOSFET die temperature is  
very close to the temperature of the PC board. Consider  
two devices mounted on a PC board heated to 105 °C  
by other components on the board (Figure 8).  
PowerPAK SO-8 therefore has the desired small size  
characteristics of the SO-8 combined with the attractive  
thermal characteristics of the DPAK package.  
PowerPAK SO-8  
Standard SO-8  
107 °C  
148 °C  
0.8 °C/W  
PC Board at 105 °C  
16 C/W  
Figure 8. Temperature of Devices on a PC Board  
www.vishay.com  
4
Document Number 71622  
28-Feb-06  
Application Note 826  
Vishay Siliconix  
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Dual  
0.260  
(6.61)  
0.150  
(3.81)  
0.024  
(0.61)  
0.026  
(0.66)  
0.024  
(0.61)  
0.050  
(1.27)  
0.032  
(0.82)  
0.040  
(1.02)  
Recommended Minimum Pads  
Dimensions in Inches/(mm)  
Return to Index  
www.vishay.com  
16  
Document Number: 72600  
Revision: 21-Jan-08  
Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
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Document Number: 91000  
Revision: 11-Mar-11  
www.vishay.com  
1

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