Si9122A
Vishay Siliconix
Care needs to be taken iꢁ there is a delay prior to the external
circuit ꢁeeding back to the VCC supply. To prevent excessive
power dissipation within the IC it is advisable to use an
external PNP device. ꢀ pin has been incorporated on the IC,
(REG_COMP) to provide compensation when employing the
external device. In this case the VIN pin is connected to the
base oꢁ the PNP device and controls the current, while the
REG_COMP pin determines the ꢁrequency compensation oꢁ
the circuit. The value oꢁ the REG_COMP capacitor cannot be
too big, otherwise it will slow down the response oꢁ the
pre-regulator in the case that ꢁault situations occur and
pre-regulator needs to be turned on again. To understand
the operation please reꢁer to Figure 5.
Half-Bridge and Synchronous Rectification Timing
Sequence
The PWM signal generated within the Si9122ꢀ controls the
low and high-side bridge drivers on alternative cycles. ꢀ
period oꢁ inactivity always results aꢁter initiation oꢁ the soꢁt-
start cycle until the soꢁt-start voltage reaches approximately
1.2 V and PWM controlled switching begins. The ꢁirst bridge
driver to switch is always the low-side (DL), as this allows
charging oꢁ the high-side boost capacitor.
The timing and coordination oꢁ the drives to the primary and
secondary stages is very important and shown in ꢁigure 3. It
is essential to avoid the situation where both oꢁ the
secondary MOSFETs are on when either the high or the low-
side switch are active. In this situation the transꢁormer would
eꢁꢁectively be presented with a short across the output. To
avoid this, a dedicated break-beꢁore-make circuit is included
which will generate non overlapping waveꢁorms ꢁor the
primary and the secondary drive signals. This is achieved by
a programmable timer which delays the switching on oꢁ the
primary driver relative to the switching oꢁꢁ oꢁ the related
secondary and subsequently delays the switching on oꢁ the
secondary relative to the switching oꢁꢁ oꢁ the related primary.
The soꢁt-start circuit is designed ꢁor the dc-dc converter to
start-up in an orderly manner and reduce component stress
on the IC. This ꢁeature is programmable by selecting an
external CSS. ꢀn internal 20 µꢀ current source charges CSS
ꢁrom 0 V to the ꢁinal clamped voltage oꢁ 8 V. In the event oꢁ
UVLO or shutdown, VSS will be held low (< 1 V) disabling
driver switching. To prevent oscillations, a longer soꢁt-start
time may be needed ꢁor highly capacitive loads and/or high
peak output current applications.
Reference
Typical variations oꢁ BBM times with respect to RBBM and
other operating parameters are shown on page 13 and 14.
The reꢁerence voltage oꢁ Si9122ꢀ is set at 3.3 V. The
reꢁerence voltage should be de-coupled externally with
0.1 µF capacitor. The VREF voltage is 0 V in shutdown mode
and has 50 mꢀ source capability.
Primary High- and Low-Side MOSFET Drivers
The drive voltage ꢁor the low-side MOSFET switch is
provided directly ꢁrom VCC. The high-side MOSFET however
requires the gate voltage to be enhanced above VIN. This is
achieved by bootstrapping the VCC voltage onto the LX
voltage (the high-side MOSFET source). In order to provide
the bootstrapping an external diode and capacitor are
required as shown on the application schematic. The
capacitor will charge up aꢁter the low-side driver has turned
on. The switch gate drive signals DH and DL are shown in
ꢁigure 3.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage
mode and generates a ꢁixed ꢁrequency pulse width
modulated signal to the drivers. Duty cycle is controlled over
a wide range to maintain output voltage under line and load
variation. Voltage ꢁeed ꢁorward is also included to take
account oꢁ variations in supply voltage VIN.
In the halꢁ-bridge topology requiring isolation between output
and input, the reꢁerence voltage and error ampliꢁier must be
supplied externally, usually on the secondary side. The error
inꢁormation is thus passed to the power controller through an
opto-coupling device. This inꢁormation is inverted, hence 0 V
represents the maximum duty cycle, whilst 2 V represents
minimum duty cycle. The error inꢁormation enters the IC via
pin EP, and is passed to the PWM generator via an inverting
ampliꢁier. The relationship between duty cycle and VEP is
shown in the typical characteristic Graph, duty cycle vs.
VEP 25 °C , page 11. Voltage ꢁeedꢁorward is implemented by
taking the attenuated VIN signal at VINDET and directly
modulating the duty cycle.
Secondary MOSFET Drivers
The secondary side MOSFETs are driven ꢁrom the Si9122ꢀ
via a center tapped pulse transꢁormer and inverter drivers.
The waveꢁorms ꢁrom SRH and SRL are shown in ꢁigure 3. Oꢁ
importance is the relative voltage between SRH and SRL,
i.e. that which is presented across the primary oꢁ the pulse
transꢁormer. When both potentials oꢁ SRL and SRH are
equal then by the action oꢁ the inverting drivers both
secondary MOSFETs are turned on.
Oscillator
The oscillator is designed to operate at a nominal ꢁrequency
oꢁ 500 kHz. The 500 kHz operating ꢁrequency allows the
converter to minimize the inductor and capacitor size,
improving the power density oꢁ the converter. The oscillator
and thereꢁore the switching ꢁrequency is programmable by
attaching a resistor to the ROSC pin. Under overload
conditions the oscillator ꢁrequency is reduced by the current
overload protection to enable a constant current to be
maintained into a low impedance circuit.
ꢀt start-up, i.e., once VCC is greater than VUVLO, switching is
initiated under soꢁt-start control which increases primary
switch on-times linearly ꢁrom DMIN to DMꢀX over the soꢁt-start
period. Start-up ꢁrom a VINDET power down is also initiated
under soꢁt-start control.
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Document Number: 73492
S-80038-Rev. D, 14-Jan-08
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概述
规格参数
数据手册
