SI9165_07 [VISHAY]
High Frequency 600-mA Synchronous Buck/Boost Converter; 高频600毫安同步降压/升压转换器
| 型号： | SI9165_07 |
| 厂家： | 
VISHAY |
| 描述： | High Frequency 600-mA Synchronous Buck/Boost Converter |
| 文件： | 总10页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9165
Vishay Siliconix
High Frequency 600-mA Synchronous Buck/Boost Converter
DESCRIPTION
FEATURES
•
•
•
•
Voltage Mode Control
The Si9165 provides fully integrated synchronous buck or
boost converter solution for the latest one cell Lithium Ion
cellular phones. Capable of delivering up to 600 mA of output
current at + 3.3 V, the Si9165 provides ample power for
various baseband circuits as well as for some PAs. It
combines the 2 MHz switching controller with fully integrated
high-frequency MOSFETs to deliver the smallest and most
efficient converter available today. The 2 MHz switching
frequency reduces the inductor height to new level of 2 mm
and minimizes the output capacitance requirement to less
than 10 µF with peak-to-peak output ripple as low as 10 mV.
Combined with low-gate charge high-frequency MOSFETs,
the Si9165 delivers efficiency up to 95 %. The programmable
pulse skipping mode maintains this high efficiency even
during the standby and idle modes to increase overall battery
life and talktime. In order to extract the last ounce of power
from the battery, the Si9165 is designed with 100 % duty
cycle control for buck mode. With 100 % duty cycle, the
Si9165 operates like a saturated linear regulator to deliver
the highest potential output voltage for longer talktime.
Fully Integrated MOSFET Switches
2.7 V to 6 V Input Voltage Range
RoHS
COMPLIANT
Programmable PWM/PSM Control
- Up to 600 mA Output Current at 3.3 V in PWM
- Up to 2 MHz Adjustable Switching Frequency in PWM
- Less than 200 µA Quiescent Current in PSM
•
•
•
•
Integrated UVLO and POR
Integrated Soft-Start
Synchronization
Shutdown Current < 1 µA
The Si9165 is available in lead (Pb)-free TSSOP-20 pin
packages. In order to satisfy the stringent ambient
temperature requirements, the Si9165 is rated to handle the
industrial temperature range of - 25 °C to 85 °C.
STANDARD APPLICATION CIRCUITS
V
IN
V
OUT
2.7 to 6 V
0 to 600 mA
V
IN
2.7 to 6 V
V
V
V
V
V
COIL
V
V
OUT
0 to 600 mA
S
IN/OUT
O
DD
O
COIL
MODE
V
S
PGND
FB
V
DD
IN/OUT
MODE
FB
COMP
SHUTDOWN COMP
SHUTDOWN
PWM/PSM
R
PWM/PSM
SYNC
R
OSC
OSC
REF
REF
SYNC
PGND
GND
PGND GND
Buck Configuration
Boost Configuration
Document Number: 70845
S-72058-Rev. D, 08-Oct-07
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1
Si9165
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Unit
Voltages Referenced to GND
VDD
6.5
MODE, PWM/PSM, SYNC, SD, VREF, ROSC, COMP, FB
- 0.3 V to VDD + 0.3 V
- 0.3 V to VS + 0.3 V
0.3
V
VO
PGND
Voltages Referenced to PGND
VS, VIN/OUT
6.5
V
A
COIL
- 0.4 V to VIN/OUT + 0.4 V
Peak Output Current
Continuous Output Current
Storage Temperature Range
Operating Junction Temperature
3
1
- 65 to 150
150
°C
Power Dissipation (Package)a
20-Pin TSSOP (Q Suffix)b
20-Pin TSSOP
1.0
W
Thermal Impedance (ΘJA
Notes:
)
125
°C/W
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 8.0 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Limit
Unit
V
Voltages Referenced to GND
VDD
2.7 V to 6 V V
0 V to VDD
MODE, PWM/PSM, SYNC, SD
Voltages Referenced to PGND
VS, VIN/OUT
FOSC
2.7 V to 6 V
200 kHz to 2 MHz
25 kΩ to 300 kΩ
0.1
V
ROSC
kΩ
V
REF Capacitor
µF
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
2.7 V < VDD < 6 V,
Limits
VIN/OUT = 3.3 V, VS = 3.3 V
Parameter
Reference
Symbol
Mina
Typb
Maxa
Unit
IREF = 0 A
1.268
1.280
1.3
1.3
3
1.332
1.320
VREF
Output Voltage
V
TA = 25 °C, IREF = 0
ΔVREF
VDD = 3.3 V, - 500 µA < IREF < 0
Load Regulation
Power Supply Rejection
UVLO
mV
dB
PSRR
60
VUVLO/LH
VHYS
Under Voltage Lockout (turn-on)
Hysteresis
2.3
2.4
0.1
2.5
V
VUVLOLH - VUVLOHL
Soft-Start Time
SS Time
tSS
6
ms
Mode
VIH
VIL
IL
0.7 VDD
- 1.0
Logic High
V
0.3 VDD
1.0
Logic Low
Input Current
µA
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Document Number: 70845
S-72058-Rev. D, 08-Oct-07
Si9165
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
2.7 V < VDD < 6 V,
Limits
VIN/OUT = 3.3 V, VS = 3.3 V
Parameter
Symbol
Mina
Typb
Maxa
Unit
SD, SYNC, PWM/PSM
Logic High
VIH
VIL
IL
2.4
V
Logic Low
0.8
1.0
Input Current
Oscillator
- 1.0
2
µA
FMAX
Maximum Frequency
MHz
%
Nominal 1.60 MHz, ROSC = 30 kΩ
Accuracy
- 20
75
20
Maximum Duty Cycle (Buck, Non LDO Mode)
Maximum Duty Cycle (Boost)
SYNC Range
85
65
DMAX
FSW = 2 MHz
50
FSYNC/FOSC
1.2
50
1.5
SYNC Low Pulse Width
SYNC High Pulse Width
SYNC tr, tf
50
ns
50
1
Error Amplifier
IBIAS
AVOL
VFB = 1.5 V
TA = 25 °C
Input Bias Current
Open Loop Voltage Gain
- 1
50
µA
dB
60
1.270
1.258
1.30
1.30
2
1.330
1.342
VFB
BW
IEA
FB Threshold
Unity Gain BW
Output Current
Output Current
V
MHz
mA
Source (VFB = 1.05 V), VCOMP = 0.75 V
Sink (VFB = 1.55 V), VCOMP = 0.75 V
- 3
- 1
1
3
Boost Modec
Buck Moded
Boost Modec
Buck Moded
VIN ≤ VOUT = 2.7 to 5.0 V
VIN ≥ VOUT = 2.7 to 6.0 V
VIN = 3.3 V, VOUT = 3.6 V
VIN = 3.6 V, VOUT = 2.7 V
600
600
150
150
Output Current (PWM)
IOUT
mA
Output Current (PSM)
r
r
DS(on) N-Channel
DS(on) P-Channel
130
160
300
330
rDS(on)
VS ≥ 3.3 V
mΩ
Over temperature protection
Trip Point
Rising Temperature
165
25
°C
Hysteresis
Supply Current
Normal Mode
VDD = 3.3 V, FOSC = 2 MHz
VDD = 3.3 V
500
180
750
250
1
IDD
PSM Mode
µA
VDD = 3.3 V, SD = 0 V
Shutdown Mode
Notes:
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. VIN = VDD, VOUT = VIN/OUT = VS = VO, L = 1.5 µH.
d. VIN = VDD = VS = VIN/OUT, VOUT = VO, L = 1.5 µH.
Document Number: 70845
S-72058-Rev. D, 08-Oct-07
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Si9165
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1.310
1.32
1.31
1.30
1.29
1.28
1.305
1.300
1.295
1.290
2.0
2.5
3.0
3.5
4.0
- (V)
4.5
5.0
5.5
6.0
- 50
0
50
100
150
V
DD
Temperature (°C)
VREF vs. VDD
VREF vs. Temperature
2.00
10000
1000
100
1.95
1.90
1.85
1.80
1.75
1.70
R
OSC
= 25 kΩ
- 100
- 50
0
50
100
150
10
100
1000
Temperature (°C)
Frequency vs. Temperature
R
(kΩ)
OSC
Frequency vs. ROSC
100
95
95
PWM - 2.7 V
PWM - 3.3 V
PSM - 3 V
90
90
85
85
80
PSM - 3.3 V
PSM - 2.7 V
PSM - 3.6 V
PSM - 4.2 V
PWM - 3 V
80
75
70
PWM - 3.6 V
75
70
PWM - 4.2 V
65
60
65
60
10
Load Current (mA)
Boost Mode Efficiency, VO = 3.6 V
100
1000
1
10
Load Current (mA)
Buck Mode Efficiency, VO = 2.7 V
100
1000
1
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Document Number: 70845
S-72058-Rev. D, 08-Oct-07
Si9165
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
800
250
200
150
100
50
700
600
500
400
300
200
2
3
4
5
6
7
2
3
4
5
6
7
V
DD
- (V)
V
DD
- (V)
PSM Supply Current
PWM Supply Current
PIN CONFIGURATION AND ORDERING INFORMATION
TSSOP-20
ORDERING INFORMATION
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
SD
COIL
Part Number
Temperature Range
Package
COIL
Si9165BQ-T1-E3
- 25 to 85 °C
Tape and Reel
PWM/PSM
MODE
PGND
PGND
V
V
V
IN/OUT
IN/OUT
Eval Kit
Temperature Range
Board Type
Si9165BQ
Si9165DB
- 25 to 85 °C
Surface Mount
V
V
V
IN/OUT
SYNC
S
O
GND
DD
V
R
OSC
REF
FB
COMP
Top View
PIN DESCRIPTION
Pin Number
Name
Function
1
N/C
Not Used
2
3
SD
Shuts down the IC completely and decreases current consumed by the IC to < 1 µA.
PWM/PSM Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled.
VIN/OUT
4, 5, 6
Input node for buck mode and output node for boost mode.
Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not
used, the pin must be connected to VDD, or logic high.
7
SYNC
8
GND
VREF
Low power controller ground
9
1.3 V reference. Decoupled with 0.1 µF capacitor.
10
11
12
13
FB
COMP
Rosc
VDD
Output voltage feedback connected to the inverting input of an error amplifier.
Error amplifier output for external compensation network.
External resistor to determine the switching frequency.
Input supply voltage for the analog circuitry. Input voltage range is 2.7 V to 6 V.
VO
VS
14
15
Direct output voltage sensing to control peak inductor current in PSM mode.
Supply voltage for the internal MOSFET drive circuit.
Power ground.
16, 17
18
PGND
MODE
COIL
Determines the converter topology. Connect to AGND for buck or VDD for boost.
19, 20
Inductor connection node
Document Number: 70845
S-72058-Rev. D, 08-Oct-07
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Si9165
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
V
DD
SD
V
S
V
IN/OUT
Positive
Supply
Reference
Bias
Generator
Soft-Start
Timer
UVLO
POR
OTP
Threshold
Generator
V
REF
FB
COMP
PWM
Modulator
P
N
PWM
IN
1.0 V
Ramp
PWM
EN
COIL
0.5 V
Drivers
SYNC
PWM/PSM
Select
Oscillator
OSC
PSM
R
OSC
IN
PSM
EN
C
PSM
Modulator
V
O
PWM/PSM
MODE
Negative
Return and
Substrate
GND
PGND
DETAIL OPERATIONAL DESCRIPTION
Start-Up
turned off by pulling up the gate voltage to VS potential. The
low-side N-Channel MOSFET is turned off by pulling down
the gate voltage to PGND potential. Note that the Si9165 will
always soft starts in the PWM mode regardless of the voltage
level on the PWM/PSM pin.
The UVLO circuit prevents the internal MOSFET switches
and oscillator circuit from turning on, if the voltage on VDD pin
is less than 2.5 V. With typical UVLO hysteresis of 0.1 V,
controller is continuously powered on until the VDD voltage
drops below 2.4 V. This hysteresis prevents the converter
from oscillating during the start-up phase and unintentionally
locking up the system. Once the VDD voltage exceeds the
UVLO threshold, and with no other shutdown condition
detected, an internal Power-On-Reset timer is activated
while most circuitry, except the output driver, are turned on.
After the POR timeout of about 1 ms, the internal soft-start
capacitor is allowed to charge. When the soft-start capacitor
voltage reaches 0.5 V, the PWM circuit is enabled.
Thereafter, the constant current charging the soft-start
capacitor will force the output voltage to rise gradually
without overshooting. To prevent negative undershoot, the
synchronous switch is tri-stated until the duty cycle reaches
about 10 %. In tri-state, the high-side P-Channel MOSFET is
Shutdown
The Si9165 is designed to conserve as much battery life as
possible by decreasing current consumption of IC during
normal operation as well as the shutdown mode. With logic
low level on the SD pin, current consumption of the Si9165 is
decreased to less than 1 µA by shutting off most of the
circuits. The logic high enables the controller and starts up as
described in "Start-Up" section above.
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Document Number: 70845
S-72058-Rev. D, 08-Oct-07
Si9165
Vishay Siliconix
DETAIL OPERATIONAL DESCRIPTION (CONT’D)
Over Temperature Protection
turned on. The controller will deliver 0 % duty cycle, if the
input voltage is greater than the programmed output voltage.
Because of signal propagation time and MOSFET delay/rise/
fall time, controller will not transition smoothly from minimum
controllable duty cycle to 0 % duty cycle. For example,
controller may decrease its duty cycle from 5 % to 0 %
abruptly, instead of gradual decrease you see from 75 % to
5 %.
The Si9165 is designed with over temperature protection
circuit to prevent MOSFET switches from running away. If
the temperature reaches 165 °C, internal soft-start capacitor
is discharged, shutting down the output stage. Converter
remains in the disabled mode until the temperature in the IC
decreases below 140 °C.
PWM Mode
Pulse Skipping Mode
With PWM/PSM mode pin in logic high condition, the Si9165
operates in constant frequency (PWM) mode. As the load
and line varies, switching frequency remain constant. The
switching frequency is programmed by the Rosc value as
shown by the Oscillator curve. In the PWM mode, the
synchronous drive is always enabled, even when the output
current reaches 0 A. In continuous current mode, transfer
function of the converter remain constant, providing fast
transient response. If the converter operates in
discontinuous current mode, overall loop gain decreases and
transient response time can be ten times longer than if the
converter remain in continuous current mode. This transient
response time advantage can significantly decrease the
hold-up capacitors needed on the output of dc-dc converter
to meet the transient voltage regulation. Therefore, the
PWM/PSM pin is available to dynamically program the
controller.
The gate charge losses produced from the Miller
capacitance of MOSFETs are the dominant power
dissipation parameter during light load (i.e. < 10 mA).
Therefore, less gate switching will improve overall converter
efficiency. This is exactly why the Si9165 is designed with
pulse skipping mode. If the PWM/PSM pin is connected to
logic low level, converter operates in pulse skipping
modulation (PSM) mode. During the pulse skipping mode,
quiescent current of the controller is decreased to
approximately 200 µA, instead of 500 µA during the PWM
mode. This is accomplished by turning off most of internal
control circuitry and utilizing a simple constant on-time
control with feedback comparator. The controller is designed
to have a constant on-time and a minimum off-time acting as
the feedback comparator blanking time. If the output voltage
drops below the desired level, the main switch is first turned
on and then off. If the applied on-time is insufficient to provide
the desired voltage, the controller will force another on and
off sequence, until the desired voltage is accomplished. If the
applied on-time forces the output to exceed the desired level,
as typically found in the light load condition, the converter
stays off. The excess energy is delivered to the output slowly,
forcing the converter to skip pulses as needed to maintain
regulation. The on-time and off-time are set internally based
on inductor used (1.5 µH typical), mode pin selection and
maximum load current. Wide duty cycle range can be
achieved in both buck and boost configurations. In pulse
skipping mode, synchronous rectifier drive is also disabled to
further decrease the gate charge loss, which in turn improves
overall converter efficiency.
The maximum duty cycle of the Si9165 can reach 100 % in
buck mode. This allows the system designers to extract out
the maximum stored energy from the battery. Once the
controller delivers 100 % duty cycle, converter operates like
a
saturated linear regulator. At 100 % duty cycle,
synchronous rectification is completely turned off. Up to a
maximum duty cycle of 80 % at 2 MHz switching frequency,
controller maintains perfect output voltage regulation. If the
input voltage drops below the level where the converter
requires greater than 80 % duty cycle, controller will deliver
100 % duty cycle. This instantaneous jump in duty cycle is
due to fixed BBM time, MOSFET delay/rise/fall time, and the
internal propagational delays. In order to maintain regulation,
controller might fluctuate its duty cycle back and forth from
100 % to something less than maximum duty cycle while the
converter is operating in this input voltage range. If the input
voltage drops further, controller will remain on 100 %. If the
input voltage increases to a point where it requires less than
80 % duty cycle, synchronous rectification is once again
activated.
Reference
The reference voltage of the Si9165 is set at 1.3 V. The
reference voltage is internally connected to the non-inverting
inputs of the error amplifier. The reference is decoupled with
0.1 µF capacitor.
The maximum duty cycle under boost mode is internally
limited to 75 % to prevent inductor saturation. If the converter
is turned on for 100 % duty cycle, inductor never gets a
chance to discharge its energy and eventually saturates. In
boost mode, synchronous rectifier is always turned on for
minimum or greater duration as long as the switch has been
Document Number: 70845
S-72058-Rev. D, 08-Oct-07
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Si9165
Vishay Siliconix
DETAIL OPERATIONAL DESCRIPTION (CONT’D)
Error Amplifier
Output MOSFET Stage
The error amplifier gain-bandwidth product and slew rate is
critical parameters which determines the transient response
of converter. The transient response is function of both small
and large signal response. The small signal is the converter
closed loop bandwidth and phase margin while the large
signal is determined by the error amplifier dv/dt and the
inductor di/dt slew rate. Besides the inductance value, error
amplifier determines the converter response time. In order to
minimize the response time, the Si9165 is designed with 2
MHz error amplifier gain-bandwidth product to generate the
widest converter bandwidth and 3.5 V/µs slew rate for ultra-
fast large signal response.
The high- and low-side switches are integrated to provide
optimum performance and to minimize the overall converter
size. Both, high and low-side switches are designed to
handle up to 600 mA of continuous current. The MOSFET
switches were designed to minimize the gate charge loss as
well as the conduction loss. For the high frequency
operation, switching losses can exceed conduction loss, if
the switches are designed incorrectly. Under full load,
efficiency of 90 % is accomplished with 3.6 V battery voltage
in both buck and boost modes (+ 2.7 V output voltage for
buck mode and + 5 V output voltage for boost mode).
Oscillator
The oscillator is designed to operate up to 2 MHz minimal.
The 2 MHz operating frequency allows the converter to
minimize the inductor and capacitor size, improving the
power density of the converter. Even with 2 MHz switching
frequency, quiescent current is only 500 µA with unique
power saving circuit design. The switching frequency is
easily programmed by attaching a resistor to ROSC pin. See
oscillator frequency versus ROSC curve to select the proper
values for desired operating frequency. The tolerance on the
operating frequency is 20 % with 1 % tolerance resistors.
Synchronization
The synchronization to external clock is easily accomplished
by connecting the external clock into the SYNC pin. A logic
high to low transition synchronizes the clock. The external
clock frequency must be within 1.2 to 1.5 times the internal
clock frequency.
Break-Before-Make Timing
A proper BBM time is essential in order to prevent shoot-
through current and maintain high efficiency. The break-
before-make time is set internally at 20 ns at VS = 3.6 V. The
high and low-side MOSFET drain voltages are monitored
and when the drain voltage reaches the 1.75 V below or
above its initial starting voltage, 20 ns BBM time is set before
the other switch turns on. The maximum controllable duty
cycle is limited by the BBM time. Since the BBM time is fixed,
maximum controllable duty cycle will vary depending on the
switching frequency.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?70845.
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Document Number: 70845
S-72058-Rev. D, 08-Oct-07
Package Information
Vishay Siliconix
TSSOP: 20-LEAD (POWER IC ONLY)
B
D
4X
N
0.20
C
H
A−B
A−B
D
D
0.20
2X N/2 TIPS
E
1
E
M
bbb
C
A−B
D
b
9
ꢀ
0.05
C
A
2
E/2
A
C
1
2 3
aaa
C
H
A
1
e
1.00 DIA.
SEATING
PLANE
1.00
A
D
(14_)
SIDE VIEW
MILLIMETERS
Dim
Min
—
Nom
—
Max
1.10
0.15
0.95
0.25
A
A1
A2
aaa
b
b1
bbb
c
c1
D
E
E1
e
L
PARTING
LINE
0.05
0.85
—
+
+
0.90
0.076
−
H
0.19
0.19
0.30
0.25
6
L
(∝)
0.22
0.10
−
c
1.00
B
B
0.09
0.09
0.20
0.16
(14_)
0.127
6.50 BSC
6.40 BSC
4.40
0.65 BSC
0.60
20
DETAIL ‘A’
(SCALE: 30/1)
(VIEW ROTATED 90_ C.W.)
4.30
0.50
4.50
0.70
C
L
N
4.2
P
3.0
P1
∝
0_
—
8_
e/2
ECN: S-40082—Rev. A, 02-Feb-04
DWG: 5923
SEE
DETAIL ‘A’
X
X = A and B
END VIEW
LEAD SIDES
TOP VIEW
Document Number: 72818
28-Jan-04
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1
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damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to
obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 11-Mar-11
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