SI9185DMP-29-T1 [VISHAY]
Micropower 500-mA CMOS LDO Regulator; 微功耗500 mA的CMOS LDO稳压器
| 型号： | SI9185DMP-29-T1 |
| 厂家： | 
VISHAY |
| 描述： | Micropower 500-mA CMOS LDO Regulator |
| 文件： | 总12页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9185
Vishay Siliconix
Micropower 500-mA CMOS LDO Regulator
With Error Flag/Power-On-Reset
FEATURES
D Input Voltage 2 V to 6 V
D Other Output Voltages Available by Special Order
D Low 150-mV Dropout at 500-mA Load
D Guaranteed 500-mA Output Current
D 1.1-W Power Dissipation
D Thin, Thermally Enhanced MLP33 PowerPAKt
Package
D Uses Low ESR Ceramic Output Capacitor
D Fast Load and Line Transient Response
D Only 100-mV(rms) Noise With Noise Bypass Capacitor
D 1-mA Maximum Shutdown Current
APPLICATIONS
D Laptop and Palm Computers
D Desktop Computers
D Built-in Short Circuit and Thermal Protection
D Out-Of-Regulation Error Flag (Power Good or POR)
D Cellular Phones
D Fixed 1.215-V, 1.5-V, 1.8-V, 2.0-V, 2.5-V, 2.8-V, 2.9-V,
3.0-V, 3.3-V, 5.0-V, or Adjustable Output Voltage
Options
D PDA, Digital Still Cameras
DESCRIPTION
The Si9185 is a 500-mA CMOS LDO (low dropout) voltage
regulator. The device features ultra low ground current and
dropout voltage to prolong battery life in portable electronics.
The Si9185 offers line/load transient response and ripple
rejection superior to that of bipolar or BiCMOS LDO regulators,
and is designed to drive lower cost ceramic, as well as
tantalum, output capacitors. An external noise bypass
capacitor connected to the device’s CNOISE pin will lower the
LDO’s output noise for low noise applications. The Si9185 also
includes an out-of-regulation error flag. If a capacitor is
connected to the device’s delay pin, the error flag output pin will
generate a delayed power-on-reset signal. The device is
guaranteed stable from maximum load current down to 0-mA
load.
The Si9185 is available in a MLP33 PowerPAK package. This
allows enhanced heat transfer to the PC board. The Si9185 is
specified to operate over the industrial temperature range of
–40_C to +85_C.
TYPICAL APPLICATIONS CIRCUITS
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
C
C
SD
SD
NOISE
NOISE
DELAY
ERROR
DELAY
ERROR
GND SENSE/ADJ
GND SENSE/ADJ
V
OUT
V
IN
V
OUT
V
IN
V
OUT
V
IN
V
IN
V
OUT
2.2 mF
GND
2.2 mF
2.2 mF
GND
2.2 mF
Si9185
Si9185
FIGURE 1. Fixed Output
FIGURE 2. Adjustable Output
1
2
3
4
8
7
6
5
SD
ON/OFF
C
NOISE
DELAY
ERROR
POR
0.1 mF
0.1 mF
1 MW
GND SENSE/ADJ
V
OUT
V
IN
V
OUT
V
IN
2.2 mF
2.2 mF
Si9185
GND
FIGURE 3. Low Noise, Full Features Application
Document Number: 71765
S-20641—Rev. B, 06-May-02
www.vishay.com
1
Si9185
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
b
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 W
IN
a
SD Input Voltage, V
Output Current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
IN
Thermal Impedance (Q
)
SD
JA
(R
Q
Q
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50_C/W
. . . . . . . . 500 mA Continuous, Short Circuit Protected
JA
OUT
(R
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4_C/W
Jc
Output Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
OUT
O(nom)
Notes
Maximum Junction Temperature, T
. . . . . . . . . . . . . . . . . . . . . . . 150_C
J(max)
a. Device mounted with all leads soldered or welded to PC board. (PC
Storage Temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C
STG
board—2” x 2”, 4-layer, FR4, 0.25 square inch spreading copper)
b. Derate 20 mW/_C above T = 25_C
ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to 6 V
Operating Ambient Temperature, T . . . . . . . . . . . . . . . . . . . . –40_C to 85_C
IN
A
Output Voltage, V
(Adjustable Version) . . . . . . . . . . . . . . . 1.215 V to 5 V
Operating Junction Temperature, T . . . . . . . . . . . . . . . . . . . –40_C to 125_C
OUT
J
R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kW to 150 kW
C
IN
= 2.2 mF, C = 2.2 mF (ceramic, X5R or X7R type) , C = 0.1 mF (ceramic)
OUT
NOISE
C
OUT
Range = 1 mF to 10 mF ("10%, x5R or x7R type)
C
IN
w C
OUT
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
–40 to 85_C
V
IN
= V
+ 1 V, I
= 1 mA
OUT(nom)
OUT
Parameter
Symbol
Tempa
Minb
Typc
Maxb
Unit
C
IN
= 2.2 mF, C = 2.2 mF, V = 1.5 V
OUT SD
Output Voltage Range
Adjustable Version
1 mA v I v 500 mA
Full
Room
Full
1.215
–1.5
5
V
1.5
V
OUT
Output Voltage Accuracy
(Fixed Versions)
% V
OUT
O(nom)
–2.5
2.5
Room
Full
1.191
1.179
1.215
1.239
1.251
Feedback Voltage (ADJ Version)
V
ADJ
V
Line Regulation
From V = V
IN
+ 1 V
OUT
Full
Full
–0.18
–0.18
0.18
0.18
(V
ADJ
v V
v 4 V)
to V + 2 V
OUT
OUT
DV
100
OUT
%/V
V
V
OUT
IN
Line Regulation (4 V V
v 5 V)
From V = 5.5 V to 6 V
IN
OUT
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
2
Si9185
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
–40 to 85_C
V
= V
+ 1 V, I
= 1 mA
IN
OUT(nom)
OUT
Parameter
Symbol
Tempa
Minb
Typc Maxb
Unit
C
= 2.2 mF, C = 2.2 mF, V = 1.5 V
OUT SD
IN
I
= 10 mA
Room
Room
Room
Full
5
20
OUT
I
= 200 mA
145
320
215
480
600
175
400
480
135
300
400
100
210
300
250
625
825
OUT
d
Dropout Voltage
(@V
w 2 V)
OUT(nom)
I
I
= 500 mA
= 200 mA
OUT
V
IN
– V
OUT
Room
Room
Full
115
250
OUT
d
Dropout Voltage
(@V
w 2.5 V)
OUT(nom)
I
I
= 500 mA
= 200 mA
OUT
Room
Room
Full
90
OUT
mV
d
Dropout Voltage
(@V w 3.3 V)
200
V
IN
V
IN
V
IN
– V
– V
– V
OUT
OUT
OUT
OUT(nom)
I
I
= 500 mA
= 200 mA
OUT
Room
Room
Full
60
OUT
d
Dropout Voltage
(@V w 5 V)
150
OUT(nom)
I
I
= 500 mA
= 200 mA
OUT
Room
Room
Full
170
415
OUT
d
Dropout Voltage
(@V t 2 V, V w 2 V)
OUT(nom)
IN
I
= 500 mA
OUT
I
= 0 mA
Room
Room
Full
150
OUT
1000
I
I
= 200 mA
= 500 mA
OUT
1500
4000
Ground Pin Current
I
mA
GND
Room
Full
2500
OUT
Shutdown Supply Current
ADJ Pin Current
I
V
= 0 V
Room
Room
Room
Room
Room
Room
Room
Room
0.1
5
1
mA
nA
IN(off)
SD
I
ADJ = 1.2 V
w 0.95 x V , t = 2 ms
OUT(nom) pw
100
ADJ
Peak Output Current
I
V
600
mA
O(peak)
OUT
w/o C
200
100
60
NOISE
BW = 50 Hz to 100 kHz
Output Noise Voltage
Ripple Rejection
e
N
mV (rms)
I
I
= 150 mA
OUT
C
= 0.1 mF
NOISE
f = 1 kHz
f = 10 kHz
60
DV
/DV
= 150 mA
dB
OUT
IN
OUT
f = 100 kHz
40
V
: V
+ 1 V to V
+ 2 V
IN
OUT(nom)
OUT(nom)
Dynamic Line Regulation
Dynamic Load Regulation
DV
Room
10
O(line)
t /t = 5 ms, I = 500 mA
R
F
OUT
mV
DV
O(load)
I
: 1 mA to 150 mA, t /t = 2 ms
Room
Room
Room
30
5
OUT
R F
w/o C
Cap
ms
NOISE
V
IN
= 4.3 V
V
OUT
Turn-On-Time
t
ON
V
OUT
= 3.3 V
C
= 0.1 mF
2
mS
NOISE
Thermal Shutdown
Thermal Shutdown Junction Temp
Thermal Hysteresis
t
Room
Room
Room
165
20
J(s/d)
_C
t
HYST
Short Circuit Current
I
V
OUT
= 0 V
800
mA
SC
Shutdown Input
V
High = Regulator ON (Rising)
Low = Regulator OFF (Falling)
Full
Full
1.5
V
IN
IH
SD Input Voltage
V
V
0.4
IL
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
3
Si9185
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
–40 to 85_C
V
= V
+ 1 V, I
= 1 mA
IN
OUT(nom)
OUT
Parameter
Symbol
Tempa
Room
Room
Full
Minb
Typc Maxb
Unit
C
= 2.2 mF, C = 2.2 mF, V = 1.5 V
OUT SD
IN
I
V
= 0 V, Regulator OFF
= 6 V, Regulator ON
0.01
IH
SD
e
SD Input Current
mA
I
V
SD
1.0
IL
Shutdown Hysteresis
V
HYST
100
mV
Error Output
Output High Leakage
I
ERROR = V
Full
Full
0.01
2
mA
OFF
OUT(nom)
g
Output Low Voltage
V
I
= 2 mA
0.4
OL
SINK
Out-of-Regulation Error Flag
Threshold Voltage (rising)
0.93 x
0.95 x
0.97 x
V
TH
Full
g
V
OUT
V
OUT
V
OUT
V
2% x
g
Hysteresis
V
Room
Room
HYST
V
OUT
Delay Pin Current Source
I
1.2
2.2
3.0
mA
DELAY
Notes
a. Room = 25_C, Full = –40 to 85_C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at V
w 2 V are measured at
OUT
V
OUT
= 3.3 V, while typical values for dropout voltage at V
< 2 V are measured at V
= 1.8 V.
OUT
OUT
d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V
differential, provided that V does not not drop below 2.0 V. When V
is less than 2.0 V, the output will be in regulation when 2.0 V – V
is
IN
OUT(nom)
OUT(nom)
greater than the dropout voltage specified.
e. The device’s shutdown pin includes a typical 6-MW internal pull-down resistor connected to ground.
f. is defined as the output voltage of the DUT at 1 mA.
V
OUT
g. The Error Output (Low) function is guaranteed for V w2.0 V.
IN
TIMING WAVEFORMS
V
IN
t
ON
V
NOM
0.95 V
NOM
V
OUT
ERROR
t
DELAY
FIGURE 4. Timing Diagram for Power-Up
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
4
Si9185
Vishay Siliconix
PIN CONFIGURATION
MLP33 PowerPAK
MLP33 PowerPAK
C
1
2
3
4
8
SD
SD
ERROR
8
7
6
5
1
2
3
4
C
NOISE
NOISE
DELAY
GND
7
6
5
ERROR
SENSE or ADJ
DELAY
GND
SENSE or ADJ
V
IN
V
OUT
V
OUT
V
IN
Exposed Pad
Top View
Bottom View
PIN DESCRIPTION
Pin Number
Name
Function
Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected
from this pin to ground.
1
2
C
NOISE
Capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (Pin
7) output. Refer to Figure 4.
DELAY
GND
3
4
5
Ground pin. Local ground for C
and C
.
NOISE
OUT
V
IN
Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground.
Output voltage. Connect C between this pin and ground.
V
OUT
OUT
For fixed output voltage versions, this pin should be connected to V
voltage version, this voltage feedback pin sets the output voltage via an external resistor divider.
(Pin 5). For adjustable output
OUT
6
SENSE or ADJ
ERROR
This open drain output is an error flag output which goes low when V drops 5% below its nominal
voltage. This pin also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.
OUT
7
8
SD
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V if unused.
IN
Exposed Pad
The die substrate is attached to the exposed pad and must be electrically connected to GND.
ORDERING INFORMATION
Part Number Marking Voltage Temperature Package
Si9185DMP-12-T1
Si9185DMP-15-T1
Si9185DMP-18-T1
Si9185DMP-20-T1
Si9185DMP-25-T1
Si9185DMP-28-T1
Si9185DMP-29-T1
Si9185DMP-30-T1
Si9185DMP-33-T1
Si9185DMP-50-T1
Si9185DMP-AD-T1
8512
8515
8518
8520
8525
8528
8529
8530
8533
8550
85AD
1.215 V
1.50 V
1.80 V
2.00 V
2.50 V
2.80 V
2.90 V
3.00 V
3.30 V
5.00 V
Adjustable
MLP33
PowerPAK
–40 to 85_C
Additional voltage options are available.
Eval Kit
Temperature Range
Board Type
Si9185DB
–40 to 85_C
Surface Mount
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
5
Si9185
Vishay Siliconix
TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED)
Dropout Voltage vs. Load Current
Dropout Characteristic
300
250
200
150
100
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
OUT
= 3.0 V
R
LOAD
= 16.5 W
0
0
100
200
300
(mA)
400
500
600
0
1
2
3
4
5
6
I
V
(V)
LOAD
IN
Dropout Voltage vs. Temperature
Dropout Voltage vs. V
OUT
300
250
200
150
100
50
400
350
300
250
200
150
100
50
I
= 500 mA
OUT
V
OUT
= 3.0 V
I
= 500 mA
OUT
I
= 200 mA
OUT
I
= 200 mA
OUT
I
= 10 mA
OUT
I
I
= 10 mA
= 0 mA
OUT
0
0
OUT
–50 –25
0
25
50
75
100 125 150
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Junction Temperature (_C)
V
OUT
Normalized Output Voltage vs. Load Current
Normalized V
vs. Temperature
OUT
0.2
0.30
0.15
I
= 1 mA
OUT
–0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0.00
–0.15
–0.30
–0.45
–0.60
–0.75
I
= 200 mA
OUT
I
= 500 mA
OUT
–40 –20
0
20
40
60
80 100 120 140
0
50 100 150 200 250 300 350 400 450 500
Load Current (mA)
Junction Temperature (_C)
Document Number: 71765
S-20641—Rev. B, 06-May-02
www.vishay.com
6
Si9185
Vishay Siliconix
TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED)
GND Current vs. Load Current
No Load GND Pin Current vs. Input Voltage
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
300
250
200
150
100
50
V
OUT
= 5 V
85_C
25_C
25_C
–40_C
0
0
50 100 150 200 250 300 350 400 450 500
Load Current (mA)
0
1
2
3
4
5
6
7
Input Voltage (V)
Power Supply Rejection
GND Pin Current vs. Temperature and Load
2500
2000
1500
1000
500
0
–20
–40
–60
–80
V
OUT
= 5 V
I
= 500 mA
C
C
= 10 mF
= 2.2 mF
= 150 mA
OUT
IN
OUT
I
LOAD
I
I
= 200 mA
= 0 mA
OUT
OUT
0
–40 –20
0
20
40
60
80 100 120 140
10
100
1000
10000
100000 1000000
Frequency (Hz)
JunctionTemperature (_C)
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
7
Si9185
Vishay Siliconix
TYPICAL WAVEFORMS
Load Transient Response-1
Load Transient Response-2
V
OUT
10 mV/div
V
OUT
10 mV/div
I
LOAD
100 mA/div
I
LOAD
100 mA/div
5.00 ms/div
5.00 ms/div
V
V
= 4.3 V, C = 2.2 mF
V
V
= 4.3 V, C = 2.2 mF
IN
IN
IN
IN
= 3.3 V, C
= 2.2 mF
= 3.3 V, C
= 2.2 mF
OUT
OUT
OUT
OUT
I
t
= 1 to 150 mA
= 2 msec
I
t
= 1 to 150 mA
= 2 msec
LOAD
rise
LOAD
rise
Load Transient Response-3
Load Transient Response-4
V
OUT
10 mV/div
V
OUT
10 mV/div
I
LOAD
100 mA/div
I
LOAD
100 mA/div
5.00 ms/div
5.00 ms/div
V
V
= 4.3 V, C = 2.2 mF
V
V
= 4.3 V, C = 2.2 mF
IN
IN
IN
IN
= 3.3 V, C
= 1.0 mF
= 3.3 V, C
= 1.0 mF
OUT
OUT
OUT
OUT
I
t
= 1 to 150 mA
= 2 msec
I
t
= 1 to 150 mA
= 2 msec
LOAD
rise
LOAD
rise
Load Transient Response-5
Load Transient Respons-6
V
OUT
V
OUT
20 mV/div
20 mV/div
I
LOAD
200 mA/div
I
LOAD
200 mA/div
V
V
= 4.3 V, C = 10 mF
V
V
= 4.3 V, C = 10 mF
IN
IN
IN
IN
10 ms/div
10 ms/div
= 3.3 V, C
= 10 mF
= 3.3 V, C
= 10 mF
OUT
OUT
OUT
OUT
I
t
= 1 to 500 mA
= 2 msec
I
t
= 1 to 500 mA
= 2 msec
LOAD
rise
LOAD
rise
Document Number: 71765
S-20641—Rev. B, 06-May-02
www.vishay.com
8
Si9185
Vishay Siliconix
TYPICAL WAVEFORMS
Line Transient Response-1
Line Transient Respons-2
V
OUT
1 V/div
V
IN
2 V/div
V
OUT
10 mV/div
5.00 ms/div
5.00 ms/div
V
V
= 4.3 to 5.3 V
= 3.3 V
V
= 5.3 to 4.3 V
INSTEP
INSTEP
OUT
V
OUT
= 3.3 V
C
C
= 2.2 mF
= 10 mF
C
= 2.2 mF
OUT
= 10 mF
OUT
IN
C
IN
I
t
= 500 mA
= 5 msec
I
= 500 mA
LOAD
rise
LOAD
t = 5 msec
fall
Turn-On Sequence
Turn-Off Sequence
V
IN
CH-3 2 V/div
V
IN
2 V/div
V
OUT
CH-1 2 V/div
V
OUT
2 V/div
C
C
delay
2 V/div
delay
CH-4 2 V/div
ERROR 2 V/div
ERROR
CH-2 2 V/div
10.00 ms/div
5.00 ms/div
V
V
= 4.2 V
V
V
= 4.2 V
IN
IN
= 3.3 V
= 3.3 V
OUT
OUT
C
C
= 0.1 mF
C
C
= 0.1 mF
delay
delay
= 0.1 mF
= 0.1 mF
NOISE
NOISE
I
= 350 mA
I
= 350 mA
LOAD
LOAD
Output Noise
Noise Spectrum
10.0
Ǹ
mVń Hz
500 mV/div
0.01
100 Hz
1 ms/div
1 MHz
V
V
= 4.2 V
V
V
C
= 4.1 V
IN
IN
= 3.3 V
= 3.3 V/10 mA
= 0.1 mF
OUT
OUT
I
= 150 mA
OUT
NOISE
C
NOISE
= 0.1 mF
BW = 10 Hz to 1 MHz
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
9
Si9185
Vishay Siliconix
BLOCK DIAGRAM
SENSE
C
1
NOISE
6
4
8
V
IN
SD
+
–
RFB2
To V
IN
5
V
OUT
60 mV
6 MW
2 mA
+
RFB1
2
7
+
–
DELAY
ERROR
+
–
1.215 V
+
V
REF
–
3
GND
FIGURE 5.
DETAILED DESCRIPTION
The Si9185 is a low drop out, low quiescent current, and very
linear regulator family with very fast transient response. It is
primarily designed for battery powered applications where
battery run time is at a premium. The low quiescent current
allows extended standby time while low drop out voltage
enables the system to fully utilize battery power before
recharge. The Si9185 is a very fast regulator with bandwidth
exceeding 50 kHz while maintaining low quiescent current at
light load conditions. With this bandwidth, the Si9185 is the
fastest LDO available today. The Si9185 is stable with any
output capacitor type from 1 mF to 10.0 mF. However, X5R or
X7R ceramic capacitors are recommended for best output
noise and transient performance.
required that the equivalent impedance (source impedance,
wire, and trace impedance in parallel with input bypass
capacitor impedance) must be smaller than the input
impedance of the Si9185 for stable operation. When the
source impedance, wire, and trace impedance are unknown,
it is recommended that an input bypass capacitor be used of
a value that is equal to or greater than the output capacitor.
VOUT
VOUT is the output voltage of the regulator. Connect a bypass
capacitor from VOUT to ground. The output capacitor can be
any value from 1.0 mF to 10.0 mF. A ceramic capacitor with
X5R or X7R dielectric type is recommended for best output
noise, line transient, and load transient performance.
VIN
VIN is the input supply pin. The bypass capacitor for this pin
is not critical as long as the input supply has low enough source
impedance. For practical circuits, a 1.0-mF or larger ceramic
capacitor is recommended. When the source impedance is
not low enough and/or the source is several inches from the
Si9185, then a larger input bypass capacitor is needed. It is
GND
Ground is the common ground connection for VIN and VOUT
It is also the local ground connection for CNOISE, DELAY,
SENSE or ADJ, and SD.
.
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
10
Si9185
Vishay Siliconix
SENSE or ADJ
Safe Operating Area
The ability of the Si9185 to supply current is ultimately
dependent on the junction temperature of the pass device.
Junction temperature is in turn dependent on power
dissipation in the pass device, the thermal resistance of the
package and the circuit board, and the ambient temperature.
The power dissipation is defined as
SENSE is used to sense the output voltage. Connect SENSE
to VOUT for the fixed voltage version. For the adjustable output
version, use a resistor divider R1 and R2, connect R1 from
VOUT to ADJ and R2 from ADJ to ground. R2 should be in the
25-kW to 150-kW range for low power consumption, while
maintaining adequate noise immunity.
PD = (VIN – VOUT) * IOUT
.
The formula below calculates the value of R1, given the
desired output voltage and the R2 value,
Junction temperature is defined as
TJ = TA + ((PD * (RθJC + RθCA)).
ǒ
ǓR2
VOUT * VADJ
R1 +
To calculate the limits of performance, these equations must
be rewritten.
VADJ
(1)
V
ADJ
is nominally 1.215 V.
SHUTDOWN (SD)
Allowable power dissipation is calculated using the equation
P
D = (TJ – TA )/ (RθJC + RθCA)
SD controls the turning on and off of the Si9185. VOUT is
guaranteed to be on when the SD pin voltage equals or is
greater than 1.5 V. VOUT is guaranteed to be off when theSD
pin voltage equals or is less than 0.4 V. During shutdown
mode, the Si9185 will draw less than 2-mA current from the
source. To automatically turn on VOUT whenever the input is
applied, tie the SD pin to VIN.
While allowable output current is calculated using the equation
IOUT = (TJ – TA )/ (RθJC + RθCA) * (VIN – VOUT).
Ratings of the Si9185 that must be observed are
TJmax = 125 _C, TAmax = 85 _C, (VIN – VOUT max
)
= 5.3 V, RθJC
ERROR
= 4 _C/W.
ERROR is an open drain output that goes low when VOUT is
less than 5% of its normal value. As with any open drain output,
an external pull up resistor is needed. When a capacitor is
connected from DELAY to GROUND, the error signal transition
from low to high is delayed (see Delay section). This delayed
error signal can be used as the power-on reset signal for the
application system. (Refer to Figure 4.)
The value of RθCA is dependent on the PC board used. The
value of RθCA for the board used in device characterization is
approximately 46 _C/W.
Figure 6 shows the performance limits graphically for the
Si9185 mounted on the circuit board used for thermal
characterization.
The ERROR pin is disconnected if not used.
0.6
0.5
DELAY
A capacitor from DELAY to GROUND sets the time delay for
ERROR going from low to high state. The time delay can be
calculated using the following formula:
T
= 0_C
A
0.4
0.3
0.2
0.1
0.0
T
A
= 25_C
ǒ
Ǔ
VADJ Cdelay
T
A
= 50_C
(2)
Tdelay
+
Idelay
T
A
= 70_C
T
A
= 85_C
The DELAY pin should be an open circuit if not used.
(V – V
)
= 5.3 V
3
IN
OUT MAX
CNOISE
0
1
2
4
5
6
For low noise application, connect a high frequency ceramic
capacitor from CNOISE to ground. A 0.01-mF or a 0.1-mF X5R
or X7R is recommended.
V
IN
– V
(V)
OUT
Figure 6.
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
11
Si9185
Vishay Siliconix
1.425
0.056
PCB Footprint and Layout Considerations
0.906
0.026
The Si9185 comes in the MLP33 PowerPAK package with an
exposed pad on the bottom to provide a low thermal
impedance path into the PC board. When the PC board layout
is designed, a copper plane, referred to as spreading copper,
is recommended to be placed under the package to which the
exposed pad is soldered. This spreading copper is the path for
the heat to move away from the package into the PC board.
With the Si9185 mounted on a four layer board measuring 2”
2”, a spreading copper area of 0.25 square inches will yield an
Rqja of 50_C/W. This allows for power dissipation in excess of
1 watt in an 80_C ambient environment.
0.650
0.026
0.325
0.013
2.245
0.088
0.396
0.016
1.426
0.056
mm
inches
2.852
0.112
Figure 7. MLP33 PowerPAK Pad Pattern
Document Number: 71765
www.vishay.com
S-20641—Rev. B, 06-May-02
12
相关型号：
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VISHAY
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