SIP825YEU [VISHAY]
5-Pin UP Reset Circuits with Watchdog Timer and Manual Reset; 5引脚复位电路，带有看门狗定时器和手动复位
| 型号： | SIP825YEU |
| 厂家： | 
VISHAY |
| 描述： | 5-Pin UP Reset Circuits with Watchdog Timer and Manual Reset |
| 文件： | 总6页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiP823/SiP824/SiP825
Vishay Siliconix
5-Pin mP Reset Circuits with Watchdog Timer and Manual Reset
FEATURES
APPLICATIONS
D Precision Power Supply Monitoring with "1.5% Accuracy
D Low Quiescent Current: 3 ꢀA max.
D Portable Intelligent Electronics
D Computers and Controllers
D Low Threshold Voltage Temperature Coefficient: 100 ppm max. D Automotive Electronics
D Guaranteed RESET Valid Dow to VCC = 1 V
D Seven Reset Threshold Options
D Small SOT23-5 Packages
D Critical ꢀ P/ꢀ C Power Supply Monitoring
D No External Components
D Power Supply Transient Immunity
DESCRIPTION
The SiP823/SiP824/SiP825 series are ꢀProcessor
supervisory circuits in a 5-pin SOT23 package, that combine
the functions of power supply and ꢀProcessor monitoring.
Specially configured options are available upon request,
allowing for further customization of reset voltage, reset
time-out, and watchdog time-out periods.
The SiP823 has a reset output that is “active low” and the
SiP824 and SiP825 have complementary outputs for both
“active high” and “active low” resets. Both output drives are
push/pull configurations.
If the power supply voltage drops, or has been, below a safe
level or the ꢀProcessor shows signs of problematic inactivity,
the circuit will generate a reset signal at it’s output.
Space saving SOT23-5 packages and low quiescent current
make this family of products ideally suited for portable battery
operated equipment.
The SiP823 and SiP825 have an input to accommodate
manual reset.
These circuits fully ignore fast negative VCC transients and
have valid reset output signals with power supply levels down
to 1 V.
Seven pre-programmed reset threshold voltage levels are
available as standard options.
PACKAGING AND PIN DEFINITION
SOT-23
SiP823
SOT-23
SOT-23
V
V
V
CC
1
2
3
5
4
1
2
3
5
4
1
2
3
5
4
RESET
GND
MR
RESET
GND
RESET
GND
CC
CC
SiP824
SiP825
RESET
RESET
WDI
WDI
MR
Top View
Top View
Top View
See page 2 for ordering and marking information.
TYPICAL APPLICATION CIRCUIT
V
CC
V
CC
V
CC
RESET
RESET
ꢀ Processor
I/O
SiP823
MR
WDI
MANUAL
RESET
GND
GND
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
1
SiP823/SiP824/SiP825
Vishay Siliconix
ORDERING INFORMATION
SiP823
SiP824
SiP825
x EU x x DT-TR1
Watchdog time-out Period
Default: 1.76 Sec
Reset time-out Period
Default: 210 mS
Threshold Voltage Options
L: 4.63 V
M: 4.38 V
T: 3.08 V
S: 2.93 V
R: 2.63 V
Z: 2.32 V
Y: 2.19 V
Please contact your local Vishay Semiconductor Sales Office for information on
customization of reset voltage, reset time-out, and watchdog time-out options.
MARKING INFORMATION
SiP823
SiP824
SiP825
SiP823LEU
SiP823MEU
SiP823TEU
SiP823SEU
SiP823REU
SiP823ZEU
SiP823YEU
AAxxx
SiP824LEU
SiP824MEU
SiP824TEU
SiP824SEU
SiP824REU
SiP824ZEU
SiP824YEU
AIxxx
SiP825LEU
SiP825MEU
SiP825TEU
SiP825SEU
SiP825REU
SiP825ZEU
SiP825YEU
ARxxx
ABxxx
ACxxx
ADxxx
AExxx
AGxxx
AHxxx
AKxxx
ALxxx
AMxxx
ANxxx
AOxxx
APxxx
ASxxx
ATxxx
AVxxx
AWxxx
AXxxx
AYxxx
Last two characters denote date code.
ABSOLUTE MAXIMUM RATINGS (T = 25_C UNLESS OTHERWISE NOTED)
A
Parameter
Symbol
Limit
Unit
Supply Voltage
V
−0.3 to 6.0
CC
V
All Other Pins
V
MAX
−0.3 to (V + 0.3)
CC
Input/Output Current, All Pins
Operating Temperature Range
Storage Temperature Range
Junction Temperature Range
I
20
mA
IN(max)
T
A
−40 to 85
−65 to 150
−40 to 125
T
stg
_C
T
J
Power Dissipation (T v 70_C)
A
P
D
310
mW
SOT-23 (Derate 4 mW/_C above 70_C)
Notes
a. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
2
SiP823/SiP824/SiP825
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
Limits
Mina
Typb
Maxa
Unit
T
A
= −40_C to 85_C, Typical Values @ T = 25_C
A
Parameter
Symbol
Supply Voltage
V
1
5.5
10.0
3.0
V
CC
V
CC
= V + 10%
TH
Supply Current (No Load)
I
ꢀ
A
CC
T
= 25_C
= 25_C
A
RESET Threshold
V
T
V
TH
−1.5%
V 1.5%
TH
V
TH
A
Threshold Hysteresis
V
0.4
40
%V
TH
TH(hys)
RESET Threshold
Temperature Coefficient
PPM/_C
Sip82_L/M/J: V t V , I
= 1.2 mA
= 0.5 mA
TH SINK
0.5
CC
TH SINK
V
OL
Sip82_R/S/T/Y/Z: V t V , I
0.4
RESET Output Voltage
RESET Output Voltage
CC
V
V
u V , I
= 0.5 mA
0.8 V
0.8 V
OH
CC
TH SOURCE
CC
V
Sip82_L/M/J: V u V , I
= 1.2 mA
= 0.5 mA
TH SINK
0.5
0.4
CC
TH SINK
V
OL
Sip82_R/S/T/Y/Z: V u V , I
CC
V
OH
V
CC
t V , I
= 0.5 mA
TH SOURCE
CC
V
to RESET Delay
T
T
V
CC
= V − 100 mV
40
ꢀ
S
CC
D1
D2
TH
RESET Time-out Period
140
210
280
mS
Watchdog Input (SiP823/SiP824)
Watchdog Time-out Period
t
1.12
50
1.76
2.40
0.7
S
WD
W
D1
Pulse Width
t
V
IL
= 0.4 V, V = 0.8 V
CC
nS
WDI
IH
V
IL
IH
IL
c
W
DI
Input Voltage
V
CC
= V + 20%
V
TH
V
0.8 V
CC
I
W
DI
= 0 V
−15
−8
W
DI
Input Current
ꢀ A
I
W
DI
= V = 5 V
8
15
IH
CC
Manual Reset Input (SiP823/SiP825)
MR Pulse Width
t
1.0
ꢀ
S
MR
V
0.7
IL
MR Input Voltage
V
CC
= V + 20%
V
TH
V
IH
0.8 V
CC
MR Noise Immunity
100
500
(Pulse Width with No RESET)
nS
MR to RESET Delay
t
MR
MR Pull-Up Resistance
80
120
kꢁ
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed or subject to production testing.
c.
W
is internally serviced within the watchdog period if W is left unconnected.
D
I
D
I
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
3
SiP823/SiP824/SiP825
Vishay Siliconix
PIN DESCRIPTION
SiP823 SiP824 SiP825
Name
Description
1
2
1
2
3
1
2
3
RESET
GND
RESET is active low. This pin has a push/pull output.
Ground
N/A
RESET
RESET is active high. This pin has a push/pull output.
Manual RESET. Active low. Pulling this pin low forces a RESET. After a low to high transition RESET
remains asserted for exactly one RESET timed period. This pin is internally pulled high. If this function is
3
N/A
4
MR
unused it can be left open or tied to V
CC.
Watchdog Input. Any transition on this pin will RESET the watchdog timer. If this pin remains high or low
for longer than the watchdog interval, a RESET is asserted. Float or tristate this pin to disable the
watchdog feature.
4
5
4
5
N/A
5
W
DI
Positive power supply. A RESET is asserted after this voltage drops below a predetermined level. After
V
CC
V
CC
rises above that level, RESET remains asserted until the end of the RESET time-out period.
TIMING DIAGRAMS
V
TH
V
TH
V
CC
t
t
D2
50%
t
t
50%
D1
RESET
RESET
50%
D2
50%
D1
Figure 1. RESET Timing Diagram
V
TH
V
DD
t
D2
t
D2
t
WD
RESET
B
WDI
Figure 2. Watchdog Timing Diagram
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
4
SiP823/SiP824/SiP825
Vishay Siliconix
DETAILED DESCRIPTION
An active signal on a microprocessor (ꢀP) RESET input starts
the ꢀP in a know state. The SiP823/SiP824/SiP825 ꢀP
supervisory circuits assert a RESET signal to prevent code
execution errors during power-up, power-down and brown-out
conditions.
RESET is asserted. The internal RESET timer is cleared by
either a RESET pulse or by toggling WDI.
WDI detects pulses as short as 50 nS. While RESET is
asserted, the timer remains cleared. As soon as RESET is
released the timer starts counting (Figure 2).
The SiP823/SiP824/SiP825 also monitors the ꢀP’s health by
checking for problematic inactivity at its WDI i input.
The watchdog timer can be disabled by leaving WDI open or
by three stating the connected driver. As soon as the WDI input
is driven either high or low, the watchdog function resumes with
the watchdog timer set to zero.
RESET Output
A RESET will be asserted for the specified RESET time-out
period (tD2), if any of three conditions are present:
WDI Input Current
The watchdog input pin (WDI) typically sources or sinks 8 ꢀA
when driven high or low.
1) VCC drops below the threshold voltage (VTH
2) The MR pin is pulled low
)
3) The watchdog timer does not detect a transition within the
watchdog interval (tWD) and the watchdog input is not left
floating.
As a result, the power dissipation at the WDI input is
independent of duty cycle. When the WDI pin is left floating or
tri-stated, the power supply current is less than 3 ꢀA.
The RESET output will remain asserted for the specified
time-out period (tD2) after:
Transient Rejection
1) VCC rises above the RESET threshold (VTH
2) MR goes high.
)
The SiP823/SiP824/SiP825 family has good immunity for
negative going transients on the VCC line.
Manual RESET Input
The smaller the duration of the transient, the larger the
amplitude can be without triggering RESET.
ꢀP based products often require a manual RESET capability,
which can be activated by manual intervention or external logic
circuitry.
The “Transient Rejection” graph below shows the relation
between transient amplitude and allowable transient duration,
without triggering RESET.
A logic low at the MR pin of the SiP823/SiP824/SiP825 asserts
a RESET signal. RESET remains asserted while MR is low
and for a period (tD2) after it returns high.
The value on the horizontal scale represents the portion of the
amplitude of the transient that is exceeding the VTH level.
MR has an internal 100-kꢁ pull-up resistor, so it can be left
floating when not activated. This input can be driven with
CMOS logic levels or with open drain devices. The input is
internally de-bounced to reject fast input transients.
RESET Output State at Low VDD
With VCC voltage on the level of MOS transistor thresholds
(t1.0 V), the RESET output of the SiP823/SiP824/SiP825
may become undefined. For outputs that are active low
(RESET), a resistor placed between RESET and GND on the
order of 100 kꢁ will ensure that the RESET output stays low
when the VCC drops below the MOS transistor threshold. In a
like manner, a resistor placed between RESET and VCC will
ensure the correct state for active high RESET outputs.
Watchdog Input (SiP823/SiP824)
The SiP823/SiP824 have a watchdog input (WDI), that
monitors the ꢀP’s activity. If the ꢀP does not toggle the
watchdog input within the watchdog time-out period (tWD),
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
5
SiP823/SiP824/SiP825
Vishay Siliconix
TYPICAL CHARACTERISTICS (T = 25_C Unless Otherwise Noted)
A
Transient Rejection
RESET Time (t ) vs. Temperature
D2
140
120
100
80
220
215
210
205
200
195
190
V
TH
= 2.63 V
60
40
20
0
−35
−5
25
55
85
115
0.01
0.1
1
Transient Amplitude (_C)
Temperature (_C)
I
vs. Temperature
RESET V
vs. Temperature
CC
TH
2.35
2.30
2.25
2.20
2.15
2.10
2.650
2.646
2.642
2.638
2.634
2.630
V
= 2.63 V
V
= 2.63 V
TH
TH
−35
−5
25
55
85
115
−35
−5
25
55
85
115
Temperature (_C)
Temperature (_C)
RESET V
vs. Temperature
OL
0.265
0.260
0.255
0.250
0.245
0.240
0.235
0.230
0.225
0.220
−35
−5
25
55
85
115
Temperature (_C)
Document Number: 72397
S-41150—Rev. B, 14-Jun-04
www.vishay.com
6
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