SIR424DP [VISHAY]
N-Channel 20-V (D-S) MOSFET; N通道20 -V （D -S ）的MOSFET
| 型号： | SIR424DP |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 20-V (D-S) MOSFET |
| 文件： | 总13页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiR424DP
Vishay Siliconix
N-Channel 20-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
ID (A)
Qg (Typ.)
Definition
TrenchFET® Power MOSFET
100 % Rg Tested
30a
30a
0.0055 at VGS = 10 V
0.0074 at VGS = 4.5 V
•
•
20
9.6 nC
• 100 % UIS Tested
Compliant to RoHS Directive 2002/95/EC
•
PowerPAK SO-8
APPLICATIONS
Buck Converters
• POL
DC/DC
S
•
6.15 mm
5.15 mm
1
D
S
2
S
3
•
G
4
D
8
D
G
7
D
6
D
5
Bottom View
S
Ordering Information:
SiR424DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Drain-Source Voltage
Gate-Source Voltage
Symbol
VDS
VGS
Limit
20
Unit
V
20
30a
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
30a
Continuous Drain Current (TJ = 150 °C)
ID
23.4b, c
18.7b, c
70
A
Pulsed Drain Current
Avalanche Current
Avalanche Energy
IDM
IAS
EAS
35
L = 0.1 mH
mJ
A
61
30a
T
T
C = 25 °C
A = 25 °C
Continuous Source-Drain Diode Current
IS
4b, c
TC = 25 °C
C = 70 °C
TA = 25 °C
TA = 70 °C
41.7
26.7
4.8b, c
3.1b, c
- 55 to 150
260
T
Maximum Power Dissipation
PD
W
TJ, Tstg
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)d, e
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambientb, f
Maximum Junction-to-Case (Drain)
Symbol
RthJA
RthJC
Typical
21
Maximum
Unit
t ≤ 10 s
Steady State
26
°C/W
2.4
3.0
Notes:
a. Based on TC = 25 °C. Package limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is
not required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 70 °C/W.
Document Number: 64830
S09-0854-Rev. A, 18-May-09
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1
SiR424DP
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
VDS
ΔVDS/TJ
ΔVGS(th)/TJ
VGS(th)
VGS = 0 V, ID = 250 µA
ID = 250 µA
Drain-Source Breakdown Voltage
20
V
V
DS Temperature Coefficient
20
mV/°C
VGS(th) Temperature Coefficient
- 5.5
VDS = VGS , ID = 250 µA
Gate-Source Threshold Voltage
Gate-Source Leakage
1
2.5
100
1
V
IGSS
VDS = 0 V, VGS
=
20 V
nA
VDS = 20 V, VGS = 0 V
DS = 20 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 10 V
VGS = 10 V, ID = 20 A
IDSS
ID(on)
RDS(on)
gfs
Zero Gate Voltage Drain Current
On-State Drain Currenta
µA
A
V
5
50
0.0046
0.0061
80
0.0055
0.0074
Drain-Source On-State Resistancea
Ω
S
VGS = 4.5 V, ID = 14 A
Forward Transconductancea
VDS = 15 V, ID = 20 A
Dynamicb
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
1250
410
175
22
V
DS = 10 V, VGS = 0 V, f = 1 MHz
pF
V
DS = 10 V, VGS = 10 V, ID = 24 A
35
15
Qg
Total Gate Charge
9.6
3.5
2.9
1.0
18
nC
Qgs
Qgd
Rg
Gate-Source Charge
VDS = 10 V, VGS = 4.5 V, ID = 24 A
Gate-Drain Charge
Gate Resistance
f = 1 MHz
0.2
2.0
30
20
40
15
15
15
40
15
Ω
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
12
V
DD = 10 V, RL = 10 Ω
ID ≅ 1.0 A, VGEN = 4.5 V, Rg = 1 Ω
Turn-Off Delay Time
23
Fall Time
10
ns
Turn-On Delay Time
9
Rise Time
10
V
DD = 10 V, RL = 10 Ω
ID ≅ 1.0 A, VGEN = 10 V, Rg = 1 Ω
Turn-Off Delay Time
23
Fall Time
7
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
IS
ISM
VSD
trr
TC = 25 °C
30
70
1.2
50
30
A
IS = 4.0 A, VGS = 0 V
0.8
25
15
13
12
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Qrr
ta
IF = 4.0 A, dI/dt = 100 A/µs, TJ = 25 °C
ns
tb
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 64830
S09-0854-Rev. A, 18-May-09
SiR424DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
70
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
GS
= 10 V thru 4 V
60
50
40
30
20
10
0
V
GS
= 3 V
T
C
= 25 °C
T
C
= 125 °C
T
C
= - 55 °C
3
0.0
0.5
1.0
1.5
2.0
0
1
2
4
V
GS
- Gate-to-Source Voltage (V)
V
DS
- Drain-to-Source Voltage (V)
Transfer Characteristics
Output Characteristics
0.012
0.009
0.006
0.003
0.000
1600
1200
800
400
0
C
iss
V
= 4.5 V
= 10 V
GS
C
oss
V
GS
C
rss
0
20
40
60
80
100
120
0
5
10
15
20
I
- Drain Current (A)
V
DS
- Drain-to-Source Voltage (V)
D
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
1.7
1.5
1.3
1.1
0.9
0.7
10
8
I
= 20 A
I
= 24 A
D
D
V
DS
= 10 V
6
V
GS
= 10 V
V
DS
= 5 V
V
DS
= 15 V
4
V
GS
= 4.5 V
2
0
- 50 - 25
0
T
25
50
75
100 125 150
0
5
10
15
20
Q
- Total Gate Charge (nC)
- Junction Temperature (°C)
g
J
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 64830
S09-0854-Rev. A, 18-May-09
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SiR424DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
10
1
0.020
0.015
0.010
0.005
0.000
T
= 25 °C
J
I
= 20 A
D
T
J
= 150 °C
T = - 50 °C
J
T
= 125 °C
= 25 °C
8
J
0.1
0.01
T
J
0.001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
1
2
3
4
5
6
7
9
10
V
SD
- Source-to-Drain Voltage (V)
V
GS
- Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.5
0.2
150
120
90
60
30
0
- 0.1
- 0.4
- 0.7
- 1.0
I
= 5 mA
D
I
= 250 µA
D
0.001
0.01
0.1
1
10
- 50 - 25
0
25
50
75
100 125 150
Time (s)
T
J
- Temperature (°C)
Single Pulse Power (Junction-to-Ambient)
Threshold Voltage
*
100
Limited by R
DS(on)
10 µs
10
1
100 µs
1 ms
10 ms
100 ms
1 s
T
= 25 °C
A
Single Pulse
0.1
10 s, DC
BVDSS Limited
0.01
0.1
1
10
100
V
DS
- Drain-to-Source Voltage (V)
* V > minimum V at which R is specified
DS(on)
GS
GS
Safe Operating Area, Junction-to-Ambient
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Document Number: 64830
S09-0854-Rev. A, 18-May-09
SiR424DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
75
60
45
Package Limited
30
15
0
0
25
50
75
100
125
150
T
C
- Case Temperature (°C)
Current Derating*
50
40
30
20
10
0
2.20
1.76
1.32
0.88
0.44
0.00
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
- Case Temperature (°C)
T
A
- Ambient Temperature (°C)
Power, Junction-to-Case
Power, Junction-to-Ambient
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 64830
S09-0854-Rev. A, 18-May-09
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SiR424DP
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Duty Cycle = 0.5
0.2
0.1
0.1
Notes:
P
DM
0.05
t
1
t
2
t
t
1
2
0.02
1. Duty Cycle, D =
2. Per Unit Base = R
= 70 °C/W
thJA
(t)
3. T - T = P
Z
JM
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
100
1000
10
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case
10
1
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?64830.
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6
Document Number: 64830
S09-0854-Rev. A, 18-May-09
Package Information
Vishay Siliconix
PowerPAK® SO-8, (SINGLE/DUAL)
L
H
E2
K
E4
W
1
1
2
3
4
Z
2
3
4
D
L1
E3
A1
Backside View of Single Pad
L
H
K
E2
E4
2
E1
E
Detail Z
1
2
3
4
D1
D2
Notes
1. Inch will govern.
E3
2
Dimensions exclusive of mold gate burrs.
Backside View of Dual Pad
3. Dimensions exclusive of mold flash and cutting burrs.
MILLIMETERS
INCHES
NOM.
0.041
DIM.
A
MIN.
0.97
0.00
0.33
0.23
5.05
4.80
3.56
1.32
NOM.
1.04
MAX.
1.12
0.05
0.51
0.33
5.26
5.00
3.91
1.68
MIN.
0.038
0.000
0.013
0.009
0.199
0.189
0.140
0.052
MAX.
0.044
0.002
0.020
0.013
0.207
0.197
0.154
0.066
A1
b
-
-
0.41
0.016
c
0.28
0.011
D
5.15
0.203
D1
D2
D3
D4
D5
E
4.90
0.193
3.76
0.148
1.50
0.059
0.57 TYP.
3.98 TYP.
6.15
0.0225 TYP.
0.157 TYP.
0.242
6.05
5.79
3.48
3.68
6.25
5.99
3.84
3.91
0.238
0.228
0.137
0.145
0.246
0.236
0.151
0.154
E1
E2
E3
E4
e
5.89
0.232
3.66
0.144
3.78
0.149
0.75 TYP.
1.27 BSC
1.27 TYP.
-
0.030 TYP.
0.050 BSC
0.050 TYP.
-
K
K1
H
0.56
0.51
0.51
0.06
0°
-
0.022
0.020
0.020
0.002
0°
-
0.61
0.71
0.71
0.20
12°
0.024
0.028
0.028
0.008
12°
L
0.61
0.024
L1
θ
0.13
0.005
-
-
W
M
0.15
0.25
0.36
0.006
0.010
0.014
0.125 TYP.
0.005 TYP.
ECN: T10-0055-Rev. J, 15-Feb-10
DWG: 5881
Document Number: 71655
Revison: 15-Feb-10
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1
AN821
Vishay Siliconix
®
PowerPAK SO-8 Mounting and Thermal Considerations
Wharton McDaniel
MOSFETs for switching applications are now available
PowerPAK SO-8 SINGLE MOUNTING
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. In this appli-
cation note, PowerPAK’s construction is described.
Following this mounting information is presented
including land patterns and soldering profiles for max-
imum reliability. Finally, thermal and electrical perfor-
mance is discussed.
The PowerPAK single is simple to use. The pin
arrangement (drain, source, gate pins) and the pin
dimensions are the same as standard SO-8 devices
(see Figure 2). Therefore, the PowerPAK connection
pads match directly to those of the SO-8. The only dif-
ference is the extended drain connection area. To take
immediate advantage of the PowerPAK SO-8 single
devices, they can be mounted to existing SO-8 land
patterns.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the
SO-8 package (Figure 1). The PowerPAK SO-8 uti-
lizes the same footprint and the same pin-outs as the
standard SO-8. This allows PowerPAK to be substi-
tuted directly for a standard SO-8 package. Being a
leadless package, PowerPAK SO-8 utilizes the entire
SO-8 footprint, freeing space normally occupied by the
leads, and thus allowing it to hold a larger die than a
standard SO-8. In fact, this larger die is slightly larger
than a full sized DPAK die. The bottom of the die attach
pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device
is mounted on. Finally, the package height is lower
than the standard SO-8, making it an excellent choice
for applications with space constraints.
Standard SO-8
PowerPAK SO-8
Figure 2.
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Sili-
conix MOSFETs. Click on the PowerPAK SO-8 single
in the index of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight and layer stack,
experiments have found that more than about 0.25 to
2
0.5 in of additional copper (in addition to the drain
land) will yield little improvement in thermal perfor-
mance.
Figure 1. PowerPAK 1212 Devices
Document Number 71622
28-Feb-06
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1
AN821
Vishay Siliconix
PowerPAK SO-8 DUAL
For the lead (Pb)-free solder profile, see http://
www.vishay.com/doc?73257.
The pin arrangement (drain, source, gate pins) and the
pin dimensions of the PowerPAK SO-8 dual are the
same as standard SO-8 dual devices. Therefore, the
PowerPAK device connection pads match directly to
those of the SO-8. As in the single-channel package,
the only exception is the extended drain connection
area. Manufacturers can likewise take immediate
advantage of the PowerPAK SO-8 dual devices by
mounting them to existing SO-8 dual land patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
Ramp-Up Rate
+ 6 °C /Second Maximum
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK SO-8 dual package.
Temperature at 155 15 °C
120 Seconds Maximum
Temperature Above 180 °C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
70 - 180 Seconds
240 + 5/- 0 °C
20 - 40 Seconds
+ 6 °C/Second Maximum
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 3 and 4.
Figure 3. Solder Reflow Temperature Profile
10 s (max)
210 - 220 °C
3 °C(max)
4 °C/s (max)
183 °C
140 - 170 °C
50 s (max)
3 °C(max)
60 s (min)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240 °C is allowed.
Figure 3. Solder Reflow Temperatures and Time Durations
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Document Number 71622
28-Feb-06
AN821
Vishay Siliconix
THERMAL PERFORMANCE
Introduction
Because of the presence of the trough, this result sug-
gests a minimum performance improvement of 10 °C/W
by using a PowerPAK SO-8 in a standard SO-8 PC
board mount.
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθ , or the
junction-to-foot thermal resistance, Rθ . This parameter
jc
jf
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the DPAK, PowerPAK SO-8, and stan-
dard SO-8. The PowerPAK has thermal performance
equivalent to the DPAK, while having an order of magni-
tude better thermal performance over the SO-8.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no
traces running between the body of the MOSFET.
Where the standard SO-8 body is spaced away from the
pc board, allowing traces to run underneath, the Power-
PAK sits directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading cop-
per, to the drain pad to aid in conducting heat from a
device. It is helpful to have some information about the
thermal performance for a given area of spreading cop-
per.
TABLE 1.
DPAK and PowerPAK SO-8
Equivalent Steady State Performance
DPAK
PowerPAK
SO-8
Standard
SO-8
Thermal
Resistance Rθjc
1.2 °C/W
1.0 °C/W
16 °C/W
Figure 6 shows the thermal resistance of a PowerPAK
SO-8 device mounted on a 2-in. 2-in., four-layer FR-4
PC board. The two internal layers and the backside layer
are solid copper. The internal layers were chosen as
solid copper to model the large power and ground
planes common in many applications. The top layer was
cut back to a smaller area and at each step junction-to-
ambient thermal resistance measurements were taken.
The results indicate that an area above 0.3 to 0.4 square
inches of spreading copper gives no additional thermal
performance improvement. A subsequent experiment
was run where the copper on the back-side was
reduced, first to 50 % in stripes to mimic circuit traces,
and then totally removed. No significant effect was
observed.
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pat-
tern. The question then arises as to the thermal perfor-
mance of the PowerPAK device under these conditions.
A characterization was made comparing a standard SO-8
and a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The
results are shown in Figure 5.
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
R
vs. Spreading Copper
th
(0 %, 50 %, 100 % Back Copper)
60
50
56
51
46
41
36
40
Si4874DY
30
Si7446DP
20
100 %
10
0 %
50 %
0
0.0001
0.01
1
10000
100
Pulse Duration (sec)
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path
Figure 6. Spreading Copper Junction-to-Ambient Performance
Document Number 71622
28-Feb-06
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3
AN821
Vishay Siliconix
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
In any design, one must take into account the change in
Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die tem-
perature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This
is a 2 °C rise above the board temperature for the Pow-
erPAK and a 43 °C rise for the standard SO-8. Referring
to Figure 7, a 2 °C difference has minimal effect on
MOSFET r
with temperature (Figure 7).
DS(on)
On-Resistance vs. Junction Temperature
1.8
1.6
1.4
1.2
1.0
0.8
0.6
r
whereas a 43C difference has a significant effect
V
I
= 10 V
GS
DS(on)
= 23 A
D
on r
.
DS(on)
Minimizing the thermal rise above the board tempera-
ture by using PowerPAK has not only eased the thermal
design but it has allowed the device to run cooler, keep
r
low, and permits the device to handle more cur-
DS(on)
rent than the same MOSFET die in the standard SO-8
package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same
thermal performance as the DPAK package while hav-
ing the same footprint as the standard SO-8 package.
The PowerPAK SO-8 can hold larger die approximately
equal in size to the maximum that the DPAK can accom-
modate implying no sacrifice in performance because of
package limitations.
Recommended PowerPAK SO-8 land patterns are pro-
vided to aid in PC board layout for designs using this
new package.
-50
-25
0
25
50
75
100 125 150
T
- Junction Temperature (°C)
J
Figure 7. MOSFET rDS(on) vs. Temperature
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises
the junction temperature of the device above that of the
PC board to which it is mounted, causing increased
power dissipation in the device. A major source of this
problem lies in the large values of the junction-to-foot
thermal resistance of the SO-8 package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and typical
thermal performance in a SO-8 environment, plus infor-
mation on the optimum thermal performance obtainable
including spreading copper. This further emphasized the
DPAK equivalency.
PowerPAK SO-8 minimizes the junction-to-board ther-
mal resistance to where the MOSFET die temperature is
very close to the temperature of the PC board. Consider
two devices mounted on a PC board heated to 105 °C
by other components on the board (Figure 8).
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
PowerPAK SO-8
Standard SO-8
107 °C
148 °C
0.8 °C/W
PC Board at 105 °C
16 C/W
Figure 8. Temperature of Devices on a PC Board
www.vishay.com
4
Document Number 71622
28-Feb-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
0.260
(6.61)
0.150
(3.81)
0.024
(0.61)
0.026
(0.66)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72599
Revision: 21-Jan-08
www.vishay.com
15
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