SiHU5N50D-GE3 [VISHAY]
D Series Power MOSFET;型号: | SiHU5N50D-GE3 |
厂家: | VISHAY |
描述: | D Series Power MOSFET |
文件: | 总8页 (文件大小:187K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SiHU5N50D
Vishay Siliconix
www.vishay.com
D Series Power MOSFET
FEATURES
PRODUCT SUMMARY
• Optimal Design
550
VDS (V) at TJ max.
DS(on) max. at 25 °C ()
Qg (max.) (nC)
- Low Area Specific On-Resistance
- Low Input Capacitance (Ciss
R
VGS = 10 V
1.5
)
20
3
- Reduced Capacitive Switching Losses
- High Body Diode Ruggedness
- Avalanche Energy Rated (UIS)
• Optimal Efficiency and Operation
- Low Cost
Q
gs (nC)
gd (nC)
Q
5
Configuration
Single
- Simple Gate Drive Circuitry
- Low Figure-of-Merit (FOM): Ron x Qg
D
- Fast Switching
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
IPAK
(TO-251)
APPLICATIONS
D
• Consumer Electronics
G
- Displays (LCD or Plasma TV)
• Server and Telecom Power Supplies
- SMPS
• Industrial
S
D
S
G
- Welding
N-Channel MOSFET
- Induction Heating
- Motor Drives
• Battery Chargers
ORDERING INFORMATION
Package
IPAK (TO-251)
SiHU5N50D-E3
SiHU5N50D-GE3
Lead (Pb)-free
Lead (Pb)-free and Halogen-free
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
Gate-Source Voltage AC (f > 1 Hz)
VDS
500
30
V
VGS
30
5.3
T
C = 25 °C
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
ID
TC =100 °C
3.4
A
Pulsed Drain Currenta
IDM
10
Linear Derating Factor
Single Pulse Avalanche Energyb
0.83
23
W/°C
mJ
W
EAS
PD
Maximum Power Dissipation
104
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dt (d)
TJ, Tstg
- 55 to + 150
24
°C
TJ = 125 °C
dV/dt
V/ns
°C
0.28
300
Soldering Recommendations (Peak Temperature)c
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 , IAS = 4.5 A.
c. 1.6 mm from case.
d. ISD ID, starting TJ = 25 °C.
S12-0690-Rev. A, 02-Apr-12
Document Number: 91492
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N50D
Vishay Siliconix
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
RthJA
TYP.
MAX.
62
UNIT
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
-
-
°C/W
RthJC
1.2
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
VDS
VDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 μA
Reference to 25 °C, ID = 250 μA
VDS = VGS, ID = 250 μA
500
-
0.58
-
-
-
V
V/°C
V
VDS Temperature Coefficient
-
3
-
-
-
-
-
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
5
VGS
=
30 V
-
100
1
nA
VDS = 500 V, VGS = 0 V
-
Zero Gate Voltage Drain Current
IDSS
μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
10
1.5
-
Drain-Source On-State Resistance
Forward Transconductancea
Dynamic
RDS(on)
gfs
VGS = 10 V
ID = 2.5 A
1.2
1.8
VDS = 20 V, ID = 2.5 A
S
Input Capacitance
Ciss
Coss
Crss
-
-
-
325
34
6
-
-
-
VGS = 0 V,
Output Capacitance
V
DS = 100 V,
f = 1 MHz
Reverse Transfer Capacitance
pF
nC
Effective Output Capacitance, Energy
Relatedb
Co(er)
Co(tr)
-
-
31
41
-
-
VDS = 0 V to 400 V, VGS = 0 V
Effective Output Capacitance, Time
Relatedc
Total Gate Charge
Qg
Qgs
Qgd
td(on)
tr
-
-
-
-
-
-
-
-
10
3
20
-
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
V
GS = 10 V
ID = 2.5 A, VDS = 400 V
5
-
12
11
14
11
1.7
24
22
28
22
-
VDD = 400 V, ID = 2.5 A
Rg = 9.1 , VGS = 10 V
ns
Turn-Off Delay Time
Fall Time
td(off)
tf
Gate Input Resistance
Drain-Source Body Diode Characteristics
Rg
f = 1 MHz, open drain
D
MOSFET symbol
showing the
integral reverse
P - N junction diode
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
IS
-
-
-
-
5
A
G
ISM
20
S
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
VSD
trr
TJ = 25 °C, IS = 4 A, VGS = 0 V
-
-
-
-
-
1.2
V
ns
μC
A
320
1.2
8
-
-
-
TJ = 25 °C, IF = IS = 2.5 A,
dI/dt = 100 A/μs, VR = 20 V
Qrr
IRRM
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
c. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
.
.
S12-0690-Rev. A, 02-Apr-12
Document Number: 91492
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N50D
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
12
3
2.5
2
TOP 15 V
14 V
TJ = 25 °C
ID = 2.5 A
13 V
12 V
9
6
3
0
11 V
10 V
9 V
1.5
1
8 V
V
GS = 10 V
7 V
6 V
0.5
0
- 60 - 40 - 20
0
20 40 60 80 100 120 140 160
0
5
10
15
20
25
30
TJ, Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
1000
8
6
4
2
0
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9.0 V
8.0 V
7.0 V
6.0 V
5.0 V
TJ = 150 °C
Ciss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
100
Coss = Cds + Cgd
Coss
10
Crss
1
0
5
10
15
20
25
30
0
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
12
24
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
9
6
3
0
16
12
8
TJ = 150 °C
4
TJ = 25 °C
0
0
3
6
9
12
15
18
0
5
10
15
20
25
VGS, Gate-to-Source Voltage (V)
Qg, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S12-0690-Rev. A, 02-Apr-12
Document Number: 91492
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N50D
Vishay Siliconix
www.vishay.com
100
10
1
6
5
4
3
2
1
TJ = 150 °C
TJ = 25 °C
VGS = 0 V
0.1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
25
50
75
100
125
150
VSD, Source-Drain Voltage (V)
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
100
625
600
575
550
525
500
475
Operation in this area
limited by R
DS(on)
10
1
100 μs
1 ms
Limited by RDS(on)
*
10 ms
0.1
0.01
T
T
= 25 °C
= 150 °C
C
J
Single Pulse
BVDSS Limited
1
10
100
1000
- 60 - 40 - 20
0
20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
TJ, Junction Temperature (°C)
Fig. 8 - Maximum Safe Operating Area
Fig. 10 - Typical Drain-to-Source Voltage vs. Temperature
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S12-0690-Rev. A, 02-Apr-12
Document Number: 91492
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N50D
Vishay Siliconix
www.vishay.com
RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
QGD
+
-
V
DD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
+
-
VDS
10 %
VGS
D.U.T.
td(on) tr
td(off) tf
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
Fig. 17 - Gate Charge Test Circuit
L
VDS
Vary tp to obtain
required IAS
D.U.T
IAS
RG
+
-
VDD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
S12-0690-Rev. A, 02-Apr-12
Document Number: 91492
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU5N50D
Vishay Siliconix
www.vishay.com
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T.
• Low leakage inductance
current transformer
-
+
-
-
+
Rg
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS = 10 Va
D.U.T. lSD waveform
D.U.T. VDS waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
ISD
Ripple ≤ 5 %
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91492.
S12-0690-Rev. A, 02-Apr-12
Document Number: 91492
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
4
3
A
E1
E
Thermal PAD
A
4
0.010
M
A B
C
0.25
c2
b4
L2
4
A
θ1
θ2
D1
4
B
C
3
Seating
plane
5
C
B
C
L3
L1
(Datum A)
L
B
A
A1
3 x b2
3 x b
c
View A - A
M
0.010
C A B
0.25
2 x e
Base
metal
5
Plating
(c)
b1, b3
Lead tip
5
c1
(b, b2)
Section B - B and C - C
MILLIMETERS
INCHES
MILLIMETERS
INCHES
MAX.
DIM.
A
MIN.
2.18
0.89
0.64
0.65
0.76
0.76
4.95
0.46
0.41
0.46
5.97
MAX.
2.39
1.14
0.89
0.79
1.14
1.04
5.46
0.61
0.56
0.86
6.22
MIN.
0.086
0.035
0.025
0.026
0.030
0.030
0.195
0.018
0.016
0.018
0.235
MAX.
0.094
0.045
0.035
0.031
0.045
0.041
0.215
0.024
0.022
0.034
0.245
DIM.
D1
E
MIN.
5.21
6.35
4.32
MAX.
MIN.
0.205
0.250
0.170
-
6.73
-
-
0.265
-
A1
b
E1
e
b1
b2
b3
b4
c
2.29 BSC
2.29 BSC
L
8.89
1.91
0.89
1.14
0'
9.65
2.29
1.27
1.52
15'
0.350
0.075
0.035
0.045
0'
0.380
0.090
0.050
0.060
15'
L1
L2
L3
θ1
θ2
c1
c2
D
25'
35'
25'
35'
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Document Number: 91362
Revision: 15-Sep-08
www.vishay.com
1
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Revision: 12-Mar-12
Document Number: 91000
1
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