EDI9G361024C20MNC [WEDC]
SRAM Module, 1MX36, 20ns, CMOS, SIMM-72;
| 型号： | EDI9G361024C20MNC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | SRAM Module, 1MX36, 20ns, CMOS, SIMM-72 静态存储器 内存集成电路 |
| 文件： | 总5页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI9G361024C
1024K x 36 Static RAM CMOS, High Speed Module
FEATURES
DESCRIPTION
The EDI9G361024C is a high speed 36Mb Static RAM module
organized as 1024K words by 36 bits. This module is constructed
from nine 1024K x 4 Static RAMs in SOJ packages on an epoxy
laminate (FR4) board.
n 1024K x 36 bit CMOS Static
n Random Access Memory
Access Times: 15, 20 and 25
Individual Byte Selects
Four chip enables (E1-E4) are used to independently enable the
four bytes. Reading or writing can be executed on individual
bytes or any combination of multiple bytes through proper use of
chip enables.
Fully Static, No Clocks
TTL Compatible I/O
n High Density Package
The EDI9G361024C is offered in a 72 lead SIMM package, which
enables 36Mb of memory to be placed in less than 1.3 square
inches of board space.
72 lead SIMM, No. 401 (Angle)
Common Data Inputs and Outputs
n Single +5V (±10%) Supply Operation
All inputs and outputs are TTL compatible and operate from a
single 5V supply. Fully asynchronous circuitry requires no clocks
or refreshing for operation and provides equal access and cycle
times for ease of use.
PIN NAMES
FIG. 1
AØ-A19
E1-E4
W
Address Inputs
Chip Enables
Write Enable
Output Enable
PIN CONFIGURATIONS AND BLOCK DIAGRAM
E4\
E3\
A17\
A16\
G\
VSS
DQ24
DQ16
DQ25
DQ17
DQ26
DQ18
DQ27
DQ19
A3
A10
A4
A11
A5
A12
VCC
A13
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
1
2
3
4
5
6
7
8
G
DQ34
DQ35
VSS
DQ32
DQ33
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
A0
DQØ-DQ35
Common Data
Input/Output
VCC
VSS
NC
Power (+5V±10%)
Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
No Connection
A0-A19
W\
G\
U1
U2
DQ0-DQ3
DQ4-DQ7
E1\
A7
A1
A8
A2
U3
DQ8-DQ11
A9
E2\
E3\
E4\
E1\
A6
DQ12
DQ4
DQ13
DQ5
DQ14
DQ6
DQ15
DQ7
VSS
W\
DQ20
DQ28
DQ21
DQ29
DQ22
DQ30
DQ23
DQ31
VSS
A18
U4
U5
DQ12-DQ15
DQ16-DQ19
U6
DQ20-DQ23
U7
U8
DQ24-DQ27
DQ28-DQ31
A15
A14
E2\
E1\
A19
NC
NC
U9
DQ32-DQ35
9G3610242C Pin Config.
9G361024C Blk Dia.
Aug. 2002 Rev. 1A
ECO #15432
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
1
EDI9G361024C
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Sym
VCC
VSS
VIH
Min
4.5
0
2.2
-0.3
Typ
5.0
0
--
--
Max
5.5
0
6.0
0.8
Units
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature, Plastic
Power Dissipation
-0.5V to 7.0V
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
11.6 Watts
VIL
Output Current
20 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels
VSS to 3.0V
5ns
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
1.5V
1TTL, CL = 30pF
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
DC ELECTRICAL CHARACTERISTICS
Parameter
Sym
ICC1
ICC2
ICC3
Conditions
W, E = VIL, II/O = 0mA, Min Cycle
E > VIH, VIN < VIL or VIN > VIH
E > VCC-0.2V
VIN > VCC-0.2V or VIN < 0.2V
VIN = 0V to VCC
Min
Typ
Max
1440
540
90
Units
mA
mA
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
CMOS
Input Leakage Current
Output Leakage Current
Output High Voltage
mA
ILI
ILO
VOH
VOL
--
--
2.4
--
--
--
--
--
±80
±20
--
µA
µA
V
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
Output Low Voltage
0.4
V
*Typical: TA = 25°C, VCC = 5.0V
CAPACITANCE
TRUTH TABLE
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Address Lines
Data Lines
Chip Enable Line
Write Line
Sym
CI
CD/Q
CC
Max
60
20
20
60
Unit
E
H
L
W
X
H
L
G
X
L
Mode
Standby
Read
Write
Output
Deselect
Output
HIGH Z
DOUT
DIN
Power
ICC2/ICC3
ICC1
pF
pF
pF
pF
L
X
ICC1
CN
L
H
H
HIGH Z
ICC1
These parameters are sampled, not 100% tested.
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Aug. 2002 Rev. 1A
ECO #15432
2
EDI9G361024C
AC CHARACTERISTICS READ CYCLE
Symbol
15ns
20ns
25ns
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
JEDEC Alt.
TAVAV TRC
TAVQV TAA
TELQV TACS
TELQX TCLZ
TEHQZ TCHZ
TAVQX TOH
TGLQV TOE
TGLQX TOLZ
TGHQZ TOHZ
Min Max Min Max Min
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
15
20
25
15
15
20
20
25
25
3
3
0
3
3
0
3
3
0
7
8
7
10
8
12
10
10
8
ns
Note 1: Parameter guaranteed, but not tested.
FIG. 2
READ CYCLE 1 - W HIGH, G, E LOW
TAVAV
A
ADDRESS 1
ADDRESS 2
TAVQX
TAVQV
Q
DATA 2
DATA 1
9G361024C Rd Cyc1
FIG. 3
READ CYCLE 2 - W HIGH
TAVAV
A
E
TAVQV
TELQV
TEHQZ
TGHQZ
TELQX
G
Q
TGLQV
TGLQX
9G361024C Rd Cyc2
Aug. 2002 Rev. 1A
ECO #15432
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
3
EDI9G361024C
AC CHARACTERISTICS WRITE CYCLE
Symbol
15ns
20ns
25ns
Parameter
Write Cycle Time
Chip Enable to End of Write
JEDEC Alt.
TAVAV TWC
TELWH TCW
TWLEH TCW
Min Max Min Max Min
Max Units
15
20
25
ns
ns
ns
12
12
15
15
20
20
Address Setup Time
Address Valid to End of Write
Write Pulse Width
TAVWL TAS
TAVEL TAS
TAVWH TAW
TAVEH TAW
TWLWH TWP
TELEH TWP
0
0
12
12
12
12
0
0
15
15
15
15
0
0
20
20
20
20
ns
ns
ns
ns
ns
ns
Write Recovery Time
Data Hold Time
TWHAX TWR
TEHAX TWR
TWHDX TDH
TEHDX TDH
0
0
3
3
0
0
3
3
0
0
0
0
ns
ns
ns
ns
Write to Output in High Z (1)
Data to Write Time
TWLQZ TWHZ
TDVWH TDW
TDVEH TDW
0
10
10
8
0
12
12
8
0
15
15
12
ns
ns
ns
Output Active from End of Write (1)
TWHQX TWLZ
3
3
3
ns
Note 1: Parameter guaranteed, but not tested.
FIG. 4
WRITE CYCLE 1 - W CONTROLLED
TAVAV
TELWH
A
E
TWHAX
TAVWH
TWLWH
W
TAVWL
TDVWH
TWHDX
DATA VALID
D
TWHQX
TWLQZ
HIGH Z
Q
9G361024C Write Cyc1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Aug. 2002 Rev. 1A
ECO #15432
4
EDI9G361024C
FIG. 5
WRITE CYCLE 2 - E CONTROLLED
TAVAV
A
TAVEL
TELEH
E
TAVEH
TEHAX
TEHDX
TWLEH
W
TDVEH
D
Q
DATA VALID
HIGH Z
9G361024C Write Cyc2
ORDERING INFORMATION
Part Number
Speed
(ns)
15
20
25
Package
No.
402
402
402
EDI9G361024C15MNC
EDI9G361024C20MNC
EDI9G361024C25MNC
PACKAGE DESCRIPTION
PACKAGE NO. 402: 72 LEAD SIMM
4.250
3.984
0.360
MAX.
0.125 DIA.
(2x)
1.045
MAX.
0.400
0.250
P1
0.250
0.050 TYP.
2.045
0.125
MIN.
0.225
MIN.
3.750
1.992
0.062 R. (2x)
P 1
9G361024C Pkg.
ALL DIMENSIONS ARE IN INCHES
Aug. 2002 Rev. 1A
ECO #15432
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
5
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