W3HG64M72EER806AD7XG [WEDC]
512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM; 512MB - 64Mx72 DDR2 SDRAM注册瓦特/ PLL ，小型VLP -DIMM
| 型号： | W3HG64M72EER806AD7XG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| 文件： | 总14页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3HG64M72EER-AD7
White Electronic Designs
ADVANCED*
512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL,
VLP Mini-DIMM
DESCRIPTION
FEATURES
The W3HG64M72EER is a 64Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory
module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
244-pin DIMM FR4 substrate.
ꢀ
244-pin, very low profile dual in-line memory
module (VLP Mini-DIMM)
ꢀ
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300*, and PC2-6400*
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Supports ECC error detection and correction
V
V
CC = VCCQ = 1.8V 0.1V
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
CCSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity option
Programmable CAS# latency (CL)
Posted CAS# additive latency (AL)
On-die termination (ODT)
Programmable burst lenghts: 4 or 8
Serial Presence Detect (SPD) with EEPROM
Auto and Self Refresh Capability (64ms: 8,192
cycle refresh)
ꢀ
ꢀ
ꢀ
ꢀ
Gold (Au) edge contacts
RoHS compliant
Single Rank
Package option
• 244 Pin Mini-DIMM
• PCB – 18.29mm (0.72")
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Contact factory for availability
December 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin Name
A0-A13
BA0,BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
ODT0
CK0,CK0#
CKE0
S0#
RAS#
CAS#
1
VREF
62
A4
123
VSS
184
VCCQ
2
3
4
5
6
7
8
9
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
RESET#
NC
63
64
VCCQ
A2
124
125
DQ4
DQ5
185
186
A3
A1
VCC
CK0
CK0#
VCC
A0
BA1
VCC
RAS#
VCCQ
S0#
VCCQ
ODT0
A13
VCC
NC
VSS
DQ36
DQ37
VSS
DM4
NC
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
VCC
VSS
VSS
NC/PAR_IN
VCC
A10/AP
BA0
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
VSS
DM0
NC
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
VSS
Data strobes
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
NC
VSS
Data strobes complement
On-die termination control
Clock Inputs, positive line
Clock Enables
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
VCC
WE#
VCCQ
CAS#
VCCQ
NC
NC
VCCQ
NC
Chip Selects
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset Input
Data Masks
SPD Power
Core Power
I/O Power
Address Input/Auto Precharge
Ground
Parity bit for the addess and control bus
Parity error found on the address and
control bus
SPD address
SPD Data Input/Output
Clock Input
No connect
Input/Output Reference
NC
NC
VSS
WE#
VSS
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
NC
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DM8
NC
VSS
CB6
CB7
VSS
NC
VCCQ
NC
RESET#
DM (0-8)
VCCSPD
VCC
VCCQ
A10/AP
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
CB0
CB1
VSS
DQS8#
DQS8
VSS
CB2
CB3
VSS
NC
VCCQ
CKE0
VCC
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5
NC
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
PAR_IN
ERR_OUT
SA0-SA2
SDA
SCL
NC
VREF
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
NC
NC
VSS
DM6
NC
SA2
NC
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7
NC
VSS
VCC
NC
NC
VCCQ
NC
NC/ERR_
OUT
VCCQ
A11
A7
VCC
DQ62
57
58
59
60
61
118
119
120
121
122
DQ58
DQ59
VSS
SA0
SA1
179
180
181
182
183
A12
A9
VCC
A8
240
241
242
243
244
DQ63
VSS
SDA
SCL
VCCSPD
A5
A6
December 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
RS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
DM/
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
RDQS
I/O0
RDQS
I/O0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM/
DM/
RDQS
I/O0
RDQS
I/O0
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM/
DM/
RDQS
I/O0
RDQS
I/O0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM/
DM/
CS# DQS DQS#
RDQS
I/O0
RDQS
I/O0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQS8
DQS8#
DM8
V
CCSPD
Serial PD
DDR SDRAMs
DM/
V
CC/VCCQ
RDQS
I/O0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
V
REF
DDR SDRAMs
DDR SDRAMs
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
V
SS
Serial PD
SCL
SDA
WP A0 A1 A2
SA0 SA1 SA2
RS0#
RBA0 - RBA1
RA0 - RA13
RRAS#
RCAS#
RWE#
ꢁ
S0# DDR2 SDRAMs
BA0 - BA1 DDR2 SDRAMs
A0 - A13 DDR2 SDRAMs
RAS# DDR2 SDRAMs
RCAS# DDR2 SDRAMs
R
S0#
ꢁ
ꢁ
E
G
I
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
ꢁ
ꢁ
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
Register
S
T
E
R
CK0
P
L
L
ꢁ WE# DDR2 SDRAMs
ꢁ
ꢁ
RCKE0
RODT0
CKE0 DDR2 SDRAMs
ODT0 DDR2 SDRAMs
CKE0
ODT0
CK0#
OE
RESET#
CK#
RST#
RESET#
CK
NOTE: All resistor values are 22 ohms 5ꢀ unless otherwise specified.
December 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Supply voltage
Symbol
VCC
VCCQ
VCCL
VREF
VTT
Min
1 .7
1 .7
Typical
1 .8
1 .8
1 .8
0.50 x VCCQ
VREF
Max
1 .9
1 .9
Unit
V
V
V
V
Notes
1
4
4
2
3
I/O Supply voltage
VCCL Supply voltage
I/O Reference voltage
I/O Termination voltage
Notes:
1 .7
1 .9
0.49 x VCCQ
VREF-0.04
0.51 x VCCQ
VREF + 0.04
V
1.
2.
V
CC and VCCQ must track each other. VCCQ must be less than or equal to VCC
.
V
REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not excedd 1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor.
3.
4.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
V
CCQ tracks with VCC; VCCL track with VCC
.
ABSOLUTE MAXIMUM DC RATINGS
Symbol
VCC
VCCQ
VCCL
VIN, VOUT
TSTG
TCASE
TOPR
Parameter
MIN
-1.0
-0.5
-0.5
-0.5
-55
0
MAX
2.3
2.3
2.3
2.3
100
85
U nit
V
V
V
V
°C
°C
°C
Voltage on VCC pin relative to VSS
Voltage on VCCQ pin relative to VSS
Voltage on VCCL pin relative to VSS
Voltage on any pin relative to VSS
Storage temperature
Device operating temperature
Operating temperature (ambient)
0
55
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM
-5
5
µA
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
IL
-5
-5
5
5
µA
µA
Output leakage current;
IOZ
DQ, DQS, DQS#
-5
5
µA
µA
0V<VOUT<VCCQ; DQs and ODT are disable
IVREF
VREF leakage current; VREF = Valid VREF level
-18
18
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Symbol
Min
Max
Unit
pF
pF
pF
pF
pF
pF
Input capacitance (A0 - A1 3, BA0 - BA1 ,RAS#,CAS#,WE#)
Input capacitance ( CKE0), (ODT0)
CIN1
CIN2
Input capacitance (CS0#)
CIN3
Input capacitance (CK0, CK0#)
CIN4
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
CIN5
COUT1
December 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature
TOPER
0°C to 85°C
°C
V
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. Forthe measurement conditions, please refer to JEDEC JESD51 .2
2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 125
-300
Max
Unit
mV
mV
Input High (Logic 1 ) Voltage
Input Low (Logic 0) Voltage
VREF + 300
VREF - 125
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
Min
VREF + 250
VREF + 200
—
Max
Unit
mV
mV
mV
AC Input High (Logic 1 ) Voltage (DDR2-400/533)
AC Input High (Logic 1) Voltage (DDR2-667)
AC Input Low (Logic 0) Voltage
—
VREF - 250
December 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V
806
Symbol Parameter
Operating one bank
Condition
667
534
403
Unit
tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is
CC
ICCO*
HIGH betCwCeen valid commands; AddressCbCus inputs are SWITCHING;
810
720
720
mA
TBD
TBD
active-precharge;
Data bus inputs are SWITCHING
IOUT = OmA; BL = 4; CL = CL(ICC); tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS
CC
CC
Operating one
ICC1* bank active-read-
precharge;
); CKE is HIGH, CS# is HIGH between valid commands; Address
MIN(I
busCinCputs are SWITCHING; Data bus inputs are SWITCHING; Data
945
855
810
mA
pattern is sames as ICC4W
.
Precharge power-
ICC2P**
All banks idle; tCK = tCK(I ); CKE is LOW; Other control and address
bus inputs are STABLE;CDCata bus inputs are FLOATING
45
450
495
315
90
45
360
405
270
90
45
315
360
225
90
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
down current;
Precharge quite
standby current;
All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control
and address bus inputs CaCre STABLE; Data bus inputs are FLOATING
ICC2Q**
Precharge standby All banks idle; tCK = tCK(I ); CKE is HIGH; CS# is HIGH; Other control
current;
and address bus inputs CaCre STABLE; Data bus inputs are SWITCHING
Fast PDN Exit
ICC2N**
All banks open; tCK = tCK(I ), CKE is LOW;
CC
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
Active power-down
current;
ICC3P**
Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
All banks open; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE
CC
CC
CC
Active standby
current;
ICC3N**
is HIGH, CS# is HIGH between valid commands; Other control and
585
495
405
990
mA
mA
TBD
TBD
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL =
0; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is HIGH, CS# is
Operating burst
write current;
CC
CC
CC
ICC4W*
1,395
1,170
HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open; Continuous burst reads; TOUT = OmA; BL = 4; CL =
CL(ICC); AL = 0; tCK = tCK(I ); tRC = tRC(I ); tRAS = tRAS MIN(I ); CKE is
Operating burst
read current;
CC
CC
CC
ICC4R*
1,575
1,305
1,035
mA
TBD
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
.
tCK = tCK(I ); Refresh command at every tRC(I ) interval; CKE is HIGH;
CC
CS# is HIGH between valid commands; OtheCrCcontrol and address bus
1,890
45
1,800
45
1,710
45
mA
mA
Burst auto refresh
current;
ICC5**
TBD
TBD
inputs are SWITCHING; Data bus inputs are SWITCHING
CK and CK# at OV; CKE < 0.2V; Other control
ICC6** Self refresh current; and address bus inputs are FLOATING; Data
bus inputs are FLOATING
Normal
All bank interleaving reads; IOUT = OmA; BL = 4; CL = CL(ICC); AL
Operating bank
ICC7* interleave read
curent;
= tRCD(I ) - 1*tCK(I ); tCK = tCK(I ); tRC = tRC(I ); tRRD = tRRD MIN(I
)
CC
CC
= 1*tCK(I ); CKE isCCHIGH; CS#CisC HIGH betwCeCen valid commands;
2,520
2,340
2,070
mA
TBD
CC
Address bus inputs are STABLE during DESELECTs; Data bus inputs
are SWITCHING
Notes:
CC specification is based on MICRON components. Other DRAM manufacturers specification may be different.
I
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
December 2005
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
AC CHARACTERISTICS
PARAMETER
806
667
534
403
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT Notes
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
ps
ps
ps
ps
tCK
tCK
ps
16, 24
16, 24
16, 24
16, 24
18
TBD
tCK (5)
3,000 8,000
TBD
Clock cycle time
tCK (4)
3,750 8,000 3,750 8,000 5,000 8,000
5,000 8,000 5,000 8,000 5,000 8,000
TBD
tCK (3)
TBD
CK high-level width
CK low-level width
Half clock period
tCH
0.45
0.45
MIN
0.55
0.55
0.45
0.45
MIN
0.55
0.55
0.45
0.45
MIN
0.55
0.55
TBD
tCL
18
TBD
tHP
19
(tCH
,
(tCH
,
(tCH
,
TBD
TBD
tCL
)
tCL
)
tCL)
DQ output access time from CK/CK#
tAC
-450
+450
-500
+500
-600
+600
ps
ps
TBD
TBD
TBD
Data-out high-impedance window from
CK/CK#
tHZ
tAC
tAC
tAC
8, 9
TBD
(MAX)
MAX
MAX
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
tLZ
tAC
tAC
tAC
tAC
tAC
tAC
ps
ps
ps
tCK
ps
ps
8, 10
TBD
TBD
TBD
TBD
TBD
TBD
(MIN) (MAX) (MIN) (MAX) (MIN) (MAX)
tDSa
300
300
100
175
0.35
350
350
100
225
0.35
400
400
150
275
0.35
7, 15,
21
TBD
tDHa
7, 15,
21
TBD
tDSb
7, 15,
21
TBD
tQHb
7, 15,
21
TBD
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access relative to DQS
tDIPW
TBD
TBD
TBD
TBD
Data hold skew factor
tQHS
340
400
450
TBD
DQ–DQS hold, DQS to first DQ to go nonvalid,
per access
tQH
tHP
-
tHP
-
tHP
-
15, 17
15, 17
TBD
tQHS
tQHS
tQHS
Data valid output window (DVW)
tDVW
tQH-
tQH-
tQH-
TBD
TBD
tDQSQ
0.35
0.35
-400
0.2
tDQSQ
0.35
0.35
-450
0.2
tDQSQ
0.35
0.35
-500
0.2
DQS input high pulse width
tDQSH
tCK
tCK
ps
TBD
TBD
TBD
TBD
DQS input low pulse width
tDQSL
TBD
DQS output access time from CK/CK#
DQS falling edge to CK rising– setup time
tDQSCK
+400
+450
+500
TBD
tDSS
tCK
TBD
TBD
TBD
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
0.2
tCK
ps
TBD
DQS–DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
240
1.1
300
1.1
350
1.1
15, 17
35
TBD
TBD
TBD
DQS read preamble
tRPRE
0.9
0.9
0.9
tCK
TBD
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
December 2005
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AC TIMING PARAMETERS (Continued)
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
AC CHARACTERISTICS
806 665 534
403
PARAMETER
SYMBOL
tRPST
MIN
MAX
MIN
0.4
0
MAX
MIN
0.4
0
MAX
MIN
0.4
0
MAX
UNIT
tCK
Notes
DQS read preamble
0.6
0.6
0.6
35
TBD
TBD
tWPRES
ps
12, 13,
36
DQS write preamble setup time
TBD
TBD
DQS write preamble
DQS write postamble
tWPRE
tWPST
0.35
0.4
0.25
0.4
0.25
0.4
tCK
tCK
TBD
TBD
TBD
TBD
0.6
0.6
0.6
11
Write command to first DQS
latching transition
WL-
0.25
WL-
0.25
WL-
0.25
tDQSS
tIPW
tISa
tCK
tCK
ps
ps
ps
ps
tCK
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Address and control input
pulse width for each input
0.6
400
400
200
275
2
0.6
500
500
250
375
2
0.6
600
600
350
475
2
Address and control input
setup time
6, 21
6, 21
6, 21
6, 21
Address and control input
hold time
tIHa
Address and control input
setup time
tISb
Address and control input
hold time
tIHb
CAS# to CAS# command
delay
tCCD
tRC
Active to Active (same bank)
command
55
55
55
33
27
Active bank a to Active b bank
command
tRRD
7.5
7.5
7.5
Active to Read or Write delay
Four Bank Activate period
Active to precharge command
tRCD
tFAW
tRAS
15
37.5
40
15
37.5
40
15
37.5
40
ns
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
30
70,000
70,000
70,000
20, 33
Internal Read to precharge
command delay
tRTP
tWR
tDAL
7.5
15
7.5
15
7.5
15
ns
ns
ns
23, 27
27
TBD
TBD
TBD
TBD
TBD
TBD
Write recovery time
Auto precharge wirte recovery
and precharge time
tWR+tRP
tWR+tRP
tWR+tRP
22
Interval Write to Read
command delay
tWTR
10
7.5
10
ns
27
TBD
TBD
Precharge command period
tRP
15
15
15
ns
ns
31
31
TBD
TBD
TBD
TBD
Precharge All command period
tRPA
tRP+tCK
tRP+tCK
tRP+tCK
Load Mode command cycle
time
tMRD
2
2
2
tCK
ns
TBD
TBD
TBD
TBD
CKE low to CK,CK#
uncertainty
tDELAY
tIS+tCK+ IH
t
tIS+tCK+ IH
t
tIS+tCK+ IH
t
28
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
December 2005
Rev. 1
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ADVANCED
AC TIMING PARAMETERS (Continued)
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
AC CHARACTERISTICS
PARAMETER
806 665 534
403
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Notes
Refresh to Active or Refresh to
Refresh command interval
tRFC
105
70,000
105
70,000
105
70,000
ns
14
TBD
TBD
Average periodic refresh
interval
tREFI
tXSNR
tXSRD
200
tRFC
7.8
7.8
7.8
µs
ns
14
TBD
TBD
TBD
TBD
TBD
TBD
Exit self refresh to non-read
command
tRFC
tRFC
(MIN)+10
(MIN)+10
(MIN)+10
Exit self refresh to read
command
200
200
200
tCK
Exit self refresh timing
reference
tISXR
tIS
2
tIS
2
tIS
2
ps
6, 29
25
TBD
TBD
TBD
TBD
ODT turn-on delay
tAOND
2
2
2
tCK
tAC(MAX)
+700
tAC(MAX)
+1,000
tAC(MAX)
+1,000
ODT turn-on
tAON
tAOFD
tAOF
tAC(MIN)
2.5
tAC(MIN)
2.5
tAC(MIN)
2.5
ps
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MIN)
tAC(MIN)
tAC(MIN)
26
2x tCK
+
2x tCK
+
2x tCK +
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
ODT turn-on (power-down
mode)
tAC (MAX)
+ 1,000
tAC (MAX)
+ 1,000
tAC (MAX)
+ 1,000
tAONPD
ps
TBD
TBD
TBD
TBD
2x tCK
+
2x tCK
+
2x tCK +
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
ODT turn-off (power-down
mode)
tAC (MAX)
+ 1,000
tAC (MAX)
+ 1,000
tAC (MAX)
+ 1,000
tAOFPD
tCK
ODT to power-down entry
latency
tANPD
tAXPD
tXARD
3
8
2
3
8
2
3
8
2
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
ODT power-down exit latency
Exit active power-down to
READ command, MR[bit12=0]
Exit active power-down to
tXARDS
7-AL
6-AL
6-AL
tCK
TBD
TBD
READ command, MR[bit12=1]
Exit precharge power-down to
any non-READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
TBD
CKE minimum high/low time
tCKE
34
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
December 2005
Rev. 1
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ADVANCED
High-Z and that any signal transition within the input switching
region must follow valid input requirements. That is if DQS transi-
tions high (above VIH DC (MIN) then it must not transition low
(below VIH (DC) prior to tDQSH (MIN).
Notes
1.
2.
All voltages referenced to VSS
Tests for AC timing, ICC, and electrical AC and DC characteristics
may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for
the full voltage range specified.
12. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus turn
around.
3.
4.
Outputs measured with equivalent load:
13. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
HIGH during this time, depending on tDQSS.
VTT = VCCQ/2
25Ω
Reference
Point
Output
(VOUT)
AC timing and ICC tests may use a VIL to VIH swing of up to 1.0V
in the test environment parameter specifications are guaranteed
for the specified AC input levels under normal use conditions. The
minimum slew rate for the input signals used to test the device is
1.0V/ns for signals in the range between VIL (AC) and VIH (AC).
Slew rates less than 1.0V/ns require the timing parameters to be
derated as specified.
14. The refresh period is 64ms. This equates to an average refresh
rate of 7.8125µs. However, a REFRESH command must be
asserted at least once every 70.3µs or tRFC (MAX). To ensure
all rows of all banks are properly refreshed, 8192 REFRESH
commands must be issued every 64ms.
15. Each half-byte lane has a corresponding DQS.
16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2V/ns if measured
differentially).
5.
6.
The AC and DC input level specifications are as defined in the
SSTL_18 standard (i.e., the receiver will effectively switch as a
result of the signal crossing the AC input level and will remain in
that state as long as the signal does not ring back above [below]
the DC input LOW [HIGH] level).
17. The data valid window is derived by achieving other specifications
- tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates in direct proportion to the clock duty cycle and a practical
data valid window can be derived.
Command/Address minimum input slew rate is at 1.0V/ns.
18. MIN (tCL, tCH) refers to the smaller of the actual clock low time and
the actual clock high time as provided to the device (i.e. This value
can be greater than the minimum specification limits for tCL and
Command/Address input timing must be derated if the slew rate is
not 1.0V/ns. This is easily accommodated using tISb and the Setup
and Hold Time Derating Values table. tIS timing (tISb) is referenced
from VIH (AC) for a rising signal and VIL (AC) for a falling signal. tIH
timming (tIHb) is referenced from VIH (AC) for a rising signal and VIL
(DC) for a falling signal. The timing table also lists the tISb and tIHb
values for a 1.0V/ns slew rate; these are the “base” values.
t
CH. For example, tCL and tCH are = 50 percent of the period, less
the half period jitter [tJIT(HP)] of the clock source, and less the half
period jitter due to cross talk [tJIT(cross talk)] into the clock traces.
19. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually
applied to the device CK and CK# inputs.
7.
Data minimum input slew rate is at 1.0V/ns. Data input timing
must be derated if the slew rate is not 1.0V/ns. This is easily
accommodated if the timing is referenced from the logic trip points.
20. READs and WRITEs with auto precharge are allowed to be
issued before tRAS (MIN) is satisfied since tRAS lockout feature is
supported in DDR2 SDRAM devices.
t
V
DS timing (tDSb) is referenced from VIH (AC) for a rising signal and
IL (AC) for a falling signal. tIH timing (tIHb) is referenced from VIH
21. VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb DDR2
SDRAM data sheet for more detail.
(DC) for a risng signal and VIL (DC) for a falling signal. The timing
table lists the tDSb and tDHb values for a 1.0V/ns slew rate. If the
DQS/DQS# differential strobe feature is not enabled, timing is no
longer referenced to the crosspoint of DQS/DQS#. Data timing is
now referenced to VREF, provided the DQS slew rate is not less
than 1.0V/ns. If the DQS slew rate is less than 1.0V/ns, then data
timing is now referenced to VIH (AC) for a rising DQS and VIL (DC)
for a falling DQS.
22.
tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already
an integer, round to the next highest integer. tCK refers to the
application clock period; nWR refers to the tWR parameter stored
in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR
programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 +
(4) clocks = 8 clocks.
8.
9.
tHZ and tLZ transitions occur in the same access time windows as
23. The minimum READ to internal PRECHARGE time. This
parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) ≤ 1,
then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has
to be satisfied as well. The DDR2 SDRAM device will automatically
delay the internal PRECHARGE command until tRAS (MIN) has
been satisfied.
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (when the device output is no longer driving (tHZ) or
begins driving (tLZ).
This maximum value is derived from the referenced test load. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
24. Operating frequency is only allowed to change during self refresh
mode, precharge power-down mode, and system reset condition.
10. tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX)
condition.
25. ODT turn-on time tAON (MIN) is when the device leaves high
impedance and ODT resistance begins to turn on. ODT turn-on
time tAON (MAX) is when the ODT resistance is fully on. Both are
11. The intent of the Don’t Care state after completion of the
postamble is the DQS-driven signal should either be high, low or
measured from tAOND
.
December 2005
Rev. 1
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ADVANCED
26. ODT turn-off time tAOF (MIN) is when the device starts to turn off
ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in
high impedance. Both are measured from tAOFD
32. Value is minimum pulse width, not the number of clock
registrations.
.
33. Applicable to Read cycles only. Write cycles generally require
additional time due to Write recovery time (tWR) during arto
precharge.
27. This parameter has a two clock minimum requirement at any tCK
.
28. tDELAY is calculated from tIS + tCK + tIH so that CKE registration
LOW is guaranteed prior to CK, CK# being removed in a system
RESET condition.
34.
tCKE (MIN) of 3 clocks means CKE must be registered on three
consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of
registration. Thus, after any CKE transition, CKE may not transition
29.
tISXR is equal to tIS and is used for CKE setup time during self
refresh exit.
from its valid level during the time period of tIS + 2* tCK + tIH
.
30. No more than 4 bank ACTIVE commands may be issued in
a given tFAW (MIN) period. tRRRD (MIN) restriction still applies.
The tFAW (MIN) parameter applies to all 8 bank DDR2 devices,
regardless of the number of banks already open or closed.
35. This parameter is not referenced to a specific voltage level, but
specified when the device output is no longer driving (tRPST) or
beginning to drive (tRPRE).
36. When DQS is used single-ended, the minimum limit is reduced by
100ps.
31.
tRPA timing applies when the PRECHARGE(ALL) command is
issued, regardless of the number of banks already open or closed.
If a single-bank PRECHARGE command is issued, tRP timing
applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
December 2005
Rev. 1
11
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ADVANCED
ORDERING INFORMATION FOR AD7
Part Number
Speed/Data Rate
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
CAS Latency
tRCD
6
tRP
6
Height*
W3HG64M72EER806AD7xG**
W3HG64M72EER665AD7xG**
W3HG64M72EER534AD7xG
W3HG64M72EER403AD7xG
6
5
4
3
18.29mm (0.72")
18.29mm (0.72")
18.29mm (0.72")
18.29mm (0.72")
5
5
4
4
3
3
**Contact factory for availability.
NOTES:
• RoHS product. (“G” = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR VLP AD7
FRONT VIEW
82.127 (3.233)
81.873 (3.223)
3.80 (0.150)
MAX
1.00 (0.039) R
X2
18.45 (0.726)
18.15 (0.715)
1.80 (0.071) D
X2
10.0 (0.394)
TYP
6.0 (0.236)
TYP
1.10 (0.043)
0.90 (0.035)
0.50 (0.02) R
1.0 (0.039)
TYP
2.0 (0.079)
TYP
PIN 122
PIN 1
42.9 (1.689)
TYP
3.60 (0.142)
FULL R
78.0 (3.071)
TYP
BACK VIEW
3.80 0.10
(0.150 0.004)
1.30
(0.051)
1.00 0.05
(0.039 0.002)
Detail A
0.25
(0.010) MAX
2.55 (0.100)
3.3 (0.130)
TYP
0.60
(0.024)
0.45 0.03
(0.018 0.001)
3.6 (0.142) TYP
PIN 123
PIN 244
Detail B
33.6 (1.323)
38.4 (1.512)
TYP
TYP
3.2 (0.126)
TYP
Detail A
Detail B
Tolerances: + /- 0.13 (0.005) unless otherwise specified.
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
December 2005
Rev. 1
12
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W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
W 3 H G 64M 72 E E R xxx AD7 x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH (x8)
1.8V
REGISTERED
SPEED (Mb/s)
VLP PACKAGE 244 PIN (0.72)
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
December 2005
Rev. 1
13
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W3HG64M72EER-AD7
White Electronic Designs
ADVANCED
Document Title
512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM
Revision History
Rev #
History
Release Date Status
Rev 0
Created
September 2005
Advanced
Rev 1
December 2005
Advanced
1.1 Updated ICC and AC specs
December 2005
Rev. 1
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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