W3HG64M72EER806PD4MG [WEDC]
DDR DRAM Module, 64MX72, CMOS, ROHS COMPLIANT, SO-RDIMM-200;
| 型号： | W3HG64M72EER806PD4MG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM Module, 64MX72, CMOS, ROHS COMPLIANT, SO-RDIMM-200 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总13页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3HG64M72EER-PD4
White Electronic Designs
512MB – 64Mx72 DDR2 SDRAM REGISTERED, SO-RDIMM, w/PLL
FEATURES
DESCRIPTION
Registered 200-pin (SO-RDIMM), Small-Outline
dual in-line memory module
The W3HG64M72EER is a 64Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory
module consists of nine 64Mx8 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-RDIMM FR4 substrate.
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300,
PC2-4200 and PC2-3200
V
V
CC = VCCQ = 1.8V ±0.1V
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
CCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Multiple internal device banks for concurrent
operation
Differential clock inputs (CK, CK#)
Programmable CAS# latency (CL): 3, 4, 5, and 6*
Posted CAS# additive latency: 0, 1, 2, 3 and 4
Adjustable data-output drive strength
On-die termination (ODT)
7.8μs average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Utilizes 512Mb DDR2 SDRAM components
Auto & Self Refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
Single Rank
RoHS compliant
JEDEC approved Pin-out
Package
• 200 Pin SO-RDIMM: 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
February 2007
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
PIN CONFIGURATION
PIN NAMES
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol
Pin Name
A0-A13
Function
1
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ18
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VCC
A6
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
VSS
VSS
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
2
BA0, BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
3
DQ0
DQ4
VSS
DQ19
DQ28
VSS
A5
DQS5#
DM5
DQS5
VSS
4
A4
5
A3
Data strobes
6
DQ5
DQ1
VSS
DQ29
DQ24
VSS
VCC
7
A2
VSS
DQS0#-DQS8#
ODT0
CK,CK#
CKE0
Data strobes complement
On-die termination control
Clock inputs
8
A1
DQ46
DQ42
DQ47
DQ43
VSS
9
DQS0#
DM0
DQS0
VSS
DQ25
DM3
VSS
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A0
Clock enable input
Chip select input
A10/AP
BA1
BA0
VCC
CS0#
VSS
RAS#
Row Address Strobe
Column Address Strobe
Write Enable
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
VSS
CAS#
DQ6
DQ2
DQ7
DQ3
VSS
DQ52
DQ48
DQ53
DQ49
VSS
RAS#
WE#
VCC
WE#
RESET#
VCC
Register reset input
Core Power
VSS
CS0#
CAS#
ODT0
NC
VSS
Ground
VSS
DQ26
CB4
DQ27
CB5
VSS
VSS
SA0-SA1
SDA
SPD address
DQ12
DQ8
DQ13
DQ9
VSS
DM6
DQS6#
VSS
Serial Data Input/Output
Input/Output Reference Voltage
Data-in mask
VREF
A13
VCC
DQS6
DQ54
VSS
DM0-DM8
VCCSPD
SCL
VSS
VCC
Serial EEPROM power supply
SPD Clock Input
VSS
CB0
DM8
CB1
VSS
NC
DM1
DQS1#
VSS
CK
DQ55
DQ50
VSS
NC
No connect
NC
CK#
DQ32
VSS
DQS1
DQ14
VSS
VSS
DQ51
DQ60
VSS
CB6
DQS8#
CB7
DQS8
VSS
VSS
DQ15
DQ10
VSS
DQ36
DQ33
DQ37
DQS4#
VSS
DQ61
DQ56
VSS
DQ11
DQ20
VSS
VSS
DQ57
DM7
VSS
CB2
CKE0
CB3
NC
DQS4
DM4
VSS
DQ21
DQ16
VSS
DQ62
DQS7#
VSS
VSS
VSS
DQ17
RESET#
VSS
NC
DQ34
DQ38
DQ35
DQ39
VSS
DQS7
DQ63
DQ58
SDA
NC
VCC
DM2
DQS2#
VSS
NC
A12
VSS
A11
VSS
SCL
DQS2
DQ22
VSS
A9
DQ40
DQ44
DQ41
DQ45
DQ59
SA1
VCC
A7
VCCSPD
SA0
DQ23
A8
February 2007
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
RCS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
CS#
DQS DQS#
DM/
CS# DQS DQS#
RDQS
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM/
CS#
DQS DQS#
DM/
CS# DQS DQS#
RDQS
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM/
DM/
CS#
DQS DQS#
CS# DQS DQS#
RDQS
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM/
DM/
CS#
DQS DQS#
CS# DQS DQS#
RDQS
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
DQS8#
DM8
Serial PD
DM/
CS# DQS DQS#
RDQS
SCL
SDA
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
WP A0 A1 A2
SA0 SA1
SA2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
DDR2 SDRAM X 2
REGISTER X 2
120
CS0#
RCS0# CS# : DDR2 SDRAMs
RBA0 - RBA1 BA0-BA1 : DDR2 SDRAMs
RA0 - RA13 A0-A13 : DDR2 SDRAMs
1:2
CK
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CK
CK#
PLL
CK#
R
E
G
I
S
T
E
R
RRAS#
RCAS#
RWE#
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
RESET#**
CKE0
ODT0
RCKE0
RODT0
VCCSPD
VCC/VCCQ
VREF
Serial PD
RESET#**
RST#
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
PCK**
PCK#**
VSS
** RESET#, PCK and PCK# connect to both Registers. Other signals connect to one of two Registers.
Note: All resistor values are 22 ohms ±5% unless otherwise specified.
February 2007
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-55
-5
Max
2.3
2.3
100
5
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
V
°C
μA
Command/Address,
RAS#, CAS#, WE#,
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
IL
CK, CK#
-10
-5
10
5
μA
μA
μA
μA
DM
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
DQ, DQS, DQS#
-5
5
IVREF
-18
18
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1.7
Typical
1.8
Max
1.9
Unit
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
V
V
V
V
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.50 x VCC
VREF
0.51 x VCC
VREF+0.04
3.6
VTT
VCCSPD
-
1
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
3. CCQ of all IC's are tied to VCC
V
.
OPERATING TEMPERATURE CONDITION
Parameter
Operating Case Temperature (Commercial)
Symbol
Rating
Units
Notes
TOPER
0 to +85°C
°C
1, 2
NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 to +85°C, operation temperature range, all DRAM specification will be supported.
February 2007
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Unit
V
Input High (Logic 1) Voltage
Input High (Logic 0) Voltage
VREF + 0.125
-0.300
VCC + 0.300
VREF - 0.125
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
VREF + 0.250
-
V
AC Input High (Logic 1) Voltage
DDR2-667
VREF + 0.200
-
V
V
V
AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533
-
-
VREF - 0.250
VREF - 0.200
AC Input High (Logic 0) Voltage
DDR2-667
INPUT/OUTPUT CAPACITANCE
TA=25°C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA1,
RAS#, CAS#, WE#)
CIN1
11
12
pF
Input capacitance (CKE0), (ODT0)
Input capacitance (CS0#)
CIN2
CIN3
11
11
12
12
11
7.5
8
pF
pF
pF
pF
pF
pF
pF
Input capacitance (CK, CK#)
CIN4
10
CIN5 (665)
CIN5 (534, 403)
COUT1 (665)
COUT1 (534, 403)
6.5
6.5
6.5
6.5
Input capacitance (DM0~DM8),
(DQS0~DQS8)
7.5
8
Input capacitance (DQ0~DQ63),
(CB0~CB7)
February 2007
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
INPUT/OUTPUT CAPACITANCE
TA=25°C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA1,
RAS#, CAS#, WE#)
CIN1
pF
Input capacitance (CKE0), (ODT0)
Input capacitance (CS0#)
CIN2
CIN3
pF
pF
pF
pF
pF
pF
pF
Input capacitance (CK, CK#)
CIN4
CIN5 (665)
CIN5 (534, 403)
COUT1 (665)
COUT1 (534, 403)
Input capacitance (DM0~DM8),
(DQS0~DQS8)
Input capacitance (DQ0~DQ63),
(CB0~CB7)
Note: Based on SAMSUNG
INPUT/OUTPUT CAPACITANCE
TA=25°C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A13, BA0~BA1,
RAS#, CAS#, WE#)
CIN1
pF
Input capacitance (CKE0), (ODT0)
Input capacitance (CS0#)
CIN2
CIN3
pF
pF
pF
pF
pF
pF
pF
Input capacitance (CK, CK#)
CIN4
CIN5 (665)
CIN5 (534, 403)
Input capacitance (DM0~DM8),
(DQS0~DQS8)
C
OUT1 (665)
Input capacitance (DQ0~DQ63),
(CB0~CB7)
C
OUT1 (534, 403)
Note: Based on QIMONDA
February 2007
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
VCC = +1.8V ± 0.1V
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge current;
806
665
534
403
Units
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,265 1,220 1,220
mA
TBD
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
1,400 1,355 1,355
mA
TBD
ICC2P* Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
572
815
860
572
770
815
572
770
815
mA
mA
mA
TBD
TBD
TBD
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
770
608
770
608
770
608
mA
mA
TBD
TBD
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
995
950
950
mA
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
TBD
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
1,760 1,580 1,490
1,805 1,625 1,490
1,805 1,760 1,760
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B** Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs
Normal
72
72
72
are FLOATING; Data bus inputs are FLOATING
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
2,480 2,480 2,480
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
February 2007
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
VCC = +1.8V ± 0.1V
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge current;
806
665
534
403
Units
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
TBD
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
mA
TBD
ICC2P* Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
mA
mA
mA
TBD
TBD
TBD
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
mA
mA
TBD
TBD
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
TBD
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B** Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs
Normal
are FLOATING; Data bus inputs are FLOATING
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
Note: ICC specification is based on QIMONDA components. Other DRAM Manufacturers specification may be different.
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
February 2007
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
DDR2 SDRAM COMPONT AC TIMING PARAMETERS & SPECIFICATIONS
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL MIN
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
TBD
TBD
TBD
TBD
TBD
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
ps
Clock cycle time
TBD
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
ps
TBD
ps
CK high-level width
CK low-level width
Half clock period
Clock jitter
TBD
TBD
tCK
tCK
ps
tCL
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tHP
MIN(tCH, CL
-125
-450
t
)
MIN(tCH, CL
-125
-500
t
)
MIN(tCH, CL
-125
-600
t
)
tJIT
125
125
125
ps
DQ output access time from CK/CK#
tAC
+450
+500
+600
ps
Data-out high-impedance window from
CK/CK#
tHZ
tLZ
TBD
TBD
TBD
TBD
tAC(MAX)
tAC(MAX)
tAC(MAX)
ps
ps
Data-out low-impedance window from
CK/CK#
tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
DQ and DM input setup time relative to
DQS
tDS
tDH
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
100
225
0.35
100
225
0.35
150
275
0.35
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each
input)
tDIPW
tQHS
tQH
tCK
ps
ps
Data hold skew factor
340
400
450
DQ - DQS hold, DQS to first DQ to go
nonvalid, per access
tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
ns
tCK
tCK
ps
DQS input low pulse width
0.35
0.35
0.35
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
-400
0.2
+400
240
-450
0.2
+450
300
-500
0.2
+500
350
tCK
tCK
tDSH
0.2
0.2
0.2
DQS - DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
TBD
TBD
ps
DQS read preamble
tRPRE
tRPST
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRES
tWPRE
tWPST
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
DQS write postamble
0.6
0.6
0.6
Write command to first DQS latching
transition
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tDQSS
tIPW
TBD
TBD
TBD
TBD
tCK
tCK
Address and control input pulse width for
each input
0.6
0.6
0.6
Address and control input setup time
Address and control input hold time
Address and control input hold time
tIS
tIH
200
275
2
250
375
2
350
475
2
ps
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
tCCD
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
February 2007
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
DDR2 SDRAM COMPONT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
60
MAX
MIN
60
MAX
MIN
55
MAX
UNIT
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
tRC
TBD
tRRD
7.5
15
7.5
15
7.5
15
ns
TBD
tRCD
ns
TBD
tFAW
37.5
40
37.5
37.5
40
37.5
37.5
40
37.5
ns
TBD
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tRAS
70,000
70,000
70,000
ns
TBD
tRTP
7.5
15
7.5
15
7.5
15
ns
TBD
tWR
ns
TBD
Auto precharge write recovery + precharge
time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
TBD
TBD
Internal WRITE to READ command delay
PRECHARGE command period
tWTR
7.5
15
7.5
15
10
15
ns
ns
ns
tCK
TBD
TBD
TBD
TBD
TBD
tRP
TBD
PRECHARGE ALL command period
LOAD MODE command cycle time
tRPA
tRP+tCK
2
tRP+tCK
2
tRP+tCK
2
TBD
tMRD
TBD
tIS+tCK
tIH
tIS+tCK
tIH
tIS+tCK
tIH
CKE low to CK,CK# uncertainty
tDELAY
ns
ns
TBD
TBD
TBD
REFRESH to Active of Refresh to Refresh
command interfal
tRFC
105
70,000
7.8
105
70,000
7.8
105
70,000
7.8
TBD
Average periodic refresh interval
t
REFI
μs
TBD
TBD
TBD
TBD
tRFC(MIN)
+10
tRFC(MIN)
+10
tRFC(MIN)
+10
Exit self refresh to non-READ command
tXSNR
ns
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tISXR
tAOND
200
tIS
200
tIS
200
tIS
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
2
2
2
2
2
2
tCK
tAC(MAX)
+1000
tAC(MAX)
+1000
tAC(MAX)
+1000
ODT turn-on
tAON
tAC(MIN)
tAC(MIN)
tAC(MIN)
ps
TBD
TBD
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ps
TBD
TBD
TBD
TBD
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MIN)
tAC(MIN)
tAC(MIN)
2 x tCK
+
2 x tCK
+
2 x tCK+
tAC(MIN)
+2000
tAC(MIN)
+2000
tAC(MIN)
+2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAC(MIN)
+1000
tAC(MIN)
+1000
tAC(MIN)
+1000
ps
ps
TBD
TBD
TBD
TBD
2.5 x
2.5 x
2.5 x
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK
+
tAC(MIN)
+2000
tCK+
tAOFPD
tAC(MIN)
+1000
tAC(MIN)
+1000
tAC(MIN)
+1000
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
3
8
3
8
3
8
tCK
tCK
tCK
TBD
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
TBD
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
A Exit precharge power-down to any non-
READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
TBD
CKE minimum high/low time
tCKE
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
February 2007
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
ORDERING INFORMATION FOR PD4
Speed/Data Rate
Frequency
CAS
Latency
Part Number
tRCD
tRP
Height*
W3HG64M72EER806PD4xxG**
W3HG64M72EER665PD4xxG
W3HG64M72EER534PD4xxG
W3HG64M72EER403PD4xxG
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
6
5
4
3
6
5
4
3
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
** Consult factory for availability
NOTES:
• For part numbering interpretation, please see "part number guide" on page 10.
PACKAGE DIMENSIONS FOR PD4
3.8 (0.150)
MAX
67.75 (2.667)
67.45 (2.656)
4.10(0.161)
3.90(0.154)
(2X)
30.15 (1.187)
29.85 (1.175)
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
1.10 (0.043)
0.90 (0.035)
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
2.504 (63.60)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
Tolerances: ±0.13 (0.005) unless otherwise specified
February 2007
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
PART NUMBERING GUIDE
W 3 H G 64M 72 E E R xxx PD4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
REGISTERED
SPEED (Mb/s)
PACKAGE 200 PIN SO-RDIMM
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
Note: Consult factory for other vendor options.
G = RoHS COMPLIANT
February 2007
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG64M72EER-PD4
White Electronic Designs
Document Title
512MB – 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, SO-RDIMM
DRAM DIE OPTIONS:
• SAMSUNG: C-Die, will move to E-Die Q2'06
• QIMONDA:
Revision History
Rev #
History
Release Date Status
Rev 0
Created
February 2007
Concept
February 2007
Rev. 0
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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