WED3DG6466V7AD1I [WEDC]

DRAM,;
WED3DG6466V7AD1I
型号: WED3DG6466V7AD1I
厂家: WHITE ELECTRONIC DESIGNS CORPORATION    WHITE ELECTRONIC DESIGNS CORPORATION
描述:

DRAM,

动态存储器
文件: 总7页 (文件大小:103K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
WED3DG6466V-JD1  
-AD1  
White Electronic Designs  
PRELIMINARY*  
512MB- 64Mx64 SDRAM UNBUFFERED  
FEATURES  
DESCRIPTION  
The WED3DG6466V is a 64Mx64 synchronous  
DRAM module which consists of eight 64Mx8 SDRAM  
components in TSOP II package, and one 2K EEPROM  
in an 8 pin TSSOP package for Serial Presence Detect  
which are mounted on a 144 pin SO-DIMM multilayer  
FR4 Substrate.  
PC100 and PC133 compatible  
Burst Mode Operation  
Auto and Self Refresh capability  
LVTTL compatible inputs and outputs  
Serial Presence Detect with EEPROM  
Fully synchronous: All signals are registered on the positive  
edge of the system clock  
* This product is under development, is not qualified or characterized and is subject to  
change without notice.  
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page  
3.3V 0.3V Power Supply  
144 Pin SO-DIMM JEDEC  
Package height option:  
AD1: 27.81 mm (1.095”)  
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)  
PIN NAMES  
PINOUT  
A0 – A12  
BA0-1  
DQ0-63  
CK0, CK1  
CKE0  
CS0  
Address Input (Multiplexed)  
PIN FRONT PIN  
BACK  
VSS  
PIN FRONT PIN  
BACK  
DQ45  
DQ46  
DQ47  
VSS  
NC  
NC  
CKE0  
VCC  
CAS#  
NC  
A12  
NC  
CK1  
VSS  
NC  
PIN  
97  
99  
BACK  
DQ22  
DQ23  
VCC  
A6  
A8  
VSS  
A9  
A10  
VCC  
DQMB2  
DQMB3  
VSS  
DQ24  
DQ25  
DQ26  
DQ27  
VCC  
DQ28  
DQ29  
DQ30  
DQ31  
VSS  
PIN  
98  
BACK  
DQ54  
DQ55  
VCC  
A7  
BA0  
VSS  
BA1  
A11  
VCC  
DQMB6  
DQMB7  
VSS  
DQ56  
DQ57  
DQ58  
DQ59  
VCC  
DQ60  
DQ61  
DQ62  
DQ63  
VSS  
Select Bank  
1
3
5
7
VSS  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
2
4
6
8
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
DQ13  
DQ14  
DQ15  
VSS  
NC  
NC  
CKL0  
VCC  
RAS#  
WE#  
CS0#  
NC  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
Data Input/Output  
Clock Input  
DQ32  
DQ33  
DQ34  
DQ35  
VCC  
DQ36  
DQ37  
DQ38  
DQ39  
VSS  
DQMB4  
DQMB5  
VCC  
A3  
A4  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
Clock Enable Input  
Chip Select Input  
Row Address Strobe  
Column Address Strobe  
Write Enable  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
RAS#  
CAS#  
WE#  
DQ4  
DQ5  
DQ6  
DQ7  
VSS  
DQMB0  
DQMB1  
VCC  
A0  
A1  
A2  
VSS  
DQ8  
DQ9  
DQ10  
DQ11  
VCC  
DQMB0-7  
VCC  
DQM  
Power Supply (3.3V)  
Ground  
NC  
VSS  
NC  
NC  
VSS  
SDA  
Serial Data I/O  
Serial Clock  
SCL  
NC  
VCC  
DNU  
Do Not Use  
A5  
VSS  
VCC  
DQ16  
DQ17  
DQ18  
DQ19  
VSS  
DQ48  
DQ49  
DQ50  
DQ51  
VSS  
NC  
No Connect  
DQ40  
DQ41  
DQ42  
DQ43  
VCC  
DQ20  
DQ21  
DQ52  
DQ53  
SDA  
VCC  
SCL  
VCC  
DQ12  
DQ44  
April 2004  
Rev. 1  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WED3DG6466V-JD1  
-AD1  
White Electronic Designs  
PRELIMINARY  
FUNCTIONAL BLOCK DIAGRAM  
WE#  
DQMB0  
S0#  
DQMB4  
DQM  
S
WE  
DQM  
S
WE  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
D0  
D4  
DQ6  
DQ7  
I/O 6  
I/O 7  
DQ38  
DQ39  
I/O 6  
I/O 7  
DQMB1  
DQMB5  
S
WE  
S
WE  
DQM  
DQM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
D1  
D5  
I/O 7  
I/O 7  
DQMB2  
DQMB6  
S
WE  
S
WE  
DQM  
DQM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
D2  
D6  
DQ54  
DQ55  
I/O 6  
I/O 7  
I/O 6  
I/O 7  
DQMB3  
DQMB7  
DQM  
S
WE  
DQM  
S
WE  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
D3  
D7  
DQ62  
DQ63  
I/O 6  
I/O 7  
I/O 6  
I/O 7  
NOTE: DQ writing may differ than described in this drawing,  
however DQ/DQMB/CKE/S relationships must be  
maintained as shown.  
*CLOCK WIRING  
CLOCK  
INPUT  
SDRAMS  
RAS#  
CAS#  
CKE0  
RAS#: SDRAM D0-D7  
CAS#: SDRAM D0-D7  
CKE: SDRAM D0-D7  
*CLK0  
*CLK1  
4 OR 5 SDRAMS  
4 OR 5 SDRAMS  
*Wire per Clock Loading Table/Wiring Diagrams  
BA0-BA1  
A0-A12  
BA0-BA1: SDRAM D0-D7  
A0-A12: SDRAM D0-D7  
SERIAL PD  
SDA  
SCL  
VDD  
D0-D7  
D0-D7  
A1  
A2  
A0  
VSS  
April 2004  
Rev. 1  
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WED3DG6466V-JD1  
-AD1  
White Electronic Designs  
PRELIMINARY  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
Units  
V
Voltage on any pin relative to VSS  
Voltage on VCC supply relative to VSS  
Storage Temperature  
VIN, VOUT  
VCC, VCCQ  
TSTG  
-1.0 ~ 4.6  
-1.0 ~ 4.6  
-55 ~ +150  
9
V
°C  
W
Power Dissipation  
PD  
Short Circuit Current  
IOS  
50  
mA  
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
RECOMMENDED DC OPERATING CONDITIONS  
Voltage Referenced to: VSS = 0V, 0°C TA +70°C  
Parameter  
Symbol  
VCC  
VIH  
Min  
3.0  
2.0  
-0.3  
2.4  
Typ  
3.3  
3.0  
Max  
3.6  
Unit  
V
Note  
Supply Voltage  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
Input Leakage Current  
VCCQ +0.3  
0.8  
V
1
2
VIL  
V
VOH  
VOL  
ILI  
V
IOH= -2mA  
IOL= -2mA  
3
0.4  
V
-10  
10  
µA  
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.  
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.  
3. Any input 0V ≤ VIN ≤ VCCQ  
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.  
CAPACITANCE  
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV  
Parameter  
Symbol  
CIN1  
Max  
35  
35  
35  
16  
35  
7
Unit  
Input Capacitance (A0-A12)  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance (RAS#,CAS#,WE#)  
Input Capacitance (CKE0)  
CIN2  
CIN3  
Input Capacitance (CK0)  
CIN4  
Input Capacitance (CS0#)  
CIN5  
Input Capacitance (DQM0-DQM7)  
Input Capacitance (BA0-BA1)  
Data Input/Output Capacitance (DQ0-DQ63)  
CIN6  
CIN7  
35  
10  
COUT  
April 2004  
Rev. 1  
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WED3DG6466V-JD1  
-AD1  
White Electronic Designs  
PRELIMINARY  
OPERATING CURRENT CHARACTERISTICS  
VCC = 3.3V, TA = 0°C to +70°C  
Version  
Parameter  
Symbol  
Conditions  
133/100  
Units  
Note  
Operating Current  
(One bank active)  
ICC1  
Burst Length = 1  
tRC tRC(min)  
IOL = 0mA  
mA  
1
1600  
Precharge Standby Current  
in Power Down Mode  
ICC2P  
ICC2PS  
ICC2N  
50  
50  
mA  
CKE VIL(max), tCC = 10ns  
CKE & CK VIL(max), tCC = ∞  
CKE VIH(min), CS VIH(min), tcc =10ns  
Input signals are charged one time during 20  
240  
80  
Precharge Standby Current  
in Non-Power Down Mode  
mA  
mA  
ICC2NS  
CKE VIH(min), CK VIL(max), tCC = ∞  
Input signals are stable  
ICC3P  
ICC3PS  
ICC3N  
80  
80  
CKE VIL(max), tCC = 10ns  
Active Standby Current in  
Power-Down Mode  
CKE & CK VIL(max), tCC = ∞  
mA  
mA  
CKE VIH(min), CS VIH(min), tcc = 10ns Input  
signals are changed one time during 20ns  
400  
400  
Active Standby Current in  
Non-Power Down Mode  
ICC3NS  
ICC4  
CKE VIH(min), CK VIL(max), tcc = ∞  
Input signals are stable  
Io = mA  
Page burst  
4 Banks activated  
tCCD = 2CK  
Operating Current (Burst mode)  
1600  
mA  
1
2
Refresh Current  
ICC5  
ICC6  
2640  
60  
mA  
mA  
tRC tRC(min)  
CKE 0.2V  
Self Refresh Current  
Notes:  
1.  
2.  
3.  
Measured with outputs open.  
Refresh period is 64ms.  
Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VCCQ/VSSQ  
)
April 2004  
Rev. 1  
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WED3DG6466V-JD1  
-AD1  
White Electronic Designs  
PRELIMINARY  
PACKAGE DIMENSIONS FOR AD1  
Ordering Information  
WED3DG6466V10AD1  
WED3DG6466V7AD1  
WED3DG6466V75AD1  
Speed  
100MHz  
133MHz  
133MHz  
CAS Latency  
CL=2  
Height*  
27.81 (1.095”)  
27.81 (1.095”)  
27.81 (1.095”)  
CL=2  
CL=3  
Note: For industrial temperature range product, add an "I" to the end of the part number.  
PACKAGE DIMENSIONS FOR AD1  
67.72  
(2.661 Max)  
3.81  
(0.150)  
MAX.  
2.01 (0.079 Min)  
27.81  
(1.095)  
Max  
3.99  
(0.157)  
19.99  
(0.787)  
9.91  
32.79  
(1.291)  
(0.039)  
(
0.004)  
23.14  
(0.913)  
4.60 (0.181)  
1.50 (0.059)  
28.2  
(1.112)  
* All Dimensions are in millimeters and (inches).  
April 2004  
Rev. 1  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WED3DG6466V-JD1  
-AD1  
White Electronic Designs  
PRELIMINARY  
PACKAGE DIMENSIONS FOR JD1  
Ordering Information  
WED3DG6466V10JD1  
WED3DG6466V7JD1  
WED3DG6466V75JD1  
Speed  
100MHz  
133MHz  
133MHz  
CAS Latency  
CL=2  
Height*  
31.75 (1.250”)  
31.75 (1.250”)  
31.75 (1.250”)  
CL=2  
CL=3  
Note: For industrial temperature range product, add an "I" to the end of the part number.  
PACKAGE DIMENSIONS FOR JD1  
67.72  
(2.661 Max)  
3.81  
(0.150)  
MAX.  
2.01 (0.079 Min)  
31.75  
(1.250)  
Max  
3.99  
(0.157)  
19.99  
(0.787)  
9.91  
32.79  
(1.291)  
(0.039)  
(
0.004)  
23.14  
(0.913)  
4.60 (0.181)  
1.50 (0.059)  
28.2  
(1.112)  
* All Dimensions are in millimeters and (inches).  
April 2004  
Rev. 1  
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
WED3DG6466V-JD1  
-AD1  
White Electronic Designs  
PRELIMINARY  
Document Title  
512MB - 64Mx64 SDRAM UNBUFFERED  
Revision History  
Rev #  
History  
Release Date Status  
Rev 0  
Rev 1  
Created Datasheet  
6-4-03  
4-04  
Advanced  
1.1 Updated Datasheet  
1.2 Added AD1 package option  
Preliminary  
April 2004  
Rev. 1  
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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