WED3DG6466V7D2G [MICROSEMI]
Synchronous DRAM Module, 64MX8, 5.4ns, CMOS, LEAD FREE, DIMM-144;
| 型号： | WED3DG6466V7D2G |
| 厂家： | 
Microsemi |
| 描述： | Synchronous DRAM Module, 64MX8, 5.4ns, CMOS, LEAD FREE, DIMM-144 动态存储器 |
| 文件： | 总9页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3DG6466V-D2
White Electronic Designs
512MB – 64Mx64, SDRAM UNBUFFERED
FEATURES
DESCRIPTION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
PC100 and PC133 compatible
Burst Mode Operation
The WED3DG6466V is a 64Mx64 synchronous DRAM
module which consists of eight 64Mx8 SDRAM components
in TSOP II package and one 2K EEPROM in an 8 Pin
TSSOP package for Serial Presence Detect which are
mounted on a 168 Pin DIMM multilayer FR4 Substrate.
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
* This product is subject to change without notice.
ꢀ
ꢀ
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
Available with "WP" Write Protect on Pin 81 option
• WED3DG6366V-D2
NOTE: Consult factory for availability of:
• Lead-Free or RoHS Products
• Vendor source control options
• Industrial temperature option
ꢀ
ꢀ
3.3V ± 0.3V Power Supply
168 Pin DIMM JEDEC
• PCB: 30.48 (1.20") MAX
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Pin
Front
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0#
DNU
VSS
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
VDD
Pin
Back
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
*CS1#
RAS#
VSS
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
VDD
A0 - A12
BA0-1
Address input (Multiplexed)
Select Bank
1
VSS
85
VSS
2
DQ0
DQ1
DQ2
DQ3
VDD
86
DQ32
DQ33
DQ34
DQ35
NC
DQ0-63
CBO-7
Data Input/Output
Check bit (Data-in/Data-out)
Clock input
3
87
4
DQ20
NC
88
DQ52
NC
CK0,CK2
CKE0#
5
A0
89
A1
Clock Enable input
6
A2
*VREF
*CKE1
VSS
90
A3
*VREF
DNU
VSS
CS0# - CS2# Chip select Input
7
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
A4
91
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
A5
8
A6
92
A7
RAS#
CAS#
WE#
DQM0-7
VDD
Row Address Strobe
Column Address Strobe
Write Enable
DQM
9
A8
DQ21
DQ22
DQ23
VSS
93
A9
DQ53
DQ54
DQ55
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10/AP
BA1
VDD
94
BA0
A11
95
96
VDD
Power Supply (3.3V)
Ground
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
VDD
DQ24
DQ25
DQ26
DQ27
VDD
97
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
*CK1
A12
DQ56
DQ57
DQ58
DQ59
VDD
VSS
CK0
VSS
98
SDA
SCL
Serial data I/O
Serial clock
99
VSS
DNU
CS2#
DQM2
DQM3
DNU
VDD
100
101
102
103
104
105
106
107
108
109
110
111
112
CKE0
CS3#
DQM6
DQM7
*A13
VDD
DNU
NC
Do not use
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
DQ62
DQ63
VSS
No Connect
DQ14
DQ15
*CBO
*CB1
Vss
DQ46
DQ47
*CB4
*CB5
VSS
WP
Write Protect
* These pins are not used in this module.
** These pins should be NC in the system which does not
support SPD.
NC
NC
NC
CK2
NC
*CK3
NC
*** WP available on the WED3DG6364V-D2 only
NC
*CB2
*CB3
VSS
NC
NC
*CB6
*CB7
VSS
NC
***WP
**SDA
**SCL
VDD
NC
**SA0
**SA1
**SA2
VDD
VDD
VDD
WE#
DQM0
DQ16
DQ17
CAS#
DQM4
DQ48
DQ49
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQM0
DQM4
DQM
DQM
CS#
CS#
CS#
CS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQM5
DQM
DQM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS2#
DQM2
DQM6
DQM
DQM
CS#
CS#
CS#
CS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM3
DQM7
DQM
DQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A0 ~ A12, BA0 & 1
SDRAM
SCL
SDA
WP
RAS#
CAS#
SDRAM
SDRAM
WP
A0 A1 A2
SA0 SA1 SA2
WE#
SDRAM
SDRAM
CKE0
SDRAM
10Ω
SDRAM
SDRAM
SDRAM
CK0/2
10Ω
DQn
Every DQpin of SDRAM
1.5 pF
10Ω
VCC
Two 0.1uF and one 0.22 uF Cap.
per each SDRAM
To all SDRAMs
Vss
CK1/3
10pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
8
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
PD
V
°C
W
Power Dissipation
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0°C TA +70°C
Parameter
Symbol
VCC
VIH
Min
3.0
2.0
-0.3
2.4
—
Typ
3.3
3.0
—
Max
Unit
V
Note
Supply Voltage
3.6
VCCQ+0.3
0.8
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
V
1
VIL
V
2
VOH
VOL
ILI
—
—
V
IOH = -2mA
IOL = -2mA
3
—
0.4
V
-10
—
10
μA
Note:
1.
2.
3.
V
V
IH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
IL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
Any input 0V ≤ VIN ≤ VCC
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF=1.4V ± 200mV
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
40
40
40
30
25
10
40
10
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0-CKE1)
Input Capacitance (CK0-CK3)
Input Capacitance (CS0#-CS3#)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
IDD SPECIFICATIONS AND CONDITIONS
VCC, VCCQ = +3.3V ±0.3V; SDRAM component values only
MAX
PARAMETER/CONDITION
SYMBOL
7
7.5 & 10
1,440
50
UNITS
mA
NOTES
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN)
STANDBY CURRENT: Power-Down Mode; All device devicebanks idle; CKE = LOW
IDD1
IDD2
IDD3
1,600
56
1
mA
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active
after tRCD met; No accesses in progress
720
280
mA
OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device
banks active
IDD4
1,600
1,360
mA
1
2
AUTO REFRESH CURRENT
tRFC = tRFC (MIN)
RFC = 7.8125μs
IDD5
IDD6
IDD7
2,640
96
2,480
96
mA
mA
mA
CKE = HIGH; CS# = HIGH
t
SELF REFRESH CURRENT: CKE < 0.2V
60
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
VCC, VCCQ = +3.3V ±0.3V
AC CHARACTERISTICS
7
7.5
10
PARAMETER
SYMBOL
tAC(3)
tAC(2)
tAH
MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
NOTE
Access timefrom CLK (pos.edge)
CL = 3
CL = 2
6
6
27
5.4
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
tAS
tCH
3
tCL
3
CL = 3
CL = 2
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
tDH
8
23
23
7.5
0.8
1.5
0.8
1.5
0.8
1.5
10
1
CKE hold time
CKE setup time
0.8
1.5
0.8
1.5
0.8
1.5
2
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
1
2
1
Data-in setup time
tDS
2
Data-out high-impedance time
CL = 3
CL = 2
tHZ(3)
tHZ(2)
tLZ
5.4
5.4
5.4
6
6
6
10
10
Data-out low-impedance time
Data-out hold time (load)
1
1
1
tOH
2.7
1.8
37
60
15
64
66
15
14
0.3
2.7
1.8
44
66
20
64
66
20
15
0.3
2.7
1.8
50
66
20
64
66
20
15
0.3
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period
tOHN
tRAS
tRC
28
120,000
120,000
120,000
tRCD
tREF
tRFC
tRP
AUTOREFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
tRRD
tT
1.2
1.2
1.2
7
WRITE recovery time
tWR
1 CLK
+
1 CLK
+
1 CLK
+
24
7ns
7.5ns
7.5ns
14
67
15
75
15
80
ns
ns
25
20
Exit SELF REFRESH to ACTIVE command
tXSR
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
AC FUNCTIONAL CHARACTERISTICS
VCC, VCCQ = +3.3V ±0.3V
PARAMETER
SYMBOL
tCCD
7
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
7.5
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
10
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
UNITS
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES
17
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
tCKED
tPED
14
14
tDQD
17
DQM to data mask during WRITEs
tDQM
tDQZ
tDWD
tDAL
17
DQMto data high-impedance during READs
WRITE command to input data delay
Data-into ACTIVE command
17
17
15, 21
16, 21
17
Data-into PRECHARGE command
tDPL
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Lastdata-into PRECHARGE command
LOADMODEREGISTER command to ACTIVE or REFRESH command
tBDL
tCDL
17
tRDL
16, 21
26
tMRD
Data-out to high-impedance from PRECHARGE command
CL = 3
CL = 2
tROH(3)
tROH(2)
17
17
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
Notes
1.
All voltages referenced to VSS
.
16. Timing actually specified by tWR
.
2.
This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25°C; pin under test biased
at 1.4V; f = 1 MHz.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
3.
I
DD is dependent on output loading and cycle rates. Specified values are obtained
18. The IDD current will increase or decrease proportionally according to the amount
of frequency alteration for the test condition.
with mini-mum cycle time and the outputs open.
4.
5.
Enables on-chip refresh and address counters.
The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5.
6.
An initial pause of 100μs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.)
The two AUTO REFRESH command wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
22.
VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse
width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL
(MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7;
7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is
executed. May not exceed limit set for precharge mode.
7.
8.
AC characteristics assume tT = 1ns.
In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
Outputs measured at 1.5V with equivalent load:
9.
Q
25. Precharge mode only.
26. JEDEC and PC133, PC100 specify three clocks.
50pF
27.
tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design.
10. tHZ defines the time at which the output achieves the open circuit condition; it is
not a reference to VOH or VOL. The last valid data element will meet tOH before
going High-Z.
28. Parameter guaranteed by design.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13.
IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
ORDERING INFORMATION
Part Number
Speed
100MHz
133MHz
133MHz
CAS Latency
CL=2
Height*
Part Number
Speed
100MHz
133MHz
133MHz
CAS Latency
CL=2
Height*
WED3DG6466V10D2
WED3DG6466V7D2
WED3DG6466V75D2
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
WED3DG6366V10D2
WED3DG6366V7D2
WED3DG6366V75D2
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
CL=2
CL=2
CL=3
CL=3
NOTES:
NOTE: Available with "WP" Write Protect on pin 81.
• Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free,
G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components
source control. The place holder for this is shown as lower case “x” in the
part numbers above and is to be replaced with the respective vendors code.
Consult factory for qualified sourcing options. (M = Micron, S = Samsung &
consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS
133.48
2.54
(0.100)
MAX.
(5.255 MAX.)
3.18
(0.125) (2X)
3.99
(0.157)
(2X)
30.48
(1.200)
MAX.
17.78
(0.700)
P1
36.83
11.43
54.61
3.99
(0.157)
MIN.
(1.450)
(0.450)
(2.150)
6.35
(0.250)
42.16
(1.660)
8.89
6.35
(0.250)
(0.350)
1.27 0.10
(0.050 0.004)
115.57
(4.550)
*ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG6466V-D2
White Electronic Designs
Document Title
512MB – 64Mx64, SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date Status
Rev A
Rev B
Rev 0
Rev 1
Created
4-10-02
5-1-02
8-19-02
5-05
Advanced
Advanced
Final
Corrected mechanical drawing
Changed from Advanced to Final
1.1 Updated IDD specs
Final
1.2 Added AC and notes
1.3 Added lead-free and RoHS notes
1.4 Added source control notes
1.5 Added industrial temperature options
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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