W26020AT-15 [WINBOND]
Standard SRAM, 128KX16, 16ns, CMOS, PDSO44, TSOP2-44;型号: | W26020AT-15 |
厂家: | WINBOND |
描述: | Standard SRAM, 128KX16, 16ns, CMOS, PDSO44, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
文件: | 总10页 (文件大小:144K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
W26020A
´ 16 HIGH-SPEED CMOS STATIC RAM
128K
GENERAL DESCRIPTION
The W26020A is a high-speed, low-power CMOS static RAM organized as 131,072 ´ 16 bits that
operates on a single 5-volt power supply. This device is manufactured by using Winbond's high
performance CMOS technology.
The W26020A has an active low chip select, separate upper and lower byte selects, and a fast output
enable. No clock or refreshing is required. Separate byte select controls (#LB and #UB) allow individual
bytes to be written and read. #LB controls I/O1-I/O8, the lower byte. #UB controls I/O9- I/O16, the
upper byte. This device is well suited for use in high-density, high-speed system applications.
FEATURES
· High speed access time: 16/25 nS (Max.)
· Low power consumption:
- Active: 1.5W (Max.)
· All inputs and outputs directly TTL compatible
· Three-state outputs
· Data byte control
- #LB (I/O1 - I/O8), #UB (I/O9 - I/O16)
· Available packages: 44-pin type two TSOP
· Single +5V power supply
· Fully static operation
- No clock or refreshing
PIN CONFIGURATION
BLOCK DIAGRAM
VDD
V
SS
A0
A1
A2
1
2
3
4
5
6
44
43
42
A15
A14
A13
#OE
#UB
A0
.
.
DECODER
CORE
ARRAY
A16
A3
A4
41
40
#CS
#LB
39
38
37
36
#UB
#CS
#OE
I/O16
I/O15
I/O14
I/O13
I/O1
I/O2
7
8
I/O1
CONTROL
.
.
DATA I/O
#WE
#LB
I/O16
I/O3
I/O4
9
35
34
33
32
31
30
29
28
10
11
12
13
V
SS
V
DD
PIN DESCRIPTION
V
V
DD
SS
I/O5
I/O12
I/O11
I/O10
I/O9
SYMBOL
DESCRIPTION
I/O6
I/O7
I/O8
#WE
A5
14
15
16
Address Inputs
A0 - A16
I/O1 - I/O16
#CS
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Lower Byte Select I/O1 - I/O8
Upper Byte Select I/O9 - I/O16
Power Supply
NC
17
18
19
20
21
22
#WE
#OE
#LB
A12
A11
A10
27
26
A6
A7
25
24
23
#UB
A8
A9
VDD
A16
NC
VSS
Ground
NC
No Connection
Publication Release Date: October 8, 2001
Revision A5
- 1 -
W26020A
TRUTH TABLE
#CS #OE #WE #LB #UB
MODE
VDD
I/O1
-
I/O8
I/O9 - I/O16
CURRENT
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
H
H
L
X
X
L
X
X
L
Not Selected
High Z
High Z
DOUT
DOUT
High Z
DIN
High Z
High Z
DOUT
High Z
DOUT
DIN
ISB, ISB1
IDD
Output Disable
2 Bytes Read
IDD
L
L
H
L
Lower Byte Read
Upper Byte Read
2 Bytes Write
IDD
L
H
L
IDD
X
X
X
X
L
IDD
L
L
H
L
Lower Byte Write
Upper Byte Write
Output Disable
DIN
High Z
DIN
IDD
L
H
H
High Z
High Z
IDD
X
H
High Z
IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to VSS Potential
Input/Output to VSS Potential
Allowable Power Dissipation
Storage Temperature
RATING
-0.5 to +7.0
UNIT
V
-0.5 to VDD +0.5
1.5
V
W
-65 to +150
0 to +70
°C
°C
Operating Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VDD = 5V ±5%, VSS = 0V, TA = 0 to 70° C)
PARAMETER
Input Low Voltage
SYM.
VIL
TEST CONDITIONS
MIN. TYP.
MAX.
+0.8
UNIT
V
-
-0.5
+2.2
-10
-
-
-
-
Input High Voltage
VIH
ILI
-
VDD +0.5
+10
V
Input Leakage Current
Output Leakage Current
VIN = VSS to VDD
mA
mA
ILO
VI/O = VSS to VDD
Output Pins in High Z,
See Truth Table
-10
+10
Output Low Voltage
Output High Voltage
VOL
IOL = +8.0 mA
-
-
-
0.4
-
V
V
VOH IOH = -4.0 mA
2.4
- 2 -
W26020A
Operating Characteristics, continued
PARAMETER
Operating Power
Supply Current
SYM.
TEST CONDITIONS
#CS = VIL (Max.),
MIN. TYP. MAX.
UNIT
IDD
16
25
-
-
-
-
220
200
mA
I/O = Open, Cycle = Min.
Duty = 100%
Standby Power
Supply Current
ISB
#CS = VIH (Min.), Cycle = Min.
-
-
-
-
50
10
mA
mA
ISB1 #CS = VDD -0.2V, I/O = Open
All other pins = VDD -0.2V/GND
Note: Typical characteristics are evaluated at VDD = 5V, TA = 25° C.
CAPACITANCE
(VDD = 5 V, TA = 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
CIN
CONDITIONS
VIN = 0V
MAX.
UNIT
6
8
pF
pF
CI/O
VOUT = 0V
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
3 nS
1.5V
CL = 30 pF, IOH/IOL = -4 mA/8 mA
Publication Release Date: October 8, 2001
Revision A5
- 3 -
W26020A
AC Test Loads and Waveform
R1 480 ohm
5 pF
5V
R1 480 ohm
5V
OUTPUT
OUTPUT
R2
255 ohm
R2
255 ohm
30 pF
Including
Jig and
Scope
Including
Jig and
Scope
)
TWHZ, TOW
TBHZ, TOHZ,
TCHZ,
TBLZ,
( For TCLZ,
TOLZ,
3.0V
0V
90%
90%
10%
10%
3 nS
3 nS
Read Cycle
(VDD = 5V ±5%, VSS = 0V, TA = 0 to 70° C)
W26020A-15
MIN. MAX.
W26020A-25
PARAMETER
SYM.
UNIT
MIN.
MAX.
-
Read Cycle Time
TRC
TAA
16
-
-
16
16
6
7
-
25
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Access Time
25
25
12
12
-
Chip Select Access Time
TACS
TAOE
-
-
Output Enable to Output Valid
#UB, #LB Access Time
-
-
TBA
-
-
Output Hold from Address Change
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
#UB, #LB Select to Output in Low Z
#UB, #LB Deselect to Output in High Z
TOH
3
3
-
5
5
-
TCLZ*
TCHZ*
TOLZ*
TOHZ*
-
-
6
-
12
-
0
-
0
-
6
-
12
-
*
0
0
TBLZ
TBHZ*
6
12
-
-
* These parameters are sampled but not 100% tested.
- 4 -
W26020A
AC Characteristics, continued
Write Cycle
PARAMETER
SYM.
W26020A-15
W26020A-25
UNIT
MIN.
16
13
13
0
MAX.
MIN.
25
18
18
0
MAX.
Write Cycle Time
TWC
TCW
TAW
TAS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
-
-
-
-
-
-
-
-
-
8
-
-
-
Chip Select to End of Write
Address Valid to End of Write
Address Setup Time
-
-
#UB, #LB Select to End of Write
Write Pulse Width
TBW
TWP
TWR
TDW
TDH
13
13
0
18
18
0
-
-
Write Recovery Time
#CS, #WE
-
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
End of Write to Output Active
9
12
0
-
0
-
TWHZ*
TOW*
12
-
-
-
5
5
* These parameters are sampled but not 100% tested.
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled, #CS = #OE = #UB = #LB = VIL, #WE = VIH)
T
RC
Address
T
AA
T
OH
T
OH
D
OUT
Publication Release Date: October 8, 2001
Revision A5
- 5 -
W26020A
Timing Waveforms, continued
Read Cycle 2
(Chip Select Controlled, #OE = VIL, #WE = VIH)
T
RC
Address
T
ACS
#CS
T
CLZ
T
CHZ
T
BA
#UB / #LB
T
BHZ
T
BLZ
D
OUT
Read Cycle 3
(Output Enable Controlled, #CS = #LB = #UB = VIL, #WE = VIH)
T
RC
Address
#OE
T
T
AOE
T
OH
T
OLZ
OHZ
D
OUT
- 6 -
W26020A
Timing Waveforms, continued
Write Cycle 1
(#OE Clock)
T
WC
Address
#OE
TWR
T
CW
#CS
T
BW
#UB/ #LB
#WE
T
AW
T
WP
T
AS
D
OUT
T
DW
T
DH
D
IN
Write Cycle 2
(#OE = VIL Fixed)
T
WC
Address
#CS
T
T
T
WR
CW
BW
#UB/ #LB
T
AW
TWP
#WE
T
OH
T
AS
(2)
(3)
T
WHZ (1, 4)
T
OW
D
OUT
T
DH
T
DW
D
IN
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
Publication Release Date: October 8, 2001
- 7 -
Revision A5
W26020A
ORDERING INFORMATION
PART NO.
ACCESS
TIME
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
(nS)
W26020AT-15
W26020AT-25
Notes:
16
25
220
200
10
10
44-pin type two TSOP
44-pin type two TSOP
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
- 8 -
W26020A
PACKAGE DIMENSIONS
44-pin Standard Type Two TSOP
Y
Dimension in inches
Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
A
D
A 2
A
0.047
1.20
A
1
0.002
0.05
1
A
2
0.037 0.039 0.041
0.010 0.014 0.018
0.95
0.25
0.12
1.00 1.05
0.35 0.45
A
b
D
E
H
0.005 0.006 0.007
0.15 0.17
c
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
0.455 0.463 0.471 11.56 11.76 11.96
D
E
1
L
L
H
e
L
D
e
q
0.031
0.016 0.020 0.024 0.40 0.50
0.031 0.80
0.80
b
M
0.10 (0.004)
0.60
L 1
Y
0.004
o
0.10
o
c
o
o
0
5
0
5
q
Publication Release Date: October 8, 2001
Revision A5
- 9 -
W26020A
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
Jan. 1998
May. 1998
Initial Issued
1
Power consumption 1.3W to 1.5W
Modify pin configuration
4
5
TOH from 3 to 4 for-20, TOH from 3 to 4 for-25
TCLZ* from 3 to 5 for-25
TCW from 13 to 12 for-15, TCW from 17 to 14 for-20
TCW from 18 to 15 for-25, TWP from 10 to 13 for-15
TWP from 12 to 17 for-20, TWP from 15 to 18 for-25
TOW from 0 to 3 for-15, TOW from 0 to 5 for-20
TOW from 0 to 5 for-25
A3
A4
Jul. 1998
Jun. 2001
1, 3, 4, 5, 8, 9 Delete 15 nS and SOJ item
2, 4
Modify VDD parameter from 5V ±10% to 5V ±5%
1, 3, 4, 5, 8 Delete 20 nS and add in 15 nS specification
1, 3, 4, 5, 8 Change access time from 15 nS to 16 nS
A5
Oct. 8, 2001
5
Write Cycle parameter TCW, TAW, TWP and TBW for
W26020A-15 are changed from 10 nS to 13 nS; TCW for
W26020A-25 is changed from 15 nS to 18 nS
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
2727 N. First Street, San Jose,
FAX: 886-3-5792766
CA 95134, U.S.A.
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 10 -
相关型号:
©2020 ICPDF网 联系我们和版权申明