W26020AT-25 [WINBOND]
128K X 16 High Speed CMOS Static RAM; 128K ×16高速CMOS静态RAM
| 型号： | W26020AT-25 |
| 厂家： | 
WINBOND |
| 描述： | 128K X 16 High Speed CMOS Static RAM |
| 文件： | 总10页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W26020A
128K ´ 16 HIGH-SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W26020A is a high-speed, low-power CMOS static RAM organized as 131,072 ´ 16 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
The W26020A has an active low chip select, separate upper and lower byte selects, and a fast output
enable. No clock or refreshing is required. Separate byte select controls (LB and UB ) allow
individual bytes to be written and read. LB controls I/O1-I/O8, the lower byte. UB controls I/O9-
I/O16, the upper byte. This device is well suited for use in high-density, high-speed system
applications.
FEATURES
· High speed access time: 20/25 nS (max.)
· Low power consumption:
- Active: 1.5W (max.)
· All inputs and outputs directly TTL compatible
· Three-state outputs
· Data byte control
· Single +5V power supply
· Fully static operation
- LB (I/O1- I/O8), UB (I/O9- I/O16)
· Available packages: 44-pin type two TSOP
- No clock or refreshing
PIN CONFIGURATION
BLOCK DIAGRAM
V
DD
V
SS
A0
A1
A2
A3
A4
1
2
3
4
5
6
44
43
42
A15
A14
A13
A0
.
.
DECODER
CORE
ARRAY
A16
41
40
OE
UB
UB
CS
I/O1
I/O2
39
38
37
36
35
34
33
32
31
LB
CS
OE
I/O1
I/O16
7
8
CONTROL
.
.
DATA I/O
I/O15
I/O14
I/O13
WE
LB
I/O16
I/O3
I/O4
9
10
11
12
13
V
SS
V
DD
PIN DESCRIPTION
V
SS
V
DD
SYMBOL
A0- A16
I/O1- I/O16
DESCRIPTION
I/O5
I/O12
I/O11
I/O10
I/O9
Address Inputs
I/O6
I/O7
I/O8
WE
A5
14
15
16
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
30
29
28
CS
WE
OE
LB
NC
17
18
19
20
21
22
A12
A11
A10
A9
27
26
25
24
23
Output Enable Input
A6
Lower Byte Select I/O1- I/O8
Upper Byte Select I/O9- I/O16
A7
UB
A8
A16
NC
VDD
VSS
NC
Power Supply
Ground
No Connection
Publication Release Date: July 1998
Revision A3
- 1 -
W26020A
TRUTH TABLE
MODE
VDD
CURRENT
I/O1
-
I/O8
I/O9-I/O16
CS OE WE LB UB
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
H
H
L
X
X
L
X
X
L
Not Selected
High Z
High Z
DOUT
DOUT
High Z
DIN
High Z
High Z
DOUT
High Z
DOUT
DIN
ISB, ISB1
IDD
Output Disable
2 Bytes Read
IDD
L
L
H
L
Lower Byte Read
Upper Byte Read
2 Bytes Write
IDD
L
H
L
IDD
X
X
X
X
L
IDD
L
L
H
L
Lower Byte Write
Upper Byte Write
Output Disable
DIN
High Z
DIN
IDD
L
H
H
High Z
High Z
IDD
X
H
High Z
IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to VSS Potential
Input/Output to VSS Potential
Allowable Power Dissipation
Storage Temperature
RATING
UNIT
V
-0.5 to +7.0
-0.5 to VDD +0.5
1.5
V
W
-65 to +150
0 to +70
°C
°C
Operating Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER
Input Low Voltage
Input High Voltage
Input Leakage Current
SYM.
VIL
TEST CONDITIONS
MIN. TYP.
MAX.
+0.8
UNIT
V
-
-
-0.5
+2.2
-10
-
-
-
-
VIH
ILI
VDD +0.5
+10
V
VIN = VSS to VDD
mA
mA
Output Leakage
Current
ILO
VI/O = VSS to VDD
Output Pins in High Z,
See Truth Table
-10
+10
Output Low Voltage
Output High Voltage
VOL
IOL = +8.0 mA
-
-
-
0.4
-
V
V
VOH IOH = -4.0 mA
2.4
- 2 -
W26020A
Operating Characteristics, continued
PARAMETER
SYM.
TEST CONDITIONS
CS = VIL (max.),
MIN. TYP. MAX. UNIT
Operating Power
IDD
20
25
-
-
-
-
220
200
mA
Supply Current
I/O = Open, Cycle = min.
Duty = 100%
Standby Power
Supply Current
ISB
-
-
-
-
50
10
mA
mA
CS = VIH (min.), Cycle = min.
ISB1
CS = VDD -0.2V, I/O = open
All other pins = VDD -0.2V/GND
Note: Typical characteristics are evaluated at VDD = 5V, TA = 25° C.
CAPACITANCE
(VDD = 5 V, TA = 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
CIN
CONDITIONS
VIN = 0V
MAX.
UNIT
6
8
pF
pF
CI/O
VOUT = 0V
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
3 nS
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
1.5V
CL = 30 pF, IOH/IOL = -4 mA/8 mA
Publication Release Date: July 1998
Revision A3
- 3 -
W26020A
AC Test Loads and Waveform
R1 480 ohm
5 pF
5V
R1 480 ohm
5V
OUTPUT
OUTPUT
R2
255 ohm
R2
255 ohm
30 pF
Including
Jig and
Scope
Including
Jig and
Scope
)
TWHZ, TOW
TOHZ,
TBHZ,
TCHZ,
TBLZ,
TOLZ,
( For TCLZ,
3.0V
0V
90%
90%
10%
10%
3 nS
3 nS
Read Cycle
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
W26020A-20
MIN. MAX.
W26020A-25
MIN. MAX.
25
PARAMETER
SYM.
UNIT
Read Cycle Time
TRC
TAA
20
-
-
-
nS
nS
nS
nS
nS
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
20
20
10
10
25
25
12
12
-
-
-
-
TACS
TAOE
-
-
TBA
-
UB LB
,
Access Time
Output Hold from Address Change
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
Output Enable to Output in Low Z
Output Disable to Output in High Z
TOH
4
3
-
5
5
-
nS
nS
nS
nS
nS
nS
-
-
-
-
TCLZ*
TCHZ*
TOLZ*
TOHZ*
10
-
12
-
0
-
0
-
10
-
12
-
*
TBLZ
0
0
UB , LB Select to Output in Low Z
TBHZ*
10
12
nS
-
-
UB , LB Deselect to Output in High Z
* These parameters are sampled but not 100% tested.
- 4 -
W26020A
AC Characteristics, continued
Write Cycle
PARAMETER
SYM.
W26020A-20
W26020A-25
UNIT
MIN.
20
14
17
0
MAX.
MIN.
25
15
18
0
MAX.
Write Cycle Time
TWC
TCW
TAW
TAS
nS
nS
nS
nS
nS
-
-
-
-
-
-
-
-
-
-
Chip Select to End of Write
Address Valid to End of Write
Address Setup Time
TBW
17
18
UB LB
,
Select to End of Write
Write Pulse Width
TWP
TWR
17
0
18
0
nS
nS
-
-
-
-
Write Recovery Time
CS WE
,
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
End of Write to Output Active
TDW
10
0
12
0
nS
nS
nS
nS
-
-
-
-
TDH
TWHZ*
TOW*
10
-
12
-
-
-
5
5
* These parameters are sampled but not 100% tested.
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled, CS = OE = UB = LB = VIL, WE = VIH)
T
RC
Address
T
AA
T
OH
T
OH
D
OUT
Publication Release Date: July 1998
Revision A3
- 5 -
W26020A
Timing Waveforms, continued
Read Cycle 2
(Chip Select Controlled, OE = VIL, WE = VIH)
T
RC
Address
T
ACS
CS
T
CLZ
T
CHZ
T
BA
UB / LB
T
BHZ
T
BLZ
D
OUT
Read Cycle 3
(Output Enable Controlled, CS = UB = LB = VIL, WE = VIH)
T
RC
Address
OE
T
AA
T
AOE
T
OH
T
OLZ
OHZ
T
D
OUT
- 6 -
W26020A
Timing Waveforms, continued
Write Cycle 1
(OE Clock)
T
WC
Address
OE
WR
T
CW
T
BW
UB/LB
WE
T
AW
WP
T
AS
D
OUT
T
DH
DW
D
IN
Write Cycle 2
(OE = VIL Fixed)
T
T
T
CW
BW
WR
CS
UB/LB
T
WE
T
T
(2)
T
D
T
T
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
Publication Release Date: July 1998
- 7 -
Revision A3
W26020A
ORDERING INFORMATION
PART NO.
ACCESS
TIME
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
(nS)
W26020AT-20
W26020AT-25
20
25
220
200
10
10
44-pin type two TSOP
44-pin type two TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
- 8 -
W26020A
PACKAGE DIMENSIONS
44-pin Standard Type Two TSOP
Y
Dimension in inches
Dimension in mm
Symbol
Max.
Min. Nom.
Min. Nom. Max.
A
D
A 2
A
0.047
1.20
A 1
0.002
0.05
1
A
2
0.95
0.25
0.12
0.037 0.039 0.041
0.010 0.014 0.018
1.00 1.05
0.35 0.45
A
b
c
D
E
H
0.005 0.006 0.007
0.15 0.17
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
0.455 0.463 0.471 11.56 11.76 11.96
D
E
1
L
L
D
H
e
q
0.80
0.50
0.80
0.031
e
L
b
M
0.10 (0.004)
0.016 0.020 0.024 0.40
0.60
0.031
0.004
1
L
c
0.10
Y
o
o
o
o
q
0
5
0
5
Publication Release Date: July 1998
Revision A3
- 9 -
W26020A
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
Jan. 1998
May. 1998
Initial Issued
1
Power consumption 1.3W to 1.5W
Modify pin configuration
4
5
TOH from 3 to 4 for-20, TOH from 3 to 4 for-25
TCLZ* from 3 to 5 for-25
TCW from 13 to 12 for-15, TCW from 17 to 14 for-20
TCW from 18 to 15 for-25, TWP from 10 to 13 for-15
TWP from 12 to 17 for-20, TWP from 15 to 18 for-25
TOW from 0 to 3 for-15, TOW from 0 to 5 for-20
TOW from 0 to 5 for-25
A3
Jul. 1998
1, 3, 4, Delete 15 nS and SOJ item
5, 8, 9
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
123 Hoi Bun Rd., Kwun Tong,
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 10 -
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