W55206B [WINBOND]
Standard SRAM, 128X1, 80ns, CMOS, PDIP18;
| 型号： | W55206B |
| 厂家： | 
WINBOND |
| 描述： | Standard SRAM, 128X1, 80ns, CMOS, PDIP18 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总6页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W55206B
SERIAL VOICE SRAM (128K 1 BIT)
´
GENERAL DESCRIPTION
The W55206B is a normal speed, low power CMOS static RAM organized as 128K ´ 1 bit that
operates on a single 5V power supply. Manufactured using Winbond's high performance CMOS
technology, the W55206B is designed for extensive use in voice recording applications.
FEATURES
· Single 3.6V to 5.5V power supply
· Low power consumption
· Fully static operation
· Low data retention voltage
· Easy to cascade
PIN CONFIGURATION
NC
NC
NC
1
2
3
18
17
16
NC
NC
NC
4
5
6
7
15
14
13
NC
NC
V
NC
NC
V
DD
SS
CS
12
CLK
DATA
ADDR
W/R
EOP
11
10
8
9
PIN DESCRIPTION
NO.
6
PIN
I/O
PWR
I
DESCRIPTION
VDD
Positive power supply
7
CS
Chip-inhibit for CS = 1; chip-select for CS = 0 or open (with internal
pull-low resistor)
Publication Release Date: September 1996
- 1 -
Revision A1
W55206B
Pin Description, continued
NO.
PIN
I/O
DESCRIPTION
8
I
W/R
EOP
ADDR
DATA
CLK
Write-in control for W/R = 1, read-out control for W/R = 0
End signal output
9
O
10
11
12
13
I
I/O
I
Clock input for start address
Bidirectional data pin
Clock input for address increment
Ground
VSS
PWR
BLOCK DIAGRAM
EOP
W/R
Control
SRAM
Circuits
CS
128K x 1 bit
DATA
ADDR
CLK
Address
Controller
FUNCTIONAL DESCRIPTION
· TRUTH TABLE
MODE
DATA PIN
VDD CURRENT
CS
H
W/R
X
Not selected
Write
High Z
Data in
Data out
ISB
IOP
IOP
L
H
L
L
Read
· When the chip is unselected, the W/R signal will be transmitted to the EOP pin.
· Before a read or write operation, the address counter must be reset by sending an ADDR pulse and
setting DATA = 0.
- 2 -
W55206B
· After power on, the read operation is disabled. A read operation may be performed only after a write
operation is completed.
· In write-in operation, the EOP signal will change from low to high and remain high when the final
address of the chip is encountered. It will change to low again with the next ADDR pulse.
· In read-out operation, the EOP pin will generate one pulse signal when the final address of the
SRAM chip is encountered.
The timing of the loading start address for write-in/read-out operations is shown below:
· Load start address for write-in/read-out operations:
CS
...
ADDR
CLK
...
DATA
EOP
· Write-in operation:
CS
W/R
ADDR
...
CLK
...
128K
DATA
EOP
Publication Release Date: September 1996
- 3 -
Revision A1
W55206B
· Read-out operation:
CS
W/R
ADDR
CLK
...
...
128K
DATA
EOP
T
EP
· No operation (standby)
CS
W/R
EOP
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
SYMBOL
RATING
-0.3 to +5.5
UNIT
V
VDD- VSS
VIN
Input Voltage
VSS -0.2 to VDD +0.2
VSS to VDD
V
Output Voltage
VO
V
Operating Temperature
Storage Temperature
TOPR
TSTG
0 to +70
°C
°C
-55 to +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
- 4 -
W55206B
DC CHARACTERISTICS
TA = 25° C, VDD = 5.0V, VSS = 0.0V
PARAMETER
SYMBOL
CONDITIONS
LIMIT
TYP. MAX.
UNIT
MIN.
3.6
-
Operating Voltage
Operating Current
VDD for Data Retention
VDD
IOP
-
5.0
5.5
15
V
mA
V
Fc = 1 MHz
-
-
VDR
2.4
5.5
CS ³ VDD -0.2V
Data Retention Current
IDDDR
-
-
10
mA
VDD ³ 3V, CS ³ 2.8V
Standby Current
ISB
VIH
VIL
-
-
-
-
2
-
10
6.0
mA
Input Voltage (for ADDR,
2.8
-0.5
V
-
+0.8
CLK, W/R and CS pins)
IIH
VI = 5.0V
-
-
5
mA
Input Current (for CS)
Output Current (for EOP)
IOH
IOL
VO = 4.0V
VO = 0.8V
4
6
-
-
mA
-4
-8
AC CHARACTERISTICS
Ta = 25° C, VDD = 5.0V, VSS = 0.0V
PARAMETER
SYMBOL CONDITIONS
MIN.
TYP
MAX.
UNIT
Clock Frequency (for CLK and
ADDR)
FC
-
-
-
1
MHz
Data Hold Time
TWH
TRH
TAH
TRA
TWS
TAS
TEP
TH
Write mode
0
0
-
-
-
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
nS
nS
nS
Data Hold Time
Read mode
Data Hold Time (for ADDR)
Data Access Time
-
0
-
Read mode
-
80
-
Data Setup Time
Write mode
250
250
100
400
Data Setup Time (for ADDR)
EOP Pulse Width (for ADDR)
-
-
Read mode
-
-
High Level Duration of Clock
for CLK and ADDR
-
Low Level Duration of Clock
for CLK and ADDR
TL
-
-
600
300
-
-
-
-
nS
nS
TSUR
W/R Signal Setup Time for
Write Mode
TSUW
TD
-
-
300
1
-
-
-
-
nS
W/R Signal Setup Time for
Write Mode
Time Width Between ADDR
and CLK Clock
mS
TYPICAL APPLICATION CIRCUIT (For reference only)
Publication Release Date: September 1996
Revision A1
- 5 -
W55206B
W51205901A/
W51205903A
W55206B
DATA
DATA
CLK
CLK
ADDR
ADDR
W/R
CS
W/R
EOP
CS
EOP
* W51205901A/W51205903A substrate connected to VSS for C.O.B.
* W55206B substrate connected to VDD for C.O.B.
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
123 Hoi Bun Rd., Kwun Tong,
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792697
Winbond Microelectronics Corp.
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 6 -
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