W681512S [WINBOND]
SINGLE-CHANNEL VOICEBAND CODEC; 单通道语音频带编解码器
| 型号： | W681512S |
| 厂家： | 
WINBOND |
| 描述： | SINGLE-CHANNEL VOICEBAND CODEC |
| 文件： | 总38页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W681512
SINGLE-CHANNEL VOICEBAND CODEC
Data Sheet
Publication Release Date: September, 2007
Revision C14
- 1 -
W681512
1. GENERAL DESCRIPTION
The W681512 is a general-purpose single channel PCM CODEC with pin-selectable μ-Law or A-Law
companding. The device is compliant with the ITU G.712 specification. It operates from a single +5V
power supply and is available in 20-pin SOG (SOP), SSOP and TSSOP package. Functions
performed include digitization and reconstruction of voice signals, and band limiting and smoothing
filters required for PCM systems. The filters are compliant with ITU G.712 specification. W681512
performance is specified over the industrial temperature range of –40°C to +85°C.
The W681512 includes an on-chip precision voltage reference and an additional power amplifier,
capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is
fully differential, reducing noise and improving the power supply rejection ratio. The data transfer
protocol supports both long-frame and short-frame synchronous communications for PCM
applications, and IDL and GCI communications for ISDN applications. W681512 accepts seven
master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically
determines the division ratio for the required internal clock.
ApplIcations
2. FEATURES
•
•
VoIP, Voice over Networks equipment
•
•
Single +5V power supply
Digital telephone and communication
systems
Typical power dissipation of 30 mW,
power-down mode of 0.5 μW
•
•
•
•
•
•
•
Wireless Voice devices
DECT/Digital Cordless phones
Broadband Access Equipment
Bluetooth Headsets
•
Fully-differential analog circuit design and
output signals
•
•
Differential Analog Outputs
On-chip precision reference of 1.575 V for
a 0 dBm TLP at 600 Ω (775mVRMS
Fiber-to-curb equipment
Enterprise phones
)
•
•
•
•
•
•
•
Push-pull power amplifiers with external
gain adjustment with 300 Ω load capability
Digital Voice Recorders
Seven master clock rates of 256 kHz to
4.096 MHz
Pin-selectable
companding (compliant with ITU G.711)
μ-Law
and
A-Law
CODEC A/D and D/A filtering compliant
with ITU G.712
Industrial temperature range (–40°C to
+85°C)
Packages: 20-pin SOG (SOP), SSOP and
TSSOP
Pb-Free package options available
- 2 -
W681512
3. BLOCK DIAGRAM
BCLKR
FSR
PAO+
PAO-
PAI
RO-
RO+
PCMR
G.712 CODEC
BCLKT
G.711 /A-Law
μ
AO
FST
AI+
AI-
PCMT
/A-Law
μ
256 kHz
VAG
MCLK
Voltage reference
Pre-Scaler
8 kHz
256 kHz,
512 kHz,
1536 kHz,
1544 kHz,
2048 kHz,
2560 kHz
& 4096 kHz
Power Conditioning
Publication Release Date: April, 2007
Revision C14
- 3 -
W681512
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 6
6. PIN DESCRIPTION............................................................................................................................. 7
7. FUNCTIONAL DESCRIPTION............................................................................................................ 8
7.1. Transmit Path ................................................................................................................................8
7.2. Receive Path .................................................................................................................................9
7.3. Power Management.....................................................................................................................10
7.3.1. Analog and Digital Supply.....................................................................................................10
7.3.2. Analog Ground Reference Voltage Output...........................................................................10
7.4. PCM Interface..............................................................................................................................10
7.4.1. Long Frame Sync..................................................................................................................10
7.4.2. Short Frame Sync .................................................................................................................11
7.4.3. General Circuit Interface (GCI) .............................................................................................11
7.4.4. Interchip Digital Link (IDL).....................................................................................................12
7.4.5. System Timing ......................................................................................................................12
8. TIMING DIAGRAMS.......................................................................................................................... 13
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20
9.1. Absolute Maximum Ratings.........................................................................................................20
9.2. Operating Conditions...................................................................................................................20
10. ELECTRICAL CHARACTERISTICS............................................................................................... 21
10.1. General Parameters ..................................................................................................................21
10.2. Analog Signal Level and Gain Parameters ...............................................................................22
10.3. Analog Distortion and Noise Parameters ..................................................................................23
10.4. Analog Input and Output Amplifier Parameters.........................................................................24
10.5. Digital I/O ...................................................................................................................................26
10.5.1. μ-Law Encode Decode Characteristics...............................................................................26
10.5.2. A-Law Encode Decode Characteristics ..............................................................................27
10.5.3. PCM Codes for Zero and Full Scale ...................................................................................28
10.5.4. PCM Codes for 0dBm0 Output ...........................................................................................28
11. TYPICAL APPLICATION CIRCUIT................................................................................................. 29
12. PACKAGE SPECIFICATION .......................................................................................................... 31
12.1. 20L SOG (SOP)-300mil.............................................................................................................31
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W681512
12.2. 20L SSOP-209 mil.....................................................................................................................33
12.3. 20L TSSOP - 4.4X6.5mm..........................................................................................................35
13. ORDERING INFORMATION........................................................................................................... 36
14. VERSION HISTORY ....................................................................................................................... 37
Publication Release Date: April, 2007
- 5 -
Revision C14
W681512
5. PIN CONFIGURATION
VAG
AI+
AI-
RO+
RO-
PAI
PAO-
PAO+
VDD
1
2
20
19
18
17
16
15
14
13
12
11
3
AO
4
SINGLE
CHANNEL
CODEC
/A-Law
5
μ
VSS
6
FST
PCMT
BCLKT
MCLK
FSR
7
PCMR
BCLKR
PUI
8
9
10
SOG/SSOP/TSSOP
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W681512
6. PIN DESCRIPTION
Pin
Name
Pin Functionality
No.
RO+
1
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to
1.575 volt peak referenced to the analog ground level.
RO-
2
Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 1.575
volt peak referenced to the analog ground level.
PAI
3
4
This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced
to the VAG voltage level.
PAO+
5
Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak
referenced to the VAG voltage level.
VDD
6
7
Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.
FSR
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCMR
8
9
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD
.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10
11
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,
the part is powered down.
MCLK
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have
the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the
case of 256 and 512 kHz frequency.
BCLKT
PCMT
FST
12
13
14
15
16
PCM transmit bit clock input pin.
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
This is the supply ground. This pin should be connected to 0V.
VSS
μ/A-Law
Compander mode select pin. μ-Law companding is selected when this pin is tied to VDD. A-Law
companding is selected when this pin is tied to VSS.
AO
AI-
17
18
19
20
Analog output of the first gain stage in the transmit path.
Inverting input of the first gain stage in the transmit path.
Non-inverting input of the first gain stage in the transmit path.
AI+
VAG
Mid-Supply analog ground pin, which supplies a 2.4 Volt reference voltage for all-analog signal
processing. This pin should be decoupled to VSS with a 0.01μF to 0.1 μF capacitor. This pin
becomes high impedance when the chip is powered down.
Publication Release Date: April, 2007
- 7 -
Revision C14
W681512
7. FUNCTIONAL DESCRIPTION
W681512 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC
complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a
complete μ-Law and A-Law compander. The μ-Law and A-Law companders are designed to comply
with the specifications of the ITU-T G.711 recommendation.
The block diagram in section 3 shows the main components of the W681512. The chip consists of a
PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats.
The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample
rate with the external frame sync frequency. The power conditioning block provides the internal
power supply for the digital and the analog section, while the voltage reference block provides a
precision analog ground voltage for the analog signal processing. The main CODEC block diagram
is shown in section 3.
+
-
VAG
PAO+
-
PAO
PAI
Receive Path
8
+
-
+
-
RO
RO
D/A
Converter
fC
= 3400Hz
Smoothing
Smoothing
/A-
μ
Filter
Filter
Control
Transmit Path
AO
AI+
8
A/D
+
Converter
f
C
f
C
= 3400Hz
= 200Hz
-
AI
μ
-
/A
HighPass
Filter
Ant
-Aliasing
Ant
-Aliasing
Control
Filter
Filter
Figure 7.1 The W681512 Signal Path
7.1. Transmit Path
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain
setting (see application examples in section 11). The device has an input operational amplifier whose
output is the input to the encoder section. If the input amplifier is not required for operation it can be
powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or
the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The
input amplifier can be powered down by connecting the AI+ pin to VDD or VSS. The AO pin is selected
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W681512
as an input when AI+ is tied to VDD and the AI- pin is selected as an input when AI+ is tied to VSS (see
Table 7.1).
AI+
Input Amplifier
Input
VDD
Powered Down
Powered Up
AO
1.2 to VDD-1.2
VSS
AI+, AI-
AI-
Powered Down
Table 7.1 Input Amplifier Modes of operation
When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the
analog ground voltage VAG
.
The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched
capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of
input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is
filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the
recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is
digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or A-
Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression
format can be selected according to Table 7.2.
Format
μ/A-Law Pin
VSS
VDD
A-Law
μ-Law
Table 7.2. Pin-selectable Compression Format
The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the
data rate supplied by the external BCLKT.
7.2. Receive Path
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the differential receive output signals RO+ and RO-. The RO+ or RO- outputs can
be externally connected to the PAI pin to provide a differential output with high driving capability at the
PAO+ and PAO- pins. By using external resistors (see section 11 for examples), various gain settings
Publication Release Date: April, 2007
- 9 -
Revision C14
W681512
of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered
down by connecting PAI to VDD
.
7.3. POWER MANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681512 must be 5V +/- 10%. This supply
voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF
ceramic capacitor.
7.3.2. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the VAG pin. This voltage
needs to be decoupled to VSS through a 0.01 μF to a 0.1 μF ceramic capacitor.
7.4. PCM INTERFACE
The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.3.
BCLKR
FSR
Interface Mode
64 kHz to 4.096 MHz 8 kHz
Long or Short Frame Sync
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VDD
ISDN GCI with active channel B1
ISDN GCI with active channel B2
ISDN IDL with active channel B1
ISDN IDL with active channel B2
Table 7.3 PCM Interface mode selections
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8
kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC
sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when
the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The
length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge
occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin
- 10 -
W681512
PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data
word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame
Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted.
The internal decision logic will determine whether the next frame sync is a long or a short frame sync,
based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high
impedance for two frame sync cycles after every power down state. More detailed timing information
can be found in the interface timing section.
7.4.2. Short Frame Sync
The W681512 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is
HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge
of the bit-clock, the W681512 starts clocking out the data on the PCMT pin, which will also change
from high to low impedance state. The data transmit pin PCMT will go back to the high impedance
state halfway through the LSB. The Short Frame Sync operation of the W681512 is based on an 8-bit
data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after
the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine
whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every
power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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Revision C14
W681512
7.4.4. Interchip Digital Link (IDL)
The IDL interface mode is selected when the BCLKR pin is connected to VDD for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface
consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR
pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the
first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK
cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after
the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK
after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the
IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when
not used for data transmission and also in the time slot of the unused channel. For more timing
information, see the timing section.
7.4.5. System Timing
The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz
master clock rates. The system clock is supplied through the master clock input MCLK and can be
derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and 8
kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency
versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW
for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the
W681512 will enter the low power standby mode. Another way to power down is to set the PUI pin to
LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will
become low impedance.
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W681512
8. TIMING DIAGRAMS
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFSL
FST
TFTRH
TFTRS
TFTFH
TBCKH
TBCKL
BCLKT
PCMT
0
1
2
3
4
5
6
7
8
0
1
TFDTD
TBDTD
THID
THID
TBCK
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
TFS
TFSL
FSR
TFRRH
TFRRS
TFRFH
TBCKH
TBCKL
BCLKR
PCMR
0
1
2
3
4
5
6
7
8
0
1
TBCK
D7 D6 D5 D4 D3 D2 D1 D0
LSB
MSB
TDRH
TDRS
Figure 8.1 Long Frame Sync PCM Timing
Publication Release Date: April, 2007
Revision C14
- 13 -
W681512
SYMBOL
1/TFS
DESCRIPTION
MIN
---
TYP
MAX UNIT
FST, FSR Frequency
8
---
kHz
sec
TFSL
FST / FSR Minimum LOW Width 1
BCLKT, BCLKR Frequency
BCLKT, BCLKR HIGH Pulse Width
BCLKT, BCLKR LOW Pulse Width
TBCK
64
1/TBCK
TBCKH
TBCKL
---
---
---
---
4096 kHz
50
---
---
---
ns
ns
ns
50
TFTRH
BCLKT 0 Falling Edge to FST Rising
Edge Hold Time
20
TFTRS
TFTFH
TFDTD
TBDTD
THID
FST Rising Edge to BCLKT 1 Falling
edge Setup Time
80
50
---
---
10
---
---
---
---
---
---
---
60
60
60
ns
ns
ns
ns
ns
BCLKT 2 Falling Edge to FST Falling
Edge Hold Time
FST Rising Edge to Valid PCMT Delay
Time
BCLKT Rising Edge to Valid PCMT
Delay Time
Delay Time from the Later of FST
Falling Edge, or
BCLKT 8 Falling Edge to PCMT Output
High Impedance
TFRRH
TFRRS
TFRFH
TDRS
BCLKR 0 Falling Edge to FSR Rising
Edge Hold Time
20
80
50
0
---
---
---
---
---
---
---
---
---
---
ns
ns
ns
ns
ns
FSR Rising Edge to BCLKR 1 Falling
edge Setup Time
BCLKR 2 Falling Edge to FSR Falling
Edge Hold Time
Valid PCMR to BCLKR Falling Edge
Setup Time
TDRH
PCMR Hold Time from BCLKR Falling
Edge
50
Table 8.1 Long Frame Sync PCM Timing Parameters
1 TFSL must be at least ≥ TBCK
- 14 -
W681512
TFTRHM
TFTRSM
TMCKL
TMCKH
TRISE
TFALL
MCLK
TMCK
TFS
TFTFH
TFTFS
FST
TFTRS
TFTRH
TBCKH
TBCKL
BCLKT
PCMT
0
1
-1
0
1
2
3
4
5
6
7
8
TBCK
TBDTD
TBDTD
THID
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
TFS
TFRFH
TFRFS
FSR
TFRRS
TFRRH
TBCKH
TBCKL
BCLKR
PCMR
0
1
-1
0
1
2
3
4
5
6
7
8
TBCK
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
TDRH
TDRS
Figure 8.2 Short Frame Sync PCM Timing
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Revision C14
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W681512
SYMBOL
1/TFS
DESCRIPTION
MIN
---
TYP
8
MAX UNIT
FST, FSR Frequency
---
kHz
1/TBCK
TBCKH
BCLKT, BCLKR Frequency
BCLKT, BCLKR HIGH Pulse Width
BCLKT, BCLKR LOW Pulse Width
64
50
50
20
---
---
---
---
4096 kHz
---
---
---
ns
ns
ns
TBCKL
TFTRH
BCLKT –1 Falling Edge to FST Rising Edge Hold
Time
TFTRS
FST Rising Edge to BCLKT 0 Falling edge Setup
Time
80
---
---
ns
TFTFH
TFTFS
BCLKT 0 Falling Edge to FST Falling Edge Hold Time
50
50
---
---
---
---
ns
ns
FST Falling Edge to BCLKT 1 Falling Edge Setup
Time
TBDTD
THID
BCLKT Rising Edge to Valid PCMT Delay Time
10
10
---
---
60
60
ns
ns
Delay Time from BCLKT 8 Falling Edge to PCMT
Output High Impedance
TFRRH
TFRRS
BCLKR –1 Falling Edge to FSR Rising Edge Hold
Time
20
80
---
---
---
---
ns
ns
FSR Rising Edge to BCLKR 0 Falling edge Setup
Time
TFRFH
TFRFS
BCLKR 0 Falling Edge to FSR Falling Edge Hold Time
50
50
---
---
---
---
ns
ns
FSR Falling Edge to BCLKR 1 Falling Edge Setup
Time
TDRS
TDRH
Valid PCMR to BCLKR Falling Edge Setup Time
PCMR Hold Time from BCLKR Falling Edge
0
---
---
---
---
ns
ns
50
Table 8.2 Short Frame Sync PCM Timing Parameters
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W681512
TFS
FST
BCLKT
PCMT
TFSFH
TFSRS
TFSRH
-1
TBCKH
TBCKL
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
TBCK
THID
TBDTD
TBDTD
THID
TBDTD
TBDTD
D7 D6 D5
D4 D3 D2 D1 D0
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB
TDRS
TDRH
TDRS
TDRH
D7
PCMR
D6 D5
D4 D3 D2 D1 D0
LSB
D7 D6 D5 D4 D3 D2
MSB
D1 D0
MSB
LSB
BCH = 0
BCH = 1
B1 Channel
B2 Channel
Figure 8.3 IDL PCM Timing
SYMBOL DESCRIPTION
MIN
---
TYP
MAX
---
UNIT
kHz
kHz
ns
1/TFS
1/TBCK
TBCKH
TBCKL
TFSRH
FST Frequency
8
BCLKT Frequency
256
50
---
---
---
---
4096
---
BCLKT HIGH Pulse Width
BCLKT LOW Pulse Width
50
---
ns
BCLKT –1 Falling Edge to FST Rising Edge
Hold Time
20
---
ns
TFSRS
TFSFH
TBDTD
THID
FST Rising Edge to BCLKT 0 Falling edge
Setup Time
60
20
10
10
---
---
---
---
---
---
60
50
ns
ns
ns
ns
BCLKT 0 Falling Edge to FST Falling Edge
Hold Time
BCLKT Rising Edge to Valid PCMT Delay
Time
Delay Time from the BCLKT 8 Falling Edge
(B1 channel) or BCLKT 18 Falling Edge (B2
Channel) to PCMT Output High Impedance
TDRS
TDRH
Valid PCMR to BCLKT Falling Edge Setup
Time
20
75
---
---
---
---
ns
ns
PCMR Hold Time from BCLKT Falling Edge
Table 8.3 IDL PCM Timing Parameters
Publication Release Date: April, 2007
Revision C14
- 17 -
W681512
TFS
FST
BCLKT
PCMT
TFSFH
TFSRS
TBCKH
TBCKL
TFSRH
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
THID
TFDTD
D7
TBDTD
D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
MSB
THID
TBDTD
TBDTD
TBCK
D6 D5
D1 D0
LSB
MSB
LSB
TDRS
TDRH
TDRS
TDRH
D7
D6 D5
PCMR
D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
MSB
D1 D0
MSB
LSB
LSB
BCH = 0
BCH = 1
B1 Channel
B2 Channel
Figure 8.4 GCI PCM Timing
SYMBOL
1/TFST
1/TBCK
TBCKH
TBCKL
DESCRIPTION
MIN
---
TYP
8
MAX UNIT
FST Frequency
---
kHz
BCLKT Frequency
BCLKT HIGH Pulse Width
BCLKT LOW Pulse Width
512
50
50
20
60
20
---
---
---
---
---
---
---
---
---
---
6176 kHz
---
---
---
---
---
60
60
50
ns
ns
ns
ns
ns
ns
ns
ns
TFSRH
TFSRS
TFSFH
BCLKT 0 Falling Edge to FST Rising Edge Hold Time
FST Rising Edge to BCLKT 1 Falling edge Setup Time
BCLKT 1 Falling Edge to FST Falling Edge Hold Time
FST Rising Edge to Valid PCMT Delay Time
TFDTD
TBDTD
THID
BCLKT Rising Edge to Valid PCMT Delay Time
---
Delay Time from the BCLKT 16 Falling Edge (B1
channel) or BCLKT 32 Falling Edge (B2 Channel) to
PCMT Output High Impedance
10
TDRS
TDRH
Valid PCMR to BCLKT Rising Edge Setup Time
PCMR Hold Time from BCLKT Rising Edge
Table 8.4 GCI PCM Timing Parameters
20
---
---
---
---
ns
ns
60
- 18 -
W681512
SYMBOL
DESCRIPTION
MIN
TYP
256
MAX
UNIT
1/TMCK
Master Clock Frequency
---
---
kHz
512
1536
1544
2048
2560
4096
TMCKH
TMCK
/
MCLK Duty Cycle for 256 kHz
Operation
45%
50
55%
---
TMCKH
TMCKL
TFTRHM
TFTRSM
Minimum Pulse Width HIGH for
MCLK(512 kHz or Higher)
---
---
---
---
ns
ns
ns
ns
Minimum Pulse Width LOW for MCLK
(512 kHz or Higher)
50
---
MCLK falling Edge to FST Rising Edge
Hold Time
50
---
FST Rising Edge to MCLK Falling edge
Setup Time
50
---
TRISE
TFALL
Rise Time for All Digital Signals
Fall Time for All Digital Signals
---
---
---
---
50
50
ns
ns
Table 8.5 General PCM Timing Parameters
Publication Release Date: April, 2007
Revision C14
- 19 -
W681512
9. ABSOLUTE MAXIMUM RATINGS
9.1. ABSOLUTE MAXIMUM RATINGS
Condition
Junction temperature
Value
1500C
-650C to +1500C
Storage temperature range
Voltage Applied to any pin
(VSS - 0.3V) to (VDD + 0.3V)
(VSS – 1.0V) to (VDD + 1.0V)
-0.5V to +6V
Voltage applied to any pin (Input current limited to +/-20 mA)
VDD - VSS
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
9.2. OPERATING CONDITIONS
Condition
Industrial operating temperature
Supply voltage (VDD
Ground voltage (VSS)
Value
-400C to +850C
)
+4.5V to +5.5V
0V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device.
- 20 -
W681512
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS
Symbol Parameters
Conditions
Min (2) Typ (1)
Max (2)
Units
VIL
Input LOW Voltage
0.6
V
V
V
V
VIH
VOL
VOH
Input HIGH Voltage
2.4
PCMT Output LOW Voltage
PCMT Output HIGH Voltage
IOL = 3 mA
0.4
IOL = -3 mA
VDD
–
0.4
V
DD Current (Operating) - ADC + DAC
6
8
mA
IDD
ISB
No Load
VDD Current (Standby)
FST & FSR =Vss ;
PUI=VDD
10
100
μA
Ipd
IIL
VDD Current (Power Down)
Input Leakage Current
PUI= Vss
0.1
10
μA
μA
μA
VSS<VIN<VDD
+/-10
+/-10
VSS<PCMT<VDD
High Z State
IOL
PCMT Output Leakage Current
CIN
Digital Input Capacitance
10
15
pF
pF
COUT
PCMT Output Capacitance
PCMT High Z
1. Typical values: TA = 25°C , VDD = 5.0 V
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
Publication Release Date: April, 2007
- 21 -
Revision C14
W681512
10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG
MCLK=BCLK= 2.048MHz; FST=FSR=8kHz synchronous operation
;
PARAMETER SYM.
CONDITION
TYP.
TRANSMIT
(A/D)
RECEIVE
(D/A)
UNIT
MIN.
MAX.
MIN.
MAX.
Absolute
Level
LABS
1.096
0.775
---
---
---
---
VPK
0 dBm0 = 0dBm @ 600Ω
VRMS
Max. Transmit TXMAX
Level
1.579
1.573
---
---
---
---
---
---
---
---
VPK
VPK
3.17 dBm0 for μ-Law
3.14 dBm0 for A-Law
Absolute Gain GABS
(0 dBm0 @
1020 Hz;
0 dBm0 @ 1020 Hz;
TA=+25°C
0
-0.25
+0.25 -0.25 +0.25 dB
TA=+25°C)
Absolute Gain GABST
variation with
Temperature
0
-0.03
-0.05
+0.03 -0.03 +0.03 dB
+0.05 -0.05 +0.05
TA=0°C to TA=+70°C
TA=-40°C to TA=+85°C
Frequency
Response,
GRTV
15 Hz
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
-40
-30
-26
-0.4
-0.5
-0.5
-0.5
-0.5
0
0
0
0
dB
50 Hz
Relative to
0dBm0 @
1020 Hz
60 Hz
---
200 Hz
-1.0
-0.20
-0.35
-0.8
---
300 to 3000 Hz
3300 Hz
+0.15 -0.20 +0.15
+0.15 -0.35 +0.15
3400 Hz
0
-0.8
---
0
3600 Hz
0
0
4000 Hz
---
-14
-32
+0.3
+0.6
+1.6
---
-14
-30
+0.2
+0.4
+1.6
4600 Hz to 100 kHz
+3 to –40 dBm0
-40 to –50 dBm0
-50 to –55 dBm0
---
---
Gain Variation GLT
vs. Level Tone
-0.3
-0.6
-1.6
-0.2
-0.4
-1.6
dB
(1020 Hz
relative to –10
dBm0)
- 22 -
W681512
10.3. ANALOG DISTORTION AND NOISE PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG
MCLK=BCLK= 2.048MHz; FST=FSR=8kHz synchronous operation
;
PARAMETER
SYM.
CONDITION
TRANSMIT (A/D)
MIN. TYP. MAX.
RECEIVE (D/A)
TYP. MAX.
UNIT
MIN.
34
36
30
25
34
36
30
25
---
Total Distortion vs.
Level Tone (1020 Hz,
μ-Law, C-Message
Weighted)
+3 dBm0
36
36
29
25
36
36
29
25
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
-47
---
---
---
---
---
---
---
---
---
---
---
---
---
---
dBC
DLTμ
0 dBm0 to -30 dBm0
-40 dBm0
---
-45 dBm0
---
Total Distortion vs.
Level Tone (1020 Hz,
A-Law, Psophometric
Weighted)
DLTA
+3 dBm0
---
dBp
dB
0 dBm0 to -30 dBm0
-40 dBm0
---
---
-45 dBm0
---
Spurious Out-Of-Band DSPO
at RO+ (300 Hz to
3400 Hz @ 0dBm0)
4600 Hz to 7600 Hz
7600 Hz to 8400 Hz
8400 Hz to 100000 Hz
300 to 3000 Hz
-30
-40
-30
-47
---
---
Spurious In-Band (700 DSPI
Hz to 1100 Hz @
0dBm0)
---
dB
dB
Intermodulation
Distortion (300 Hz to
3400 Hz –4 to –21
dBm0
DIM
Two tones
---
---
-41
---
---
-41
Crosstalk (1020 Hz @ DXT
0dBm0)
---
---
---
---
-75
---
---
---
---
-75
dBm0
Absolute Group Delay
1200Hz
360
240
μsec
μsec
τABS
Group Delay
500 Hz
---
---
---
---
---
---
---
---
---
---
---
---
---
---
750
380
130
130
750
18
---
---
---
---
---
---
---
---
---
---
---
---
---
---
750
370
120
120
750
13
τD
Distortion (relative to
group delay @ 1200
Hz)
600 Hz
1000 Hz
2600 Hz
2800 Hz
Idle Channel Noise
NIDL
dBrnc0
dBm0p
μ-Law; C-message
-68
-78
A-Law; Psophometric
Publication Release Date: April, 2007
Revision C14
- 23 -
W681512
10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS
VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG
;
PARAMETER
AI Input Offset Voltage
AI Input Current
SYM.
VOFF,AI
CONDITION
MIN.
---
TYP.
MAX.
UNIT.
mV
μA
AI+, AI-
AI+, AI-
---
±0.1
---
±25
±1.0
---
IIN,AI
---
AI Input Resistance
AI Input Capacitance
RIN,AI
CIN,AI
VCM,AI
AI+, AI- to VAG
AI+, AI-
10
MΩ
pF
---
---
10
AI Common Mode Input Voltage
Range
AI+, AI-
1.2
---
VDD-1.2
V
AI Common Mode Rejection Ratio
AI Amp Gain Bandwidth Product
AI Amp DC Open Loop Gain
AI Amp Equivalent Input Noise
AO Output Voltage Range
CMRRTI
GBWTI
GTI
AI+, AI-
---
---
---
60
2150
95
---
---
---
dB
kHz
dB
AO, RLD≥10kΩ
AO, RLD≥10kΩ
C-Message Weighted
RLD=10kΩ to VAG
RLD=2kΩ to VAG
AO, RO to VAG
AO
NTI
---
-24
---
---
dBrnC
V
VTG
0.5
1.0
VDD-0.5
VDD-1.0
---
Load Resistance
RLDTGRO
CLDTGAO
CLDTGRO
IOUT1
2
---
---
---
---
---
---
100
500
---
kΩ
pF
Load Capacitance
Load Capacitance
AO & RO Output Current
RO
---
pF
mA
0.5 ≤AO,RO+, RO-≤ VDD
0.5
-
±1.0
RO+, RO- Output Resistance
RO+, RO- Output Offset Voltage
Analog Ground Voltage
RRO+, RO-
VOFF,RO+,RO-
VAG
RO+, RO-, 0 to 3400 Hz
RO+ to VAG
---
---
1
---
±25
2.6
Ω
mV
V
---
Relative to VSS
2.2
---
2.4
2.5
VAG Output Resistance
RVAG
12.5
Within ±25mV change
Transmit
Ω
Power Supply Rejection Ratio (0 to PSRR
100 kHz to VDD, C-message)
30
30
---
80
75
---
---
---
dBC
Receive
PAI Input Offset Voltage
PAI Input Current
VOFF,PAI
IIN,PAI
PAI
mV
μA
±25
±1.0
---
PAI
---
10
±0.05
---
PAI Input Resistance
PAI Amp Gain Bandwidth Product
Output Offset Voltage
Load Resistance
RIN,PAI
GBWPI
VOFF,PO
RLDPO
CLDPO
IOUTPO
PAI to VAG
PAO- no load
PAO+ to PAO-
MΩ
kHz
mV
Ω
---
1000
---
---
---
±50
---
PAO+, PAO- differentially
PAO+, PAO- differentially
300
---
---
Load Capacitance
---
1000
---
pF
PO Output Current
---
mA
V
SS + 0.7 ≤PAO- or PAO+≤
±10.0
VDD-0.7
PO Output Resistance
RPO
PAO+ to PAO-
---
1
---
Ω
- 24 -
W681512
PARAMETER
PO Differential Gain
SYM.
CONDITION
MIN.
TYP.
MAX.
UNIT.
GPO
-0.2
0
+0.2
dB
RLD=300Ω, +3dBm0, 1 kHz,
PAO+ to PAO-
PO Differential Signal to Distortion
C-Message weighted
DPO
45
---
---
60
40
40
---
---
---
dBC
dB
ZLD=300Ω
ZLD=100nF + 100Ω
ZLD=100nF + 20Ω
0 to 4 kHz
PO Power Supply Rejection Ratio
(0 to 25 kHz to VDD, Differential
out)
PSRRPO
40
---
55
40
---
---
4 to 25 kHz
Publication Release Date: April, 2007
Revision C14
- 25 -
W681512
10.5. DIGITAL I/O
10.5.1. μ-Law Encode Decode Characteristics
Normalized
Normalized
Encode
Decision
Levels
Digital Code
Decode
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
0
Step
Step
Step
8159
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
8031
:
7903
:
4319
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4191
:
4063
:
2143
2079
:
2015
:
1055
1023
:
991
:
511
495
:
479
:
239
231
:
223
:
103
99
:
95
:
35
33
:
31
:
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values
- 26 -
W681512
10.5.2. A-Law Encode Decode Characteristics
Normalized
Digital Code
Normalized
Encode
Decision
Levels
Decode
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
1
Step
Step
Step
4096
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032
3968
:
:
2048
0
0
0
0
0
0
0
2112
:
2048
:
1088
1056
:
1024
:
544
528
:
512
:
272
264
:
256
:
136
132
:
128
:
68
66
:
64
:
2
0
1
Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits
Publication Release Date: April, 2007
Revision C14
- 27 -
W681512
10.5.3. PCM Codes for Zero and Full Scale
A-Law
μ-Law
Level
Sign bit
Chord bits
Step bits
Sign bit
Chord bits
(D6,D5,D4)
010
Step bits
(D3,D2,D1,D0)
1010
(D7)
(D6,D5,D4) (D3,D2,D1,D0)
(D7)
+ Full Scale
+ Zero
1
1
0
0
000
111
111
000
0000
1111
1111
0000
1
1
0
0
101
0101
- Zero
101
0101
- Full Scale
010
1010
10.5.4. PCM Codes for 0dBm0 Output
A-Law
Chord bits
(D6,D5,D4)
011
μ-Law
Sample
Sign bit Chord bits
Step bits
Sign bit
Step bits
(D3,D2,D1,D0)
0100
(D7)
0
(D6,D5,D4) (D3,D2,D1,D0)
(D7)
0
1
2
3
4
5
6
7
8
001
000
000
001
001
000
000
001
1110
1011
1011
1110
1110
1011
1011
1110
0
0
010
0001
0
0
010
0001
0
0
011
0100
1
1
011
0100
1
1
010
0001
1
1
010
0001
1
1
011
0100
- 28 -
W681512
11. TYPICAL APPLICATION CIRCUIT
VDD
0.1 uF
U2
27K
17
18
19
AO
AI-
AI+
1.0 uF
27K
14
12
13
8 KHz Frame Sy nc
FST
BCLKT
PCMT
-
DIFFERENTIAL
AUDIO IN
+
2.048 MHz
Bit Clock
27K
11
MCLK
1.0 uF 27K
20
2
PCM OUT
PCM IN
VAG
RO-
8
9
7
PCMR
BCLKR
FSR
1
3
4
5
RO+
PAI
0.01 uF
VDD
16
10
MODE SELECT
POWER CONTROL
PAO-
u/A
PUI
PAO+
-
DIFFERENTIAL
W681512
AUDIO OUT
RL > 2K ohms
+
Figure 11.1 Typical circuit for Differential Analog I/O’s
VDD
0.1 uF
U3
27K
17
AO
1.0 uF
27K
27K
14
12
13
8 KHz Frame Sync
FST
BCLKT
PCMT
18
19
AI-
AUDIO IN
2.048 MHz
Bit Clock
AI+
27K
11
MCLK
1.0 uF
20
2
PCM OUT
PCM IN
VAG
RO-
8
9
7
PCMR
BCLKR
FSR
1
3
4
5
RO+
PAI
0.01 uF
27K
27K
AUDIO OUT
RL > 2K ohms
16
10
MODE SELECT
POWER CONTROL
PAO-
u/A
PUI
PAO+
AUDIO OUT
RL > 150 ohms
100 uF
W681512
Figure 11.2 Typical circuit for Single Ended Analog I/O’s
Publication Release Date: April, 2007
Revision C14
- 29 -
W681512
VDD
1.5K
1K
0.1 uF
22 uF
62K
U4
17
18
19
AO
AI-
AI+
+
1.0 uF
1.0 uF
14
12
13
8 KHz Frame Sy nc
FST
BCLKT
PCMT
3.9K
100pF
100pF
2.048 MHz
Bit Clock
3.9K
11
MCLK
ELECTRET
MICROPHONE
20
2
PCM OUT
PCM IN
VAG
RO-
62K
8
9
7
PCMR
BCLKR
FSR
0.01 uF
1
3
4
5
RO+
PAI
27K
27K
27K
1.5K
16
10
MODE SELECT
POWER CONTROL
PAO-
u/A
PUI
PAO+
W681512
SPEAKER
Figure 11.3 Handset Interface
VDD
0.1 uF
U5
27K
17
AO
27K
14
12
13
8 KHz Frame Sync
FST
BCLKT
PCMT
18
AI-
2.048 MHz
Bit Clock
1.0 uF
19
AI+
11
MCLK
20
PCM OUT
PCM IN
VAG
2
8
9
7
RO-
PCMR
BCLKR
FSR
600
27K
27K
1
3
4
5
RO+
PAI
0.01 uF
TRANSFORMER
600 OHM 1:1
B1/B2 SELECT
MODE SELECT
16
10
PAO-
u/A
PUI
POWER CONTROL
PAO+
W681512
Figure 11.4 Transformer Interface Circuit in GCI mode
- 30 -
W681512
12. PACKAGE SPECIFICATION
12.1. 20L SOG (SOP)-300MIL
SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS
11
c
20
E
H
E
L
1
10
O
D
0.25
A
Y
SEATING PLANE
e
GAUGE PLANE
A1
b
Publication Release Date: September, 2005
Revision C13
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W681512
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
2.35
0.10
0.33
0.23
7.40
12.60
MAX.
2.65
0.30
0.51
0.32
7.60
13.00
MIN.
MAX.
0.104
0.012
0.020
0.013
0.299
0.512
A
A1
b
0.093
0.004
0.013
0.009
0.291
0.496
c
E
D
e
1.27 BSC
0.050 BSC
HE
Y
10.00
-
10.65
0.10
1.27
8º
0.394
-
0.419
0.004
0.050
8º
L
0.40
0º
0.016
0º
0
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W681512
12.2. 20L SSOP-209 MIL
SHRINK SMALL OUTLINE PACKAGE DIMENSIONS
D
11
20
DTEAIL A
HE
E
1
10
b
A
A2
SEATING PLANE
SEATING PLANE
θ
L
Y
L1
e
b
A1
DETAIL A
Publication Release Date: September, 2005
Revision C13
- 33 -
W681512
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
-
NOM.
MAX.
2.00
-
MIN.
-
NOM.
MAX.
0.079
A
A1
A2
b
-
-
0.05
1.65
0.22
0.09
6.90
5.00
7.40
-
-
0.002
0.065
0.009
0.004
0.272
0.197
0.291
-
-
0.069
-
-
1.75
-
1.85
0.38
0.25
7.50
5.60
8.20
-
-
0.015
0.010
0.295
0.220
0.323
-
c
-
-
D
7.20
5.30
7.80
0.65
0.75
1.25
-
0.283
0.209
0.307
0.0256
0.030
0.050
-
E
HE
e
L
0.55
-
0.95
-
0.021
-
0.037
-
L1
Y
-
0.10
8º
-
0.004
8º
0
0º
-
0
-
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W681512
12.3. 20L TSSOP - 4.4X6.5MM
PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
-
NOM.
-
MAX.
1.20
MIN.
-
NOM.
-
MAX.
A
A1
A2
E
0.047
0.006
0.041
0.177
0.05
0.80
4.30
-
0.15
1.05
4.50
0.002
0.031
0.169
-
0.035
0.90
4.40
0.173
HE
D
6.40 BSC
.252 BSC
0.256
6.40
0.50
6.50
6.60
0.75
0.252
0.020
0.260
0.030
L
0.60
0.024
L1
b
1.00 REF
0.039 REF
-
0.19
-
0.30
0.007
0.012
e
0.65 BSC
0.026 BSC
-
c
0.09
0º
-
0.20
8º
0.004
0º
0.008
8º
0
-
-
Y
0.10 BASIC
0.004 BASIC
Publication Release Date: September, 2005
Revision C13
- 35 -
W681512
13. ORDERING INFORMATION
Winbond Part Number Description
W681512_ _
Product Family
W681512 Product
Package Material:
Blank
=
=
Standard Package
Pb-free Package
G
Package Type:
S
=
=
=
20-Lead Plastic Small Outline Package (SOG/SOP)
R
20-Lead Plastic Shrink Small Outline Package (SSOP)
WG
20-Lead Free Plastic Thin Shrink Small Outline Package (TSSOP)
When ordering W681512 series devices, please refer to the following part numbers.
Part Number
W681512S*
W681512R*
W681512SG
W681512RG
W681512WG
*All Pb packages will be available for a limited time. Thus, Pb-free
packages are strongly recommended.
- 36 -
W681512
14. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A10
March 25,
2003
First revision
A11
B11
April 2,
2003
7
VAG: fixed the voltage value from 2.5V to 2.4V
July, 2004
2
6
Added reference to SSOP package. Revised Applications
section.
Added reference to SSOP package.
32
33
Added description of SSOP package.
Added R package ordering code.
C11
November,
2004
2
Added reference to TSSOP package and Pb-free packaging.
Added reference to TSSOP package.
Added description of TSSOP package.
Added W and G package ordering code.
Extended conditions on Table 10.2.
6
32
33
22
23
Extended conditions on Table 10.3.
Corrected Idle Channel Noise min/max and units.
29
30
Improved Application Diagram.
Improved Application Diagram.
Add Important Notice
C12
C13
April 2005
37
September
, 2005
29, 30
Improved Applications Diagram
Various Capilatized Logic HIGH/LOW
2, 22
31
Added reference to VRMS
C14
April, 2007
SOP Package diagram legible
SSOP Package diagram legible
TSSOP Package diagram legible
Removed Pb TSSOP Package
Footnote on Pb parts limited availability
33
35
36
36
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
Publication Release Date: September, 2005
- 37 -
Revision C13
W681512
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
The information contained in this datasheet may be subject to change without
notice. It is the responsibility of the customer to check the Winbond USA website
(www.winbond-usa.com) periodically for the latest version of this document, and
any Errata Sheets that may be generated between datasheet revisions.
- 38 -
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