W78LE516A24DL [WINBOND]
Microcontroller;
| 型号： | W78LE516A24DL |
| 厂家： | 
WINBOND |
| 描述： | Microcontroller 微控制器 |
| 文件： | 总37页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78LE516 Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES................................................................................................................................. 3
PIN CONFIGURATIONS ............................................................................................................ 4
PIN DESCRIPTION..................................................................................................................... 6
BLOCK DIAGRAM ...................................................................................................................... 7
FUNCTIONAL DESCRIPTION ................................................................................................... 8
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
RAM................................................................................................................................ 8
Timers 0, 1, and 2........................................................................................................... 8
Clock............................................................................................................................... 9
Crystal Oscillator............................................................................................................. 9
External Clock................................................................................................................. 9
Power Management........................................................................................................ 9
Reduce EMI Emission .................................................................................................... 9
Reset............................................................................................................................. 10
Port 4 ............................................................................................................................ 11
6.10
INT2 /INT3 ................................................................................................................... 11
6.11 Port 4 Base Address Registers .................................................................................... 13
6.12 In-System Programming (ISP) Mode............................................................................ 15
6.13 In-System Programming Control Register (CHPCON)................................................. 17
7.
SECURITY................................................................................................................................ 21
7.1
7.2
7.3
7.4
Lock bit.......................................................................................................................... 21
MOVC Inhibit................................................................................................................. 21
Encryption..................................................................................................................... 21
Oscillator Control .......................................................................................................... 22
8.
9.
ELECTRICAL CHARACTERISTICS......................................................................................... 22
8.1
8.2
8.3
Absolute Maximum Ratings.......................................................................................... 22
D.C. Characteristics...................................................................................................... 22
A.C. Characteristics...................................................................................................... 24
TIMING WAVEFORMS............................................................................................................. 26
9.1
9.2
9.3
9.4
Program Fetch Cycle.................................................................................................... 26
Data Read Cycle........................................................................................................... 26
Data Write Cycle........................................................................................................... 27
Port Access Cycle......................................................................................................... 27
Publication Release Date: February 15, 2005
- 1 -
Revision A5
W78LE516
10.
11.
TYPICAL APPLICATION CIRCUIT........................................................................................... 28
10.1 External Program Memory and Crystal ........................................................................ 28
10.2 Expanded External Data Memory and Oscillator ......................................................... 29
PACKAGE DIMENSIONS......................................................................................................... 30
11.1 40-pin DIP..................................................................................................................... 30
11.2 44-pin PLCC ................................................................................................................. 30
11.3 44-pin PQFP ................................................................................................................. 31
11.4 48-pin LQFP.................................................................................................................. 31
12.
13.
APPLICATION NOTE: IN-SYSTEM PROGRAMMING SOFTWARE EXAMPLES .................. 32
REVISION HISTORY................................................................................................................ 37
- 2 -
W78LE516
1. GENERAL DESCRIPTION
The W78LE516 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78LE516 is fully compatible with the standard 8052.
The W78LE516 contains a 64K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash
EPROM which allows the contents of the 64KB main Flash EPROM to be updated by the loader
program located at the 4KB auxiliary Flash EPROM; 512 bytes of on-chip RAM; four 8-bit bi-
directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a
serial port. These peripherals are supported by a eight sources two-level interrupt capability. To
facilitate programming and verification, the Flash EPROM inside the W78LE516 allows the program
memory to be programmed and read electronically. Once the code is confirmed, the user can protect
the code for security.
The W78LE516 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
•
Fully static design 8-bit CMOS microcontroller
•
64K bytes of in-system programmable Flash EPROM for Application Program (AP FLASH
EPROM)
•
•
•
•
•
•
•
•
•
•
•
4K bytes of auxiliary Flash EPROM for Loader Program (LD FLASH EPROM)
512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)
64K bytes program memory address space and 64K bytes data memory address space
Four 8-bit bi-directional ports
One 4-bit multipurpose programmable port
Three 16-bit timer/counters
One full duplex serial port
Eight-sources, two-level interrupt capability
Built-in power management
Code protection
Packaged in
− DIP 40: W78LE516-24
− PLCC 44: W78LE516P-24
− QFP 44: W78LE516F-24
− LQFP 48: W78LE516D-24
− Lead Free DIP 40: W78L516A24DL
− Lead Free PLCC 44: W78L516A24PL
− Lead Free QFP 44: W78L516A24FL
− Lead Free LQFP 48: W78L516A24LL
Publication Release Date: February 15, 2005
- 3 -
Revision A5
W78LE516
3. PIN CONFIGURATIONS
40-Pin DIP (W78LE516)
1
2
3
4
5
6
7
8
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
T2EX, P1.1
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin PLCC (W78LE516P)
/
T
2
E
X
,
I
A
D
3
,
A
D
0
,
A
D
1
,
A
D
2
,
N
T
3
,
T
2
,
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
4
3
2
1
0
1
2
3
2
0
40
39
6
5
4
3
2
1
44 43 42
41
7
8
9
10
11
12
13
14
15
P1.5
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
38
37
36
35
34
33
32
31
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
30
16
P2.6, A14
P2.5, A13
29
17
T1, P3.5
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
6
,
7
,
0
,
1
,
2
,
3
,
4
,
0
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
W
R
R
D
- 4 -
W78LE516
Pin Configurations, continued
44-Pin QFP (W78LE516F)
/
T
2
E
X
,
I
A
D
1
,
A
D
2
,
A
D
3
,
A
D
0
,
N
T
3
,
T
2
,
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
4
3
2
1
0
1
2
3
0
2
34
43 42 41 40 39 38 37 36 35
44
1
2
33
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P1.5
P1.6
P1.7
32
31
30
29
28
27
26
25
3
4
5
6
7
8
9
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
10
11
24
23
T1, P3.5
12 13 14 15 16 17 18 19 20 21 22
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
6
,
7
,
0
,
1
,
2
,
3
,
4
,
0
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
W
R
R
D
48-Pin LQFP (W78LE516D)
/
I
T
2
E
X
.
N
T
3
.
A
A
A
D
2
.
A
D
3
.
D
0
.
D
1
.
T
2
.
P
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
N
.
P
1
.
P
1
.
P
1
.
P
1
.
V
4
.
D
D
C
.
2
3
0
1
2
3
4
2
1
0
37
46
44
42 41 40 39 38
47
45
48
43
1
2
3
4
5
6
7
8
9
36
N.C.
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P1.5
P1.6
P1.7
35
34
33
32
31
30
29
28
27
26
25
RST
RXD, P3.0
INT2,P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
N.C.
10
11
12
P2.6, A14
P2.5, A13
23
13 14 15 16 17 18 19 20 21 22
24
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
4
.
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
N
.
C
.
6
,
7
,
0
0
,
1
,
2
,
3
,
4
,
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
W
R
R
D
Publication Release Date: February 15, 2005
Revision A5
- 5 -
W78LE516
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
EA
external ROM. The ROM address and data will not be presented on the bus if
the EA pin is high.
O H
PSEN
ALE
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RST
I L RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
XTAL1
I
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
VSS
O
I
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: ground potential.
VDD
I
POWER SUPPLY: Supply voltage for operation.
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.
P3.0−P3.7
P4.0−P4.3
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1,
Example:
P4
REG 0D8H
P4, #0AH
A, P4
P4, #00000001B ; Set bit P4.0
P4, #11111101B ; Clear bit P4.1
MOV
MOV
ORL
ANL
; Output data "A" through P4.0−P4.3.
; Read P4 status to Accumulator.
- 6 -
W78LE516
5. BLOCK DIAGRAM
P1.0
Port 1
Latch
Port
1
P1.7
ACC
B
P0.0
Port 0
Latch
Interrupt
Port
0
T1
T2
Timer
2
P0.7
DPTR
Timer
0
Stack
Pointer
Temp Reg.
PC
PSW
ALU
Timer
1
Incrementor
Addr. Reg.
UART
P3.0
64KB
ROM
Port 3
Latch
SFR RAM
Address
Port
3
Instruction
Decoder
&
P3.7
4KB
ROM
Sequencer
512 bytes
RAM & SFR
P2.0
Port
2
Port 2
Latch
Bus & Clock
Controller
P2.7
Port 4
Latch
P4.0
P4.3
Port
4
Oscillator
Reset Block
RST
Power control
ALE
XTAL1 XTAL2
VCC
Vss
PSEN
Publication Release Date: February 15, 2005
Revision A5
- 7 -
W78LE516
6. FUNCTIONAL DESCRIPTION
The W78LE516 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
6.1 RAM
The internal data RAM in the W78LE516 is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
•
•
•
RAM 0H−7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
RAM 80H−FFH can only be addressed indirectly as the same as in 8051. Address pointers are
R0, R1 of the selected registers bank.
AUX-RAM 0H−FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointers are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disabled after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from
internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD.
Example,
CHPENR
CHPCON
MOV
REG
REG
CHPENR, #87H
F6H
BFH
MOV
CHPENR, #59H
ORL
MOV
MOV
CHPCON, #00010000B ; enable AUX-RAM
CHPENR, #00H
R0, #12H
MOV
MOVX
A, #34H
@R0, A
; Write 34h data to 12h address.
6.2 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
- 8 -
W78LE516
6.3 Clock
The W78LE516 is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78LE516 relatively insensitive to duty
cycle variations in the clock.
6.4 Crystal Oscillator
The W78LE516 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
6.5 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
6.6 Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to
the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a
hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered.
6.7 Reduce EMI Emission
The W78LE516 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.
Publication Release Date: February 15, 2005
- 9 -
Revision A5
W78LE516
6.8 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78LE516 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
W78LE516 Special Function Registers (SFRs) and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
+B
00000000
CHPENR
00000000
+ACC
00000000
+P4
xxxx1111
+PSW
00000000
+T2CON
00000000
XICON
00000000
+IP
00000000
+P3
00000000
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
RCAP2L
00000000
P4CONA
00000000
RCAP2H
00000000
P4CONB
00000000
TL2
00000000
SFRAL
TH2
00000000
SFRAH
SFRFD
00000000
SFRCN
00000000
CHPCON
0xx00000
00000000
00000000
P43AL
00000000
P42AL
P43AH
00000000
P42AH
P2ECON
0000xx00
00000000
00000000
SBUF
xxxxxxxx
P41AL
00000000
TH0
00000000
P40AL
P41AH
00000000
TH1
00000000
P40AH
TMOD
00000000
SP
TL0
00000000
DPL
TL1
00000000
DPH
8F
87
PCON
00110000
80
11111111
00000111
00000000
00000000
00000000
00000000
Notes:
1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
- 10 -
W78LE516
6.9 Port 4
Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0−P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt CLR and INT2 if enabled.
Mode 1: P4.0−P4.3 are read strobe signals that are synchronized with RD signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0−P4.3 are write strobe signals that are synchronized with WRsignal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0−P4.3 are read/write strobe signals that are synchronized with RD or WRsignal at
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
6.10 INT2 /INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Publication Release Date: February 15, 2005
- 11 -
Revision A5
W78LE516
Eight-source interrupt information:
INTERRUPT SOURCE
VECTOR
POLLING
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
ADDRESS
SEQUENCE WITHIN
PRIORITY LEVEL
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
IE.1
IE.2
IE.3
IE.4
TCON.0
1
2
3
4
5
6
-
TCON.2
-
-
-
IE.5
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
P4CONB (C3H)
BIT
NAME
FUNCTION
7, 6
P43FUN1 00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
P43FUN0 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
5, 4
P43CMP1 Chip-select signals address comparison:
P43CMP0 00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
01: Compare the 15 high bits (A15−A1) of address bus with the base address
register P43AH, P43AL.
10: Compare the 14 high bits (A15−A2) of address bus with the base address
register P43AH, P43AL.
11: Compare the 8 high bits (A15−A8) of address bus with the base address
register P43AH, P43AL.
3, 2
1, 0
P42FUN1 The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.
P42FUN0
P42CMP1 The P4.2 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
P42CMP0
- 12 -
W78LE516
P4CONA (C2H)
BIT
7, 6
NAME
P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.
P41CMP1 The P4.1 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.
P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.
P40CMP1 The P4.0 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.
FUNCTION
P41FUN0
P41CMP0
P40FUN0
P40CMP0
5, 4
3, 2
1, 0
P2ECON (AEH)
BIT
NAME
FUNCTION
7
P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
= 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe
signal.
= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
6
5
4
3
2
1
0
P42CSINV The similarity definition as P43SINV.
P41CSINV The similarity definition as P43SINV.
P40CSINV The similarity definition as P43SINV.
-
-
-
-
Reserve
Reserve
0
0
6.11 Port 4 Base Address Registers
P40AH, P40AL:
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.
P41AH, P41AL:
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.
Publication Release Date: February 15, 2005
- 13 -
Revision A5
W78LE516
P42AH, P42AL:
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.
P43AH, P43AL:
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.
P4 (D8H)
BIT
7
6
5
4
NAME
FUNCTION
-
-
-
Reserve
Reserve
Reserve
Reserve
-
3
2
1
0
P43
P42
P41
P40
Port 4 Data bit which outputs to pin P4.3 at mode 0.
Port 4 Data bit which outputs to pin P4.2 at mode 0.
Port 4 Data bit which outputs to pin P4.1at mode 0.
Port 4 Data bit which outputs to pin P4.0 at mode 0.
Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H−1237H
and positive polarity, and P4.1−P4.3 are used as general I/O ports.
MOV P40AH,#12H
MOV P40AL,#34H
; Base I/O address 1234H for P4.0
MOV P4CONA,#00001010B
MOV P4CONB,#00H
MOV P2ECON,#10H
; P4.0 a write strobe signal and address line A0 and A1 are masked.
; P4.1−P4.3 as general I/O port which are the same as PORT1
; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity
; default is negative.
Then any instruction MOVX @DPTR,A (with DPTR = 1234H−1237H) will generate the positive polarity
write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of data #XX
to pin P4.3−P4.1.
- 14 -
W78LE516
P4xCSINV
P4 REGISTER
P4.x
DATA I/O
RD_CS
MUX 4->1
WR_CS
READ
WRITE
RD/WR_CS
PIN
P4.x
ADDRESS BUS
P4xFUN0
P4xFUN1
EQUAL
REGISTER
P4xAL
P4xAH
Bit Length
Selectable
comparator
P4.x INPUT DATA BUS
REGISTER
P4xCMP0
P4xCMP1
6.12 In-System Programming (ISP) Mode
The W78LE516 equips one 64K byte of main Flash EPROM bank for application program (called AP
FLASH EPROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LD
FLASH EPROM). In the normal operation, the microcontroller executes the code in the AP FLASH
EPROM. If the content of AP FLASH EPROM needs to be modified, the W78LE516 allows user to
activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is
read-only by default, software must write two specific values 87H, then 59H sequentially to the
CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the
values except 87H and 59H will close CHPCON register write attribute. The W78LE516 achieves
all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc,
during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming
mode after a wake-up from idle mode. Because device needs proper time to complete the ISP
operations before awaken from idle mode, software may use timer interrupt to control the duration for
device wake-up from idle mode. To perform ISP operation for revising contents of AP FLASH
EPROM, software located at AP FLASH EPROM setting the CHPCON register then enter idle mode,
after awaken from idle mode the device executes the corresponding interrupt service routine in LD
FLASH EPROM. Because the device will clear the program counter while switching from AP FLASH
EPROM to LD FLASH EPROM, the first execution of RETI instruction in interrupt service routine will
jump to 00H at LD FLASH EPROM area. The device offers a software reset for switching back to AP
FLASH EPROM while the content of AP FLASH EPROM has been updated completely. Setting
CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The
software reset serves as a external reset. This in-system programming feature makes the job easy
and efficient in which the application needs to update firmware frequently. In some applications, the in-
system programming feature make it possible to easily update the system firmware without opening
the chassis.
Note: The ISP Mode operates by supply voltage from 3.3V to 5.5V.
Publication Release Date: February 15, 2005
- 15 -
Revision A5
W78LE516
SFRAH, SFRAL: The objective address of on-chip Flash EPROM in the in-system programming
mode. SFRAH contains the high-order byte of address, SFRAL contains the low-
order byte of address.
SFRFD: The programming data for on-chip Flash EPROM in programming mode.
SFRCN: The control byte of on-chip Flash EPROM programming mode.
SFRCN (C7)
BIT
NAME
FUNCTION
7
-
Reserve.
On-chip Flash EPROM bank select for in-system programming.
= 0: 64K bytes Flash EPROM bank is selected as destination for re-
programming.
6
WFWIN
= 1: 4K bytes Flash EPROM bank is selected as destination for re-
programming.
5
4
OEN
CEN
Flash EPROM output enable.
Flash EPROM chip enable.
The flash control signals
3, 2, 1, 0
CTRL[3:0]
MODE
WFWIN
CTRL<3:0>
OEN
CEN
SFRAH, SFRAL
SFRFD
Erase 64KB AP FLASH
EPROM
0
0010
1
0
X
X
Program 64KB AP FLASH
EPROM
0
0
1
1
1
0001
0000
0010
0001
0000
1
0
1
1
0
0
0
0
0
0
Address in
Address in
X
Data in
Data out
X
Read 64KB AP FLASH
EPROM
Erase 4KB LD FLASH
EPROM
Program 4KB LD FLASH
EPROM
Address in
Address in
Data in
Data out
Read 4KB LD FLASH
EPROM
- 16 -
W78LE516
6.13 In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT
NAME
FUNCTION
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will
enforce microcontroller reset to initial condition just like power on reset. This
action will re-boot the microcontroller and start to normal operation. To read
this bit in logic-1 can determine that the H/W REBOOT mode is running.
SWRESET
(F04KMODE)
7
6
5
-
-
Reserve.
Reserve.
1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM
Must set to 0.
ENAUXRAM
4
3
2
0
0
Must set to 0.
The Program Location Select.
0: The Loader Program locates at the 64 KB AP FLASH EPROM. 4KB LD
1
FBOOTSL FLASH EPROM is destination for re-programming.
1: The Loader Program locates at the 4 KB memory bank. 64KB AP FLASH
EPROM isdestination for re-programming.
FLASH EPROM Programming Enable.
= 1: enable. The microcontroller enter the in-system programming mode after
entering the idle mode and wake-up from interrupt. During in-system
0
FPROGEN
programming mode, the operation of erase, program and read are
achieve when device enters idle mode.
= 0: disable. The on-chip flash memory is read-only. In-system
programmability is disabled.
H/W REBOOT Mode (Boot from LD FLASH EPROM)
By default, the W78LE516 boots from AP FLASH EPROM program after a power on reset. On some
occasions, user can force the W78LE516 to boot from the LD FLASH EPROM program via following
settings. The possible situation that you need to enter H/W REBOOT mode when the AP FLASH
EPROM program can not run properly and device can not jump back to LD FLASH EPROM to
execute in-system programming function. Then you can use this H/W REBOOT mode to force the
W78LE516 jumps to LD FLASH EPROM and executes in-system programming procedure. When you
design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a
CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel.
When the AP FLASH EPROM program fails to execute the normal application program. User can
press both two buttons at the same time and then turn on the power of the personal computer to force
the W78LE516 to enter the H/W REBOOT mode. After power on of personal computer, you can
release both buttons and finish the in-system programming procedure to update the AP FLASH
EPROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN
pin value at reset to prevent from accidentally activating the programming mode or H/W REBOOT
mode.
Publication Release Date: February 15, 2005
- 17 -
Revision A5
W78LE516
H/W REBOOT MODE
P4.3
X
L
P2.7
L
X
P2.6
L
X
MODE
FO4KBOOT
FO4KBOOT
The Reset Timing For Entering
F04KBOOT Mode
P2.7
Hi-Z
Hi-Z
P2.6
RST
30 mS
10 mS
- 18 -
W78LE516
The Algorithm of In-System Programming
Part 1:64KB APROM
procedure of entering
START
In-System Programming Mode
Enter In-System
Programming Mode ?
(conditions depend on
user's application)
No
Yes
Setting control registers
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Execute the normal application
program
Setting Timer (about 1.5 us)
and enable timer interrupt
END
Start Timer and enter idle Mode.
(CPU will be wakened from idle mode
by timer interrupt, then enter In-System
Programming mode)
CPU will be wakened by interrupt and
re-boot from 4KB LDROM to execute
the loader program.
Go
Publication Release Date: February 15, 2005
Revision A5
- 19 -
W78LE516
Part 2: 4KB LDROM
Procedure of Updating
the 64KB APROM
Go
Timer Interrupt Service Routine:
Stop Timer & disable interrupt
PGM
Yes
Yes
Is F04KBOOT Mode?
(CHPCON.7=1)
End of Programming ?
No
No
Reset the CHPCON Register:
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Setting Timer and enable Timer
interrupt for wake-up .
(50us for program operation)
Yes
Is currently in the
F04KBOOT Mode ?
No
Software reset CPU and
re-boot from the 64KB
APROM.
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H
Get the parameters of new code
(Address and data bytes)
Setting Timer and enable Timer
interrupt for wake-up .
(15 ms for erasing operation)
through I/O ports, UART or
other interfaces.
Setting erase operation mode:
MOV SFRCN,#22H
(Erase 64KB APROM)
Setting control registers for
programming:
Hardware Reset
to re-boot from
MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
new 64 KB APROM.
Start Timer and enter IDLE
Mode.
(S/W reset is
MOV SFRCN,#21H
invalid in F04KBOOT
(Erasing...)
Mode)
End of erase
operation. CPU will
be wakened by Timer
interrupt.
END
Executing new code
from address
00H in the 64KB APROM.
PGM
- 20 -
W78LE516
7. SECURITY
During the on-chip ROM programming mode, the Flash EPROM can be programmed and verified
repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection
of ROM and those operations on it are described below.
The W78LE516 has a Security Register which can not be accessed in programming mode. Those bits
of the Security Registers can not be changed once they have been programmed from high to low.
They can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of
the LD FLASH EPROM space.
0000h
4KB On-chip ROM
Program Memory
LDROM
0FFFh
B2 B1 B0
B7 Reserved
Security Bits
64KB On-chip ROM
Program Memory
B0: Lock bit, logic 0: active
B1: MOVC inhibit,
APROM
logic 0: the MOVC instruction in external memory
Reserved
logic 1: no restriction.
cannot access the code in internal memory.
B2: Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable
FFFFh
Security Register
B07: Osillator Control
logic 0: 1/2 gain
logic 1: Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Register
7.1 Lock bit
This bit is used to protect the customer's program code in the W78LE516. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
FLASH EPROM data and Special Setting Register can be accessed again.
7.2 MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the FLASH EPROM data in both internal and external memory. If this bit
is logic 1, there are no restrictions on the MOVC instruction.
7.3 Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
Publication Release Date: February 15, 2005
- 21 -
Revision A5
W78LE516
7.4 Oscillator Control
W78LE516/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to
set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may
improperly affect the external crystal operation at high frequency. The value of C1 and C2 may need
some adjustment while running at lower gain.
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
PARAMETER
DC Power Supply
Input Voltage
Operating Temperature
Storage Temperature
SYMBOL
VDD−VSS
VIN
MIN.
-0.3
VSS -0.3
0
MAX.
+6.0
VDD +0.3
60
UNIT
V
V
°C
°C
TA
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8.2 D.C. Characteristics
VSS = 0V, TA = 25° C, unless otherwise specified.
SPECIFICATION
PARAMETER
Operating Voltage
Operating Current
Idle Current
SYM.
VDD
UNIT
TEST CONDITIONS
Without I.S.P.
MIN.
2.4
3.3
-
-
-
-
-
-
MAX.
5.5
5.5
20
3
V
V
With I.S.P.
mA
mA
mA
mA
µA
µA
No load VDD = 5.5V
No load VDD = 2.4V
VDD = 5.5V, Fosc = 20 MHz
VDD = 2.4V, Fosc = 12 MHz
VDD = 5.5V, Fosc = 20 MHz
VDD = 2.4V, Fosc = 12 MHz
VDD = 5.5V
VIN = 0V or VDD
VDD = 5.5V
0 < VIN < VDD
VDD = 5.5V
IDD
6
IIDLE
IPWDN
1.5
50
20
Power Down Current
Input Current
P1, P2, P3, P4
Input Current
RST
IIN1
IIN2
-50
-10
-10
+10
+300
+10
µA
µA
µA
Input Leakage Current
ILK
ITL [*4]
VIL1
0V < VIN < VDD
P0, EA
Logic 1 to 0 Transition
VDD = 5.5V
VIN = 2.0V
Current
-500
-
µA
P1, P2, P3, P4
Input Low Voltage
0
0
0.8
0.5
V
V
VDD = 4.5V
VDD = 2.4V
P0, P1, P2, P3, P4,
- 22 -
W78LE516
D.C. Characteristics, continued
SPECIFICATION
PARAMETER
SYM.
VIL2
UNIT
TEST CONDITIONS
VDD = 4.5V
VDD = 2.4V
VDD = 4.5V
VDD = 2.4V
VDD = 5.5V
VDD = 2.4V
MIN.
0
MAX.
0.8
Input Low Voltage
RST[*1]
Input Low Voltage
XTAL1 [*3]
V
V
V
V
V
0
0.3
0
0.8
VIL3
0
0.4
Input High Voltage
2.4
VDD +0.2
VIH1
1.4
3.5
1.7
3.5
2.4
-
VDD +0.2
V
V
V
V
V
V
V
V
P0, P1, P2, P3, P4,EA
Input High Voltage
RST[*1]
Input High Voltage
XTAL1 [*3]
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
VDD +0.2
VDD +0.2
VDD +0.2
VDD +0.2
0.45
VDD = 5.5V
VDD = 2.4V
VDD = 5.5V
VDD = 2.4V
VDD = 4.5V, IOL = +2 mA
VDD = 2.4V, IOL = +1 mA
VDD = 4.5V, IOL = +4 mA
VIH2
VIH3
VOL1
-
0.25
-
0.45
VOL2
ISK1
-
0.25
V
VDD = 2.4V, IOL = +2 mA
P0, ALE, PSEN [*2]
Sink Current
P1, P2, P3, P4
Sink Current
4
1.8
8
12
5.4
16
mA
mA
mA
VDD = 4.5V, Vin = 0.45V
VDD = 2.4V, Vin = 0.45V
VDD = 4.5V, Vin = 0.45V
ISK2
4.5
2.4
1.4
2.4
1.4
9
-
mA
V
VDD = 2.4V, Vin = 0.4V
P0, ALE, PSEN
Output High Voltage
P1, P2, P3, P4
VDD = 4.5V, IOH = -100 µA
VDD = 2.4V, IOH = -8 µA
VDD = 4.5V, IOH = -400 µA
VOH1
VOH2
ISR1
ISR2
-
V
Output High Voltage
-
V
-
V
VDD = 2.4V, IOH = -200 µA
VDD = 4.5V, Vin = 2.4V
VDD = 2.4V, Vin = 1.4V
VDD = 4.5V, Vin = 2.4V
VDD = 2.4V, Vin = 1.4V
P0, ALE, PSEN [*2]
Source Current
P1, P2, P3, P4
-100
-20
-8
-250
-50
µA
µA
mA
Source Current
-14
-1.9
-3.8
mA
P0, ALE, PSEN
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
Publication Release Date: February 15, 2005
Revision A5
- 23 -
W78LE516
8.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
T
CH
T
CL
F
T
CP
OP,
PARAMETER
Operating Speed
SYMBOL
FOP
MIN.
0
TYP.
MAX.
24
-
UNIT
MHz
nS
NOTES
-
-
-
-
1
2
3
3
Clock Period
Clock High
Clock Low
TCP
41.7
20
TCH
-
nS
TCL
20
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
SYMBOL
TAAS
TAAH
MIN.
1 TCP-∆
1 TCP-∆
1 TCP-∆
-
TYP.
MAX.
UNIT
nS
nS
NOTES
-
-
-
-
-
-
-
4
1, 4
4
Address Hold from ALE Low
TAPL
nS
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
TPDA
TPDH
TPDZ
TALW
TPSW
2 TCP
nS
nS
nS
nS
nS
2
3
0
0
-
1 TCP
-
1 TCP
Data Float after PSEN High
ALE Pulse Width
2 TCP
3 TCP
-
-
4
4
2 TCP-∆
3 TCP-∆
PSEN Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
- 24 -
W78LE516
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
3 TCP+∆
4 TCP
2 TCP
2 TCP
-
UNIT
NOTES
TDAR
-
nS
1, 2
3 TCP-∆
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDDA
TDDH
TDDZ
TDRD
-
-
nS
nS
nS
nS
1
0
0
-
-
6 TCP
2
6 TCP-∆
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
MIN.
TYP.
MAX.
UNIT
TDAW
-
nS
3 TCP-∆
1 TCP-∆
1 TCP-∆
6 TCP-∆
3 TCP+∆
TDAD
TDWD
TDWR
-
-
-
-
-
nS
nS
nS
6 TCP
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
-
-
-
-
-
-
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Publication Release Date: February 15, 2005
- 25 -
Revision A5
W78LE516
9. TIMING WAVEFORMS
9.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
T
ALW
T
APL
PSEN
T
PSW
T
AAS
PORT 2
PORT 0
T
PDA
T
AAH
T
T
PDH, PDZ
A0-A7
A0-A7
Code A0-A7
Code
Data
Data
A0-A7
9.2 Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
TDAR
TDDA
TDDH, TDDZ
TDRD
- 26 -
W78LE516
Timing Waveforms, continued
9.3 Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
T
DATA OUT
T
DWD
T
DAD
T
DWR
DAW
9.4 Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDH
TPDA
PORT
DATA OUT
INPUT
SAMPLE
Publication Release Date: February 15, 2005
Revision A5
- 27 -
W78LE516
10. TYPICAL APPLICATION CIRCUIT
10.1 External Program Memory and Crystal
V
DD
AD0
31
19
39
AD0
3
4
7
8
11
12
13
15
16
17
18
19
AD0
2
5
A0
A1
A2
A3
A4
A5
A0
A1
A2
A3
A4
A5
A6
A7
10
9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
38 AD1
37 AD2
AD1
AD2
AD3
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A1
6
8
A2
XTAL1
AD3
AD4
AD5
36
35
34
9
7
10 u
A3
AD4 13
AD5 14
6
12
15
A4
R
18
9
5
XTAL2
RST
A5
CRYSTAL
33 AD6
32 AD7
17
16 A6
AD6
4
A6
19
A7
3
AD7 18
A7
8.2 K
A8 25
A9 24
A8
1
11
GND
21
22
23
24
25
26
27
28
A8
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C1
C2
A9
A10 21
A10
A11
A12
A13
A14
A15
INT0
12
13
14
15
A11
A12
A10
A11
A12
A13
A14
A15
23
2
INT1
74LS373
A13 26
T0
A14
A15
27
1
T1
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
20
22
GND
2
3
4
5
6
7
8
CE
OE
RD
WR
17
16
29
30
27512
PSEN
ALE
11
10
TXD
RXD
W78LE516
Figure A
CRYSTAL
6 MHz
C1
C2
R
-
47P
30P
15P
47P
30P
10P
16 MHz
24 MHz
-
-
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A
2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
- 28 -
W78LE516
Typical Application Circuit, continued
10.2 Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
2
5
A0
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
EA
A1
9
8
6
A2
7
XTAL1
8
9
A3
7
OSCILLATOR
10 u
13
14
17
18
12
15
16
19
6
A4
18
9
A5
5
XTAL2
A6
4
A7
3
8.2 K
25
24
21
23
2
A8
RST
INT0
GND
1
11
A8
A9
A9
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
OC
G
A10
A11
A12
A13
A14
A10
A11
A12
A13
12
13
14
15
23 A10
A11
24
74LS373
INT1
26
1
25
26
A12
A13
T0
A14
CE
OE
WR
T1
27 A14
28
1
GND
20
22
27
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
2
3
4
5
6
RD
WR
17
16
29
20256
PSEN
30
11
ALE
7
8
TXD
RXD
10
W78LE516
Figure B
Publication Release Date: February 15, 2005
Revision A5
- 29 -
W78LE516
11. PACKAGE DIMENSIONS
11.1 40-pin DIP
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
A
5.334
0.210
0.010
0.150 0.155 0.160
0.254
3.81
A
A
B
B
c
1
3.937 4.064
2
0.016 0.018
0.406 0.457 0.559
1.219 1.27 1.372
0.203 0.254 0.356
0.022
0.054
0.050
0.010
2.055
0.048
0.008
1
0.014
D
2.070
52.58
15.494
13.97
2.794
3.556
15
52.20
15.24
D
E
E
e
L
a
40
21
0.610
0.590 0.600
14.986
13.72 13.84
0.540
0.545 0.550
1
1
0.110
0.090 0.100
2.286
3.048
0
2.54
0.120 0.130 0.140
15
3.302
1
E
0
0.630 0.650 0.670 16.00 16.51 17.01
0.090
e
S
A
2.286
1
20
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
A2
A
L
Base Plane
A1
.
are determined at the mold parting line.
Seating Plane
4. Dimension B1 does not include dambar
protrusion/intrusion.
B
e1
eA
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
a
B 1
11.2 44-pin PLCC
D
H
D
1
6
44
40
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
7
39
0.185
4.699
A
A
0.020
0.508
1
0.145 0.150 0.155 3.683 3.81 3.937
A2
1
0.026 0.028
0.016 0.018
0.032 0.66
0.406
0.813
0.559
0.356
0.711
0.457
b
0.022
b
HE
GE
E
0.008 0.010 0.014 0.203 0.254
c
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
D
E
e
0.648 0.653
0.658
0.050 BSC
0.590
0.590
0.680
0.680
14.99 15.49 16.00
14.99 15.49 16.00
17.27 17.53 17.78
17.27 17.53 17.78
0.610 0.630
0.610 0.630
0.690 0.700
0.690 0.700
17
29
GD
G
H
H
E
D
E
18
28
c
0.090 0.100
2.54 2.794
0.10
0.110 2.296
0.004
L
y
L
Notes:
A2
A1
A
1. Dimension D & E do not include interlead
flash.
θ
2. Dimension b1 does not include dambar
protrusion/intrusion.
e
b
b 1
3. Controlling dimension: Inches
Seating Plane
y
4. General appearance spec. should be based
on final visual inspection spec.
G D
- 30 -
W78LE516
Package Dimensions, continued
11.3 44-pin PQFP
H D
D
Dimension in inch
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
34
44
---
---
---
---
---
---
0.002
0.01
0.02
0.25
2.05
0.05
1.90
0.25
0.5
1
A
0.075 0.081 0.087
2.20
0.45
0.254
A2
b
c
33
1
0.01
0.014
0.006
0.394
0.394
0.031
0.018
0.010
0.398
0.35
0.101 0.152
0.004
0.390
10.00
10.00
0.80
9.9
9.9
10.1
10.1
0.952
13.45
13.45
0.95
1.905
0.08
7
D
E
e
0.398
0.036
0.530
0.390
0.025
E
HE
0.635
12.95
12.95
0.65
0.510 0.520
13.2
13.2
0.8
H
D
E
0.520 0.530
0.025 0.031
0.510
H
L
L
y
11
0.037
0.051 0.063 0.075 1.295
0.003
1.6
1
12
22
e
b
7
θ
0
0
Notes:
1. Dimension D & E do not include interlead
c
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
A
A2
A1
3. Controlling dimension: Millimeter
θ
4. General appearance spec. should be based
on final visual inspection spec.
L
See Detail F
y
Seating Plane
L
1
Detail F
11.4 48-pin LQFP
D
H
D
25
36
Dimension in mm
Symbol
Nom.
Min.
---
Max.
1.60
A
---
---
0.05
1.35
0.15
1.45
A
A2
b
1
24
37
1.40
0.17 0.20
0.27
0.20
---
0.09
c
7.00
7.00
D
E
E
H
E
e
0.50
9.00
9.00
HD
HE
L
48
13
0.45
0.75
0.60
1.00
0.08
3.5
L
y1
---
0
---
7
1
12
e
b
0
Notes:
c
1. Dimensions D & E do not include interlead
flash.
2
A
A
A
2. Dimension b does not include dambar
protrusion/intrusion.
1
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
See Detail F
L
y
Seating Plane
L
1
Detail F
Publication Release Date: February 15, 2005
Revision A5
- 31 -
W78LE516
12. APPLICATION NOTE: IN-SYSTEM PROGRAMMING SOFTWARE EXAMPLES
This application note illustrates the in-system programmability of the Winbond W78LE516 Flash
EPROM microcontroller. In this example, microcontroller will boot from 64 KB AP FLASH EPROM
bank and waiting for a key to enter in-system programming mode for re-programming the contents of
64 KB AP FLASH EPROM. While entering in-system programming mode, microcontroller executes
the loader program in 4KB LD FLASH EPROM bank. The loader program erases the 64 KB AP
FLASH EPROM then reads the new code data from external SRAM buffer (or through other
interfaces) to update the 64KB AP FLASH EPROM.
EXAMPLE 1:
;*******************************************************************************************************************
;* Example of 64K AP FLASH EPROM program: Program will scan the P1.0. if P1.0 = 0, enters in-
system
;* programming mode for updating the content of AP FLASH EPROM code else executes the current
ROM code.
;* XTAL = 16 MHz
;*******************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON EQU
CHPENR EQU
BFH
F6H
C4H
C5H
C6H
C7H
SFRAL
SFRAH
SFRFD
SFRCN
EQU
EQU
EQU
EQU
ORG
0H
LJMP 100H
; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH
CLR
TR0
; TR0 = 0, STOP TIMER0
MOV
MOV
RETI
TL0, R6
TH0, R7
;************************************************************************
;* 64K AP FLASH EPROM MAIN PROGRAM
;************************************************************************
ORG100H
MAIN_64K:
MOV A, P1
; SCAN P1.0
ANL A, #01H
CJNE A, #01H, PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE
JMP NORMAL_MODE
PROGRAM_64K:
MOV CHPENR, #87H
; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE
; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE
; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE
MOV CHPENR, #59H
MOV CHPCON, #03H
- 32 -
W78LE516
MOV TCON, #00H
MOV IP, #00H
; TR = 0 TIMER0 STOP
; IP = 00H
MOV IE, #82H
; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
; TL0 = F0H
; TH0 = FFH
MOV TH0, R7
MOV TMOD, #01H
MOV TCON, #10H
MOV PCON, #01H
; TMOD = 01H, SET TIMER0 A 16-BIT TIMER
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM
; PROGRAMMING
;********************************************************************************
;* Normal mode 64KB AP FLASH EPROM program: depending user's application
;********************************************************************************
NORMAL_MODE:
.
; User's application program
.
.
.
EXAMPLE 2:
;***************************************************************************************************************************** ;*
Example of 4 KB LD FLASH EPROM program: This loader program will erase the 64KB AP FLASH EPROM first,
then reads the new ;* code from external SRAM and program them into 64 KB AP FLASH EPROM bank. XTAL =
16 MHz
;*****************************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON
CHPENR
SFRAL
EQU
EQU
EQU
EQU
EQU
EQU
BFH
F6H
C4H
C5H
C6H
C7H
SFRAH
SFRFD
SFRCN
ORG 000H
LJMP 100H
; JUMP TO MAIN PROGRAM
;************************************************************************
;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0
MOV TL0, R6
MOV TH0, R7
RETI
; TR0 = 0, STOP TIMER0
;************************************************************************
;* 4KB LD FLASH EPROM MAIN PROGRAM
;************************************************************************
ORG 100H
Publication Release Date: February 15, 2005
Revision A5
- 33 -
W78LE516
MAIN_4K:
MOV SP, #C0H
; BE INITIAL SP REGISTER
MOV CHPENR, #87H
MOV CHPENR, #59H
MOV A, CHPCON
ANL A, #80H
; CHPENR = 87H, CHPCON WRITE ENABLE.
; CHPENR = 59H, CHPCON WRITE ENABLE.
CJNE A, #80H, UPDATE_64K ; CHECK H/W REBOOT MODE ?
MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.
MOV CHPENR, #00H
; DISABLE CHPCON WRITE ATTRIBUTE
MOV TCON, #00H
MOV TMOD, #01H
MOV IP, #00H
; TCON = 00H, TR = 0 TIMER0 STOP
; TMOD = 01H, SET TIMER0 A 16BIT TIMER
; IP = 00H
MOV IE, #82H
; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV TCON, #10H
MOV PCON, #01H
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE
UPDATE_64K:
MOV CHPENR, #00H
MOV TCON, #00H
MOV IP, #00H
; DISABLE CHPCON WRITE-ATTRIBUTE
; TCON = 00H, TR = 0 TIM0 STOP
; IP = 00H
MOV IE, #82H
; IE = 82H, TIMER0 INTERRUPT ENABLED
; TMOD = 01H, MODE1
MOV TMOD, #01H
MOV R6, #E0H
; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING
; ON USER'S SYSTEM CLOCK RATE.
MOV R7, #B1H
MOV TL0, R6
MOV TH0, R7
ERASE_P_4K:
MOV SFRCN, #22H
MOV TCON, #10H
MOV PCON, #01H
; SFRCN (C7H) = 22H ERASE 64K
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE (FOR ERASE OPERATION)
;*********************************************************************
;* BLANK CHECK
;*********************************************************************
MOV SFRCN, #0H
MOV SFRAH, #0H
MOV SFRAL, #0H
MOV R6, #FEH
MOV R7, #FFH
MOV TL0, R6
; READ 64KB AP FLASH EPROM MODE
; START ADDRESS = 0H
; SET TIMER FOR READ OPERATION, ABOUT 1.5 µS.
MOV TH0, R7
BLANK_CHECK_LOOP:
SETB TR0
; ENABLE TIMER 0
; ENTER IDLE MODE
; READ ONE BYTE
MOV PCON, #01H
MOV A, SFRFD
CJNE A, #FFH, BLANK_CHECK_ERROR
INC SFRAL
; NEXT ADDRESS
- 34 -
W78LE516
MOV A, SFRAL
JNZ BLANK_CHECK_LOOP
INC SFRAH
MOV A, SFRAH
CJNE A, #0H, BLANK_CHECK_LOOP ; END ADDRESS = FFFFH
JMP PROGRAM_64KROM
BLANK_CHECK_ERROR:
MOV P1, #F0H
MOV P3, #F0H
JMP $
;*******************************************************************************
;* RE-PROGRAMMING 64KB AP FLASH EPROM BANK
;*******************************************************************************
PROGRAM_64KROM:
MOV DPTR, #0H
MOV R2, #00H
MOV R1, #00H
MOV DPTR, #0H
MOV SFRAH, R1
MOV SFRCN, #21H
MOV R6, #BEH
MOV R7, #FFH
MOV TL0, R6
; THE ADDRESS OF NEW ROM CODE
; TARGET LOW BYTE ADDRESS
; TARGET HIGH BYTE ADDRESS
; EXTERNAL SRAM BUFFER ADDRESS
; SFRAH, TARGET HIGH ADDRESS
; SFRCN (C7H) = 21 (PROGRAM 64K)
; SET TIMER FOR PROGRAMMING, ABOUT 50 µS.
MOV TH0, R7
PROG_D_64K:
MOV SFRAL, R2
MOVX A, @DPTR
; SFRAL (C4H) = LOW BYTE ADDRESS
; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER?
; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE.
; SFRFD (C6H) = DATA IN
MOV SFRFD, A
MOV TCON, #10H
MOV PCON, #01H
INC DPTR
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE (PRORGAMMING)
INC R2
CJNE R2, #0H, PROG_D_64K
INC R1
MOV SFRAH, R1
CJNE R1, #0H, PROG_D_64K
;*****************************************************************************
; * VERIFY 64KB AP FLASH EPROM BANK
;*****************************************************************************
MOV R4, #03H
MOV R6, #FEH
MOV R7, #FFH
MOV TL0, R6
; ERROR COUNTER
; SET TIMER FOR READ VERIFY, ABOUT 1.5 µS.
MOV TH0, R7
MOV DPTR, #0H
MOV R2, #0H
; The start address of sample code
; Target low byte address
MOV R1, #0H
; Target high byte address
MOV SFRAH, R1
MOV SFRCN, #00H
; SFRAH, Target high address
; SFRCN = 00 (Read Flash code)
Publication Release Date: February 15, 2005
Revision A5
- 35 -
W78LE516
READ_VERIFY_64K:
MOV SFRAL, R2
MOV TCON, #10H
MOV PCON, #01H
INC R2
; SFRAL (C4H) = LOW ADDRESS
; TCON = 10H, TR0 = 1, GO
MOVX A,@DPTR
INC DPTR
CJNE A, SFRFD, ERROR_64K
CJNE R2, #0H, READ_VERIFY_64K
INC R1
MOV SFRAH, R1
CJNE R1, #0H, READ_VERIFY_64K
;******************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************
MOV CHPENR, #87H
MOV CHPENR, #59H
MOV CHPCON, #83H
; CHPENR = 87H
; CHPENR = 59H
; CHPCON = 83H, SOFTWARE RESET.
ERROR_64K:
DJNZ R4, UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES.
.
.
.
.
; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
- 36 -
W78LE516
13. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
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March, 2001
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A5
August, 2004
Feb. 15, 2005
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Publication Release Date: February 15, 2005
Revision A5
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