W78LE516P-24 [WINBOND]
8-BIT MICROCONTROLLER; 8位微控制器
| 型号： | W78LE516P-24 |
| 厂家： | 
WINBOND |
| 描述： | 8-BIT MICROCONTROLLER |
| 文件： | 总31页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary W78LE516
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE516 is an 8-bit microcontroller which has an in-system programmable MTP-ROM for
firmware updating. The instruction set of the W78LE516 is fully compatible with the standard 8052.
The W78LE516 contains a 64K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM
which allows the contents of the 64KB main MTP-ROM to be updated by the loader program located
at the 4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-
addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These
peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming
and verification, the MTP-ROM inside the W78LE516 allows the program memory to be programmed
and read electronically. Once the code is confirmed, the user can protect the code for security.
The W78LE516 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
· Fully static design 8-bit CMOS microcontroller
· 64K bytes of in-system programmable MTP-ROM for Application Program (APROM)
· 4K bytes of auxiliary MTP-ROM for Loader Program (LDROM)
· 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)
· 64K bytes program memory address space and 64K bytes data memory address space
· Four 8-bit bi-directional ports
· One 4-bit multipurpose programmable port
· Three 16-bit timer/counters
· One full duplex serial port
· Eight-sources, two-level interrupt capability
· Built-in power management
· Code protection
· Packaged in
-
-
-
DIP 40: W78LE516-24
PLCC 44: W78LE516P-24
QFP 44: W78LE516F-24
Publication Release Date: June 2000
Revision A1
- 1 -
Preliminary W78LE516
PIN CONFIGURATIONS
40-Pin DIP (W78LE516)
1
VDD
T2, P1.0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2EX, P1.1
2
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
3
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin PLCC (W78LE516P)
44-Pin QFP (W78LE516F)
/
T
2
E
X
,
I
/
A
D
1
,
A
D
3
,
A
D
0
,
A
D
2
,
N
T
3
,
T
2
E
X
,
I
T
2
,
A
D
1
,
A
D
3
,
N
T
3
,
A
D
0
,
A
D
2
,
T
2
,
P
1
.
P
1
.
P
0
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
4
.
P
0
.
V
D
D
3
4
3
2
1
0
0
1
2
2
3
4
3
2
1
0
1
2
2
0
34
43 42 41 40 39 38 37 36 35
44
40
39
6
5
4
3
2
1
44 43 42
41
1
2
3
4
5
6
7
8
9
33
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.5
P1.6
7
8
9
P1.5
P1.6
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
32
31
30
29
28
27
26
25
38
37
36
35
34
33
32
31
P1.7
P1.7
RST
10
11
12
13
14
15
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
EA
RXD, P3.0
EA
P4.1
P4.1
ALE
INT2, P4.3
TXD, P3.1
ALE
INT0, P3.2
INT1, P3.3
T0, P3.4
PSEN
P2.7, A15
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
10
11
24
23
P2.6, A14
P2.5, A13
30
29
16
17
P2.6, A14
P2.5, A13
T1, P3.5
T1, P3.5
12 13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
3
,
A
1
1
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
P
4
.
0
,
1
,
2
,
4
,
6
,
7
,
0
,
1
,
2
,
3
,
4
,
0
0
A
8
A
9
A
1
0
A
1
2
/
W
R
/
R
D
A
1
1
A
8
A
9
A
1
0
A
1
2
W
R
- 2 -
Preliminary W78LE516
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
I
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
EA
EA
the
pin is high.
O H
PSEN
ALE
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
PSEN
Port 0 address/data bus. When internal ROM access is performed, no
strobe signal outputs originate from this pin.
O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RST
I L RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
XTAL1
XTAL2
I
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
O
I
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: ground potential.
SS
V
DD
V
I
POWER SUPPLY: Supply voltage for operation.
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
-
P0.0 P0.7
-
P1.0 P1.7
I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
-
P2.0 P2.7
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.
-
P3.0 P3.7
-
P4.0 P4.3
* Note:
I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
TYPE
PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1,
Example:
P4
REG 0D8H
P4, #0AH
A, P4
-
MOV
MOV
SETB
CLR
; Output data "A" through P4.0 P4.3.
; Read P4 status to Accumulator.
; Set bit P4.0
P4.0
P4.1
; Clear bit P4.1
Publication Release Date: June 2000
Revision A1
- 3 -
Preliminary W78LE516
BLOCK DIAGRAM
P1.0
Port 1
Latch
Port
1
P1.7
ACC
B
P0.0
Port 0
Latch
Interrupt
Port
0
T1
T2
Timer
2
P0.7
DPTR
Timer
0
Stack
Pointer
Temp Reg.
PC
PSW
ALU
Timer
1
Incrementor
Addr. Reg.
UART
P3.0
P3.7
64KB
Port 3
Latch
SFR RAM
Address
Port
3
MTP-ROM
Instruction
Decoder
&
4KB
MTP-ROM
Sequencer
512 bytes
RAM & SFR
P2.0
P2.7
Port
2
Port 2
Latch
Bus & Clock
Controller
Port 4
Latch
P4.0
P4.3
Port
4
Oscillator
Reset Block
RST
Power control
ALE
XTAL1 XTAL2
VCC
Vss
PSEN
FUNCTIONAL DESCRIPTION
The W78LE516 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
RAM
The internal data RAM in the W78LE516 is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
·
-
RAM 0H 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
- 4 -
Preliminary W78LE516
·
-
RAM 80H FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
R1 of the selected registers bank.
· AUX-RAM 0H- FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal
WR
RD
.
program memory, an access to AUX-RAM will not affect the Ports P0, P2,
Example,
and
CHPENR
CHPCON
MOV
REG
REG
F6H
BFH
CHPENR,#87H
MOV
CHPENR,#59H
ORL
CHPCON,#00010000B ; enable AUX-RAM
MOV
CHPENR,#00H
R0,#12H
MOV
MOV
A,#34H
MOVX
@R0,A
; Write 34h data to 12h address.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer
0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer
1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled
by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter
or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
Clock
The W78LE516 is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78LE516 relatively insensitive to duty
cycle variations in the clock.
Crystal Oscillator
The W78LE516 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must
be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from
each pin to ground.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
Publication Release Date: June 2000
- 5 -
Revision A1
Preliminary W78LE516
Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to
the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a
INT1
hardware reset or external interrupts INT0 to
when enabled and set to level triggered.
Reduce EMI Emission
The W78LE516 allows user to diminish the gain of on-chip oscillator amplifier by using programmer
to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must
be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect
the external crystal operating improperly at high frequency. The value of C1 ana C2 may need some
adjustment while running at lower gain.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78LE516 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
W78LE516 Special Function Registers (SFRs) and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
B8
FF
F7
EF
E7
DF
D7
CF
C7
BF
+B
CHPENR
00000000
00000000
+ACC
00000000
+P4
xxxx1111
+PSW
00000000
+T2CON
00000000
XICON
RCAP2L
RCAP2H
00000000
TL2
TH2
00000000
00000000
00000000
P4CONA
00000000
P4CONB
00000000
SFRAL
SFRAH
SFRFD
SFRCN
00000000
CHPCON
0xx00000
00000000
+IP
00000000
00000000
00000000
00000000
- 6 -
Preliminary W78LE516
Continued
B0
+P3
B7
AF
A7
9F
97
8F
87
P43AL
00000000
P42AL
P43AH
00000000
P42AH
00000000
+IE
A8
A0
98
90
88
80
P2ECON
0000xx00
00000000
+P2
00000000
00000000
11111111
+SCON
00000000
+P1
SBUF
xxxxxxxx
P41AL
00000000
TH0
P41AH
00000000
TH1
11111111
+TCON
00000000
+P0
TMOD
00000000
SP
TL0
TL1
00000000
DPL
00000000
DPH
00000000
00000000
PCON
P40AL
P40AH
11111111
00000111
00000000
00000000
00110000
00000000
00000000
Notes:
1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
Port 4
Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
-
Mode 0: P4.0 P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
CLR
INT2
if enabled.
external interrupt
and
Mode 1: P4.0 P4.3 are read strobe signals that are synchronized with
addresses. These signals can be used as chip-select signals for external peripherals.
WR
-
RD
signal at specified
-
Mode 2: P4.0 P4.3 are write strobe signals that are synchronized with
signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
RD WR
signal at
-
Mode 3: P4.0 P4.3 are read/write strobe signals that are synchronized with
or
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
INT2
/INT3
INT2
Two additional external interrupts,
and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
CLR
set/clear bits in the XICON register, one can use the "SETB (
"SETB 0C2H" sets the EX2 bit of XICON.
) bit" instruction. For example,
Publication Release Date: June 2000
Revision A1
- 7 -
Preliminary W78LE516
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3
PX2
EX2
IE2
IT2
PX3:External interrupt 3 priority high if set
EX3:External interrupt 3 enable if set
IE3:If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3:External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2:External interrupt 2 priority high if set
EX2:External interrupt 2 enable if set
IE2:If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2:External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt information:
INTERRUPT
SOURCE
VECTOR
POLLING
ENABLE
INTERRUPT
TYPE
ADDRESS SEQUENCE WITHIN REQUIRED
PRIORITY LEVEL
SETTINGS
IE.0
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
TCON.0
1
IE.1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
IE.5
-
6
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
P4CONB (C3H)
BIT
NAME
FUNCTION
7, 6
P43FUN1 00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
P43FUN0 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
- 8 -
Preliminary W78LE516
P4CONB (C3H), continued
BIT
NAME
FUNCTION
5, 4
P43CMP1 Chip-select signals address comparison:
P43CMP0 00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
-
01: Compare the 15 high bits (A15 A1) of address bus with the base address
register P43AH, P43AL.
-
10: Compare the 14 high bits (A15 A2) of address bus with the base address
register P43AH, P43AL.
-
11: Compare the 8 high bits (A15 A8) of address bus with the base address
register P43AH, P43AL.
3, 2
1, 0
P42FUN1 The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.
P42FUN0
P42CMP1 The P4.2 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.
P42CMP0
P4CONA (C2H)
BIT
NAME
FUNCTION
7, 6
P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.
P41FUN0
5, 4
3, 2
1, 0
P41CMP1 The P4.1 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.
P41CMP0
P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.
P40FUN0
P40CMP1 The P4.0 address comparator length control bits which are the similar
definition as P43CMP1, P43CMP0.
P40CMP0
P2ECON (AEH)
BIT
NAME
FUNCTION
7
P43CSINV The active polarity of P4.3 when pin P4.3 is defined as read and/or write
strobe signal.
= 1 : P4.3 is active high when pin P4.3 is defined as read and/or write strobe
signal.
= 0 : P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
6
5
P42CSINV The similarity definition as P43SINV.
P41CSINV The similarity definition as P43SINV.
Publication Release Date: June 2000
- 9 -
Revision A1
Preliminary W78LE516
P2ECON (AEH), continued
BIT
5
NAME
FUNCTION
P41CSINV The similarity definition as P43SINV.
P40CSINV The similarity definition as P43SINV.
4
3
-
-
-
-
Reserve
2
Reserve
1
0
0
0
Port 4 Base Address Registers
P40AH, P40AL:
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.
P41AH, P41AL:
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.
P42AH, P42AL:
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.
P43AH, P43AL:
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.
P4 (D8H)
BIT
NAME
FUNCTION
7
-
-
-
-
Reserve
6
5
4
3
2
1
0
Reserve
Reserve
Reserve
P43
Port 4 Data bit which outputs to pin P4.3 at mode 0.
Port 4 Data bit. which outputs to pin P4.2 at mode 0.
Port 4 Data bit. which outputs to pin P4.1at mode 0.
Port 4 Data bit which outputs to pin P4.0 at mode 0.
P42
P41
P40
- 10 -
Preliminary W78LE516
Here is an example to program the P4.0 as a write strobe signal at the I/O port address
-
-
1234H 1237H and positive polarity, and P4.1 P4.3 are used as general I/O ports.
MOV P40AH,#12H
MOV P40AL,#34H
; Base I/O address 1234H for P4.0
MOV P4CONA,#00001010B
MOV P4CONB,#00H
MOV P2ECON,#10H
; P4.0 a write strobe signal and address line A0 and A1 are masked.
; P4.1- P4.3 as general I/O port which are the same as PORT1
; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity
; default is negative.
MOV CHPENR,#00H
; Disable CHPCON write attribute.
-
Then any instruction MOVX @DPTR,A (with DPTR = 1234H 1237H) will generate the positive
polarity write strobe signal at pin P4.0. And the instruction MOV P4,#XX will output the bit3 to bit1 of
-
data #XX to pin P4.3 P4.1.
P4xCSINV
P4 REGISTER
P4.x
DATA I/O
RD_CS
MUX 4->1
WR_CS
READ
WRITE
RD/WR_CS
PIN
P4.x
ADDRESS BUS
P4xFUN0
P4xFUN1
EQUAL
REGISTER
P4xAL
P4xAH
Bit Length
P4.x INPUT DATA BUS
Selectable
comparator
REGISTER
P4xCMP0
P4xCMP1
In-System Programming (ISP) Mode
The W78LE516 equips one 64K byte of main MTP-ROM bank for application program (called
APROM) and one 4K byte of auxiliary MTP-ROM bank for loader program (called LDROM). In the
normal operation, the microcontroller executes the code in the APROM. If the content of APROM
needs to be modified, the W78LE516 allows user to activate the In-System Programming (ISP) mode
The CHPCON is read-only by default, software must write two
by setting the CHPCON register.
specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON
write attribute. Writing CHPENR register with the values except 87H and 59H will close
CHPCON register write attribute.
The W78LE516 achieves all in-system programming operations
including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the
Publication Release Date: June 2000
- 11 -
Revision A1
Preliminary W78LE516
bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode.
Because device needs proper time to complete the ISP operations before awaken from idle mode,
software may use timer interrupt to control the duration for device wake-up from idle mode. To
perform ISP operation for revising contents of APROM, software located at APROM setting the
CHPCON register then enter idle mode, after awaken from idle mode the device executes the
corresponding interrupt service routine in LDROM. Because the device will clear the program counter
while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service
routine will jump to 00H at LDROM area. The device offers a software reset for switching back to
Setting CHPCON register bit 0,
APROM while the content of APROM has been updated completely.
1 and 7 to logic-1 will result a software reset to reset the CPU
. The software reset serves as a
external reset. This in-system programming feature makes the job easy and efficient in which the
application needs to update firmware frequently. In some applications, the in-system programming
feature make it possible to easily update the system firmware without opening the chassis.
Note: The ISP Mode operates by supply voltage from 3.3V to 5.5V.
SFRAH, SFRAL:
The objective address of on-chip MTP-ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order
byte of address.
SFRFD: The programming data for on-chip MTP-ROM in programming mode.
SFRCN:
The control byte of on-chip MTP-ROM programming mode.
SFRCN (C7)
BIT
7
NAME
FUNCTION
-
Reserve.
6
WFWIN On-chip MTP-ROM bank select for in-system programming.
= 0: 64K bytes MTP-ROM bank is selected as destination for re-
programming.
= 1: 4K bytes MTP-ROM bank is selected as destination for re-programming.
5
4
OEN
CEN
MTP-ROM output enable.
MTP-ROM chip enable.
3, 2, 1, 0 CTRL[3:0] The flash control signals
MODE
WFWIN
CTRL<3:0>
0010
OEN CEN SFRAH, SFRAL
SFRFD
X
Erase 64KB APROM
Program 64KB APROM
Read 64KB APROM
Erase 4KB LDROM
Program 4KB LDROM
Read 4KB LDROM
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
X
0001
Address in
Address in
X
Data in
Data out
X
0000
0010
0001
Address in
Address in
Data in
Data out
0000
- 12 -
Preliminary W78LE516
In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT
NAME
FUNCTION
7
SWRESET When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This action will re-boot the microcontroller and start to normal operation. To
read this bit in logic-1 can determine that the F04KBOOT mode is running.
(F04KMODE)
6
5
4
-
Reserve.
-
Reserve.
ENAUXRAM
1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM
Must set to 0.
3
2
1
0
0
Must set to 0.
FBOOTSL The Program Location Select.
0: The Loader Program locates at the 64 KB APROM. 4KB LDROM is
destination for re-programming.
1: The Loader Program locates at the 4 KB memory bank. 64KB APROM is
destination for re-programming.
0
FPROGEN MTP-ROM Programming Enable.
= 1: enable. The microcontroller enter the in-system programming mode after
entering the idle mode and wake-up from interrupt. During in-system
programming mode, the operation of erase, program and read are
achieve when device enters idle mode.
= 0: disable. The on-chip flash memory is read-only. In-system
programmability is disabled.
Publication Release Date: June 2000
- 13 -
Revision A1
Preliminary W78LE516
F04KBOOT Mode (Boot From LDROM)
By default, the W78LE516 boots from APROM program after a power on reset. On some occasions,
user can force the W78LE516 to boot from the LDROM program via following settings. The possible
situation that you need to enter F04KBOOT mode when the APROM program can not run properly
and device can not jump back to LDROM to execute in-system programming function. Then you can
use this F04KBOOT mode to force the W78LE516 jumps to LDROM and executes in-system
programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to
switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY
and EJECT buttons on the panel. When the APROM program fails to execute the normal application
program. User can press both two buttons at the same time and then turn on the power of the
personal computer to force the W78LE516 to enter the F04KBOOT mode. After power on of personal
computer, you can release both buttons and finish the in-system programming procedure to update
EA
the APROM code. In application system design, user must take care of the P2, P3, ALE,
and
PSEN
pin value at reset to prevent from accidentally activating the programming mode or
F04KBOOT mode.
F04KBOOT MODE
P4.3 P2.7 P2.6
MODE
X
L
L
L
FO4KBOOT
FO4KBOOT
X
X
The Reset Timing For Entering
F04KBOOT Mode
P2.7
Hi-Z
Hi-Z
P2.6
RST
30 mS
10 mS
- 14 -
Preliminary W78LE516
The Algorithm of In-System Programming
Part 1:64KB APROM
procedure of entering
START
In-System Programming Mode
Enter In-System
Programming Mode ?
(conditions depend on
user's application)
No
Yes
Setting control registers
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Execute the normal application
program
Setting Timer (about 1.5 us)
and enable timer interrupt
END
Start Timer and enter idle Mode.
(CPU will be wakened from idle mode
by timer interrupt, then enter In-System
Programming mode)
CPU will be wakened by interrupt and
re-boot from 4KB LDROM to execute
the loader program.
Go
Publication Release Date: June 2000
Revision A1
- 15 -
Preliminary W78LE516
Part 2: 4KB LDROM
Go
Procedure of Updating
the 64KB APROM
Timer Interrupt Service Routine:
Stop Timer & disable interrupt
PGM
Yes
Yes
Is F04KBOOT Mode?
(CHPCON.7=1)
End of Programming ?
No
No
Reset the CHPCON Register:
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Setting Timer and enable Timer
interrupt for wake-up .
(50us for program operation)
Yes
Is currently in the
F04KBOOT Mode ?
No
Software reset CPU and
re-boot from the 64KB
APROM.
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H
Get the parameters of new code
(Address and data bytes)
Setting Timer and enable Timer
interrupt for wake-up .
(15 ms for erasing operation)
through I/O ports, UART or
other interfaces.
Setting erase operation mode:
MOV SFRCN,#22H
(Erase 64KB APROM)
Setting control registers for
programming:
Hardware Reset
to re-boot from
new 64 KB APROM.
(S/W reset is
invalid in F04KBOOT
Mode)
MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
Start Timer and enter IDLE
Mode.
MOV SFRCN,#21H
(Erasing...)
End of erase
operation. CPU will
be wakened by Timer
interrupt.
END
Executing new code
from address
00H in the 64KB APROM.
PGM
- 16 -
Preliminary W78LE516
SECURITY
During the on-chip MTP-ROM programming mode, the MTP-ROM can be programmed and verified
repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The
protection of MTP-ROM and those operations on it are described below.
The W78LE516 has several Special Setting Registers, including the Security Register and
Company/Device ID Registers, which can not be accessed in programming mode. Those bits of the
Security Registers can not be changed once they have been programmed from high to low. They can
only be reset through erase-all operation. The contents of the Company ID and Device ID registers
have been set in factory. The Security Register is located at the 0FFFFH of the LDROM space.
D7 D6 D5 D4 D3 D2 D1 D0
0000h
0FFFh
Company ID (#DAH)
Device ID (#62H)
Security Bits
1
1
0
1
1
0
1
0
4KB MTP ROM
Program Memory
LDROM
0
1
1
0
0
0
1
0
64KB MTP ROM
Program Memory
APROM
B2 B1 B0
B7 Reserved
B0: Lock bit, logic 0: active
B1: MOVC inhibit,
Reserved
logic 0: the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1: no restriction.
B2: Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable
FFFFh
Security Register
B07: Osillator Control
logic 0: 1/2 gain
logic 1: Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Registers
Lock bit
This bit is used to protect the customer's program code in the W78LE516. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can? be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
Publication Release Date: June 2000
- 17 -
Revision A1
Preliminary W78LE516
Oscillator Control
W78LE516/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer
to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must
be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may
improperly affect the external crystal operation at high frequency. The value of C1 and C2 may need
some adjustment while running at lower gain.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
SYMBOL
MIN.
-0.3
SS
MAX.
+6.0
DD
UNIT
V
DD
V
SS
V
-
IN
V
Input Voltage
V
-0.3
V
+0.3
V
A
Operating Temperature
Storage Temperature
T
0
60
°
C
C
ST
T
-55
+150
°
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC CHARACTERISTICS
SS
A
= 0V, T = 25 C, unless otherwise specified.
°
V
PARAMETER
SYM.
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
MAX.
5.5
5.5
20
DD
Operating Voltage
Operating Current
Idle Current
V
2.4
V
Without I.S.P.
With I.S.P.
3.3
V
DD
DD
I
-
mA
mA
mA
mA
No load V = 5.5V
DD
-
3
No load V = 2.4V
IDLE
DD
I
-
6
V
V
V
V
= 5.5V, Fosc = 20 MHz
= 2.4V, Fosc = 12 MHz
= 5.5V, Fosc = 20 MHz
= 2.4V, Fosc = 12 MHz
DD
DD
DD
-
-
1.5
50
PWDN
I
Power Down Current
m
A
-
20
m
A
IN1
IN2
LK
DD
Input Current
P1, P2, P3, P4
Input Current
RST
I
I
-50
+10
V
V
V
= 5.5V
m
A
IN
DD
= 0V or V
DD
-10
-10
+300
+10
= 5.5V
m
A
IN
DD
0 < V < V
DD
V
Input Leakage Current
I
= 5.5V
m
A
IN
DD
0V < V < V
EA
P0,
TL
DD
Logic 1 to 0 Transition
Current
I
[*4]
-500
-
V
= 5.5V
m
A
IN
V
= 2.0V
P1, P2, P3, P4
IL1
IL2
DD
DD
Input Low Voltage
V
0
0
0.8
0.5
V
V
= 4.5V
= 2.4V
V
V
EA
P0, P1, P2, P3, P4,
Input Low Voltage
RST[*1]
DD
DD
V
0
0
0.8
0.3
V
V
V
= 4.5V
= 2.4V
V
- 18 -
Preliminary W78LE516
DC Characteristics, continued
PARAMETER
SYM.
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
0
MAX.
0.8
IL3
DD
DD
DD
DD
Input Low Voltage
XTAL1 [*3]
V
V
V
V
V
V
V
V
V
= 4.5V
= 2.4V
= 5.5V
= 2.4V
0
0.4
IH1
DD
+0.2
Input High Voltage
V
2.4
1.4
V
DD
V
+0.2
EA
P0, P1, P2, P3, P4,
Input High Voltage
RST[*1]
IH2
DD
DD
DD
DD
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
V
3.5
1.7
3.5
2.4
-
V
V
V
V
+0.2
+0.2
+0.2
+0.2
V
V
V
V
V
V
V
V
= 5.5V
= 2.4V
= 5.5V
= 2.4V
IH3
Input High Voltage
XTAL1 [*3]
V
OL1
OL
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
V
0.45
= 4.5V, I = +2 mA
OL
-
0.25
0.45
0.25
= 2.4V, I = +1 mA
OL2
OL
V
-
= 4.5V, I = +4 mA
OL
-
= 2.4V, I = +2 mA
PSEN
P0, ALE,
[*2]
SK1
DD
V
DD
V
DD
V
DD
V
Sink Current
P1, P2, P3, P4
Sink Current
I
4
12
5.4
16
9
mA
mA
mA
mA
= 4.5V, Vin = 0.45V
= 2.4V, Vin = 0.45V
= 4.5V, Vin = 0.45V
= 2.4V, Vin = 0.4V
1.8
8
SK2
I
4.5
PSEN
P0, ALE,
OH1
Output High Voltage
P1, P2, P3, P4
V
2.4
1.4
2.4
1.4
-
-
-
-
V
V
V
V
DD
DD
DD
DD
OH
m
= 4.5V, I = -100 A
V
V
V
V
OH
m
= 2.4V, I = -8 A
OH2
V
Output High Voltage
OH
m
= 4.5V, I = -400 A
OH
m
= 2.4V, I = -200 A
P0, ALE, PSEN [*2]
Source Current
P1, P2, P3, P4
SR1
DD
V
DD
V
DD
V
DD
V
I
-100
-20
-8
-250
-50
= 4.5V, Vin = 2.4V
= 2.4V, Vin = 1.4V
= 4.5V, Vin = 2.4V
= 2.4V, Vin = 1.4V
m
A
m
A
SR2
Source Current
I
-14
mA
mA
-1.9
-3.8
P0, ALE, PSEN
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and
are tested in the external access mode.
PSEN
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
Publication Release Date: June 2000
Revision A1
- 19 -
Preliminary W78LE516
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
CP
specifications can be expressed in terms of multiple input clock periods (T ), and actual parts will
±
usually experience less than a 20 nS variation. The numbers below represent the performance
expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
PARAMETER
Operating Speed
SYMBOL
MIN.
TYP.
MAX.
UNIT
MHz
nS
NOTES
OP
F
0
-
-
-
-
24
-
1
2
3
3
CP
T
Clock Period
Clock High
Clock Low
25
10
10
CH
T
-
nS
CL
T
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
NOTES
AAS
T
Address Valid to ALE Low
Address Hold from ALE Low
-
-
-
-
-
-
4
1, 4
4
CP
1 T
D
D
D
-
-
-
AAH
T
CP
nS
1 T
1 T
APL
T
nS
CP
PSEN
ALE Low to
Low
PDA
CP
T
-
-
2 T
nS
nS
nS
nS
nS
2
3
PSEN
Low to Data Valid
PDH
CP
1 T
T
0
-
PSEN
PSEN
Data Hold after
Data Float after
High
High
PDZ
T
CP
1 T
0
-
ALW
CP
ALE Pulse Width
PSEN
T
2 T
3 T
-
-
4
4
CP
D
2 T
-
PSW
CP
T
CP
3 T -D
Pulse Width
Notes:
1. P0.0 P0.7, P2.0 P2.7 remain stable throughout entire memory cycle.
-
-
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to
going high.
PSEN
4. " " (due to buffer driving delay and wire loading) is 20 nS.
D
- 20 -
Preliminary W78LE516
Data Read Cycle
PARAMETER
RD
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
NOTES
1, 2
DAR
T
-
-
-
-
CP
3 T
CP+
D
D
D
-
3 T
ALE Low to
Low
DDA
T
CP
CP
CP
-
4 T
nS
1
RD
Low to Data Valid
DDH
T
0
2 T
2 T
-
nS
RD
RD
Data Hold from
Data Float from
High
High
DDZ
T
0
nS
DRD
T
CP
6 T
nS
2
CP
6 T
-
RD
Pulse Width
Notes:
1. Data memory access time is 8 TCP.
2. " " (due to buffer driving delay and wire loading) is 20 nS.
D
Data Write Cycle
PARAMETER
WR
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
DAW
T
-
-
-
CP
CP
D
+
D
D
D
D
3 T
-
3 T
ALE Low to
Low
WR
DAD
T
-
-
-
nS
CP
1 T
1 T
6 T
-
Data Valid to
Low
WR
DWD
T
CP
nS
-
Data Hold from
High
DWR
T
CP
CP
6 T
nS
-
WR
Pulse Width
Note: " " (due to buffer driving delay and wire loading) is 20 nS.
D
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
PDS
T
1 TCP
0
-
-
-
-
-
-
PDH
T
nS
PDA
T
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Publication Release Date: June 2000
- 21 -
Revision A1
Preliminary W78LE516
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
T
ALW
T
APL
PSEN
T
PSW
T
AAS
PORT 2
PORT 0
T
PDA
T
AAH
T
T
PDH, PDZ
A0-A7
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
T
T
DDA
DAR
T
T
DDH, DDZ
T
DRD
- 22 -
Preliminary W78LE516
Timing Waveforms, continued
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
T
DWD
T
DAD
T
T
DWR
DAW
Port Access Cycle
S5
S6
S1
XTAL1
ALE
T
PDS
T
PDA
T
PDH
PORT
DATA OUT
INPUT
SAMPLE
Publication Release Date: June 2000
Revision A1
- 23 -
Preliminary W78LE516
TYPICAL APPLICATION CIRCUIT
Expanded External Program Memory and Crystal
V
DD
AD0
38 AD1
37 AD2
31
19
39
AD0
AD1
AD2
AD3
AD4
AD5
3
4
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
A5
A6
A7
A8 25
A9 24
A10 21
A11 23
2
5
6
9
A0
A1
A2
A3
10
9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
A1
7
8
A2
XTAL1
AD3
AD4
AD5
36
35
34
8
13
14
7
10 u
A3
12 A4
15 A5
6
A4
R
18
9
5
XTAL2
A5
CRYSTAL
33 AD6
32 AD7
A6
A7
AD6 17
AD7 18
16
19
4
A6
3
A7
8.2 K
RST
INT0
A8
GND
1
21
22
23
24
25
26
27
28
A8
A9
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C1
C2
11
A10
A11
A12
A13
A14
A15
12
13
14
15
A10
A11
A12
A13
A14
A15
2
A12
INT1
T0
T1
74LS373
A13 26
A14 27
A15
1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
20
22
GND
CE
OE
RD
17
16
29
30
11
10
WR
27512
PSEN
ALE
TXD
RXD
W78LE516
Figure A
CRYSTAL
6 MHz
C1
C2
R
-
47P
47P
30P
10P
16 MHz
24 MHz
30P
15P
-
-
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A
2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
- 24 -
Preliminary W78LE516
Tipical Application Circuit, continued
Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
10
AD0
AD1
AD2
AD3
AD4
AD5
3
4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
2
5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
EA
9
8
6
7
XTAL1
8
13
14
9
7
OSCILLATOR
10 u
12
15
16
19
6
18
9
5
XTAL2
4
AD6 17
AD7 18
3
8.2 K
25
24
21
23
2
RST
INT0
GND
1
A8
A9
A10
A11
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
OC
G
11
A10
A11
A12
A13
12
A11
A12
A13
A14
13
14
15
74LS373
INT1
T0
T1
26
1
25 A12
26
27
28
A13
A14
A14
CE
1
GND 20
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
22
27
2
3
4
5
6
7
8
OE
RD
17
16
29
30
11
10
WR
WR
20256
PSEN
ALE
TXD
RXD
W78LE516
Figure B
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inch
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
5.334
0.210
0.010
0.150 0.155 0.160
0.254
3.81
1
A
3.937 4.064
A
B
2
0.016 0.018
0.406 0.457 0.559
0.022
0.054
0.050
1.219 1.27
1.372
0.356
0.048
0.008
1
B
c
0.203
0.010 0.014
2.055 2.070
0.254
52.20
15.24
D
52.58
D
E
E
e
L
a
40
21
15.494
0.610
0.590 0.600
14.986
13.72
0.540
13.84 13.97
2.54 2.794
0.545
0.550
0.110
1
1
0.090 0.100
2.286
3.048
0
0.120 0.130 0.140
3.302 3.556
15
1
E
0
15
0.630
0.670 16.00
0.090
17.01
2.286
0.650
16.51
e
S
A
20
1
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
A2
A
L
Base Plane
1
A
.
Seating Plane
B
e1
eA
a
B 1
6. General appearance spec. should be based on
final visual inspection spec.
Publication Release Date: June 2000
Revision A1
- 25 -
Preliminary W78LE516
Package Dimensions, continued
44-pin PLCC
H D
D
6
1
44
40
Dimension in inch
Min. Nom. Max. Min. Nom. Max.
Dimension in mm
Symbol
A
0.185
7
39
4.699
0.020
0.145
0.508
0.155 3.683
A
A
b
1
2
1
0.150
3.81
0.711
0.457
3.937
0.813
0.559
0.356
0.026 0.028
0.016 0.018
0.032
0.022
0.66
0.406
b
c
H E
GE
E
0.008 0.010 0.014 0.203 0.254
16.46 16.59 16.71
16.59
1.27 BSC
0.648 0.653 0.658
0.653
BSC
D
E
e
16.46
16.71
0.648
0.050
0.658
0.590
0.590
0.680
0.680
0.090
14.99 15.49 16.00
14.99 15.49 16.00
17.27 17.53 17.78
17.27 17.53 17.78
0.610 0.630
0.610 0.630
0.690 0.700
0.690 0.700
17
29
GD
G
H
H
E
18
28
D
c
E
0.100
2.54
0.110 2.296
0.004
2.794
0.10
L
y
L
Notes:
A2
A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
q
e
b
A1
3. Controlling dimension: Inches
4. General appearance spec. should be based
b 1
Seating Plane
y
G D
on final visual inspection spec.
44-pin PQFP
H D
D
Dimension in inch
Dimension in mm
Symbol
A
Nom.
---
Nom.
---
Min.
---
Max. Min.
Max.
---
34
44
---
---
0.002
0.075
0.01
0.01
0.02
0.25
2.05
0.05
1.90
0.25
0.5
1
A
0.081 0.087
2.20
0.45
A
b
c
2
33
1
0.014
0.006
0.018
0.010
0.35
0.101 0.152 0.254
0.004
0.390
0.394 0.398
0.394 0.398
0.031 0.036
10.00
10.00
0.80
9.9
9.9
10.1
10.1
D
E
e
0.390
0.025
0.510
E
HE
0.952
13.45
13.45
0.95
0.635
12.95
0.520
0.530
13.2
13.2
0.8
D
E
H
0.520
0.510
0.530 12.95
H
L
L
y
11
0.025 0.031
0.65
0.037
0.051 0.063 0.075 1.295
1.6
1.905
0.08
7
1
0.003
7
12
22
e
b
q
0
0
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
A
A2
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
q
A1
L
See Detail F
y
Seating Plane
on final visual inspection spec.
L 1
Detail F
- 26 -
Preliminary W78LE516
Application Note: In-system Programming Software Examples
This application note illustrates the in-system programmability of the Winbond W78LE516 MTP-ROM
microcontroller. In this example, microcontroller will boot from 64 KB APROM bank and waiting for a
key to enter in-system programming mode for re-programming the contents of 64 KB APROM. While
entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM
bank. The loader program erases the 64 KB APROM then reads the new code data from external
SRAM buffer (or through other interfaces) to update the 64KB APROM.
EXAMPLE 1:
;*******************************************************************************************************************
;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system
;* programming mode for updating the content of APROM code else executes the current ROM code.
;* XTAL = 16 MHz
;*******************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON EQU
CHPENR EQU
BFH
F6H
C4H
SFRAL
SFRAH
SFRFD
SFRCN
EQU
EQU C5H
EQU
EQU
C6H
C7H
ORG 0H
LJMP 100H
; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH
CLR
TR0
; TR0 = 0, STOP TIMER0
MOV TL0,R6
MOV TH0,R7
RETI
;************************************************************************
;* 64K APROM MAIN PROGRAM
;************************************************************************
ORG 100H
MAIN_64K:
MOV A,P1
; SCAN P1.0
ANL A,#01H
CJNE A,#01H,PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE
JMP NORMAL_MODE
PROGRAM_64K:
MOV CHPENR,#87H
; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE
; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE
; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE
; TR = 0 TIMER0 STOP
MOV CHPENR,#59H
MOV CHPCON,#03H
MOV TCON,#00H
MOV IP,#00H
; IP = 00H
Publication Release Date: June 2000
- 27 -
Revision A1
Preliminary W78LE516
MOV IE,#82H
MOV R6,#FEH
MOV R7,#FFH
MOV TL0,R6
; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE
; TL0 = FEH
; TH0 = FFH
MOV TH0,R7
MOV TMOD,#01H
MOV TCON,#10H
MOV PCON,#01H
; TMOD = 01H, SET TIMER0 A 16-BIT TIMER
; TCON = 10H, TR0 = 1,GO
; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM
; PROGRAMMING
;********************************************************************************
;* Normal mode 64KB APROM program: depending user's application
;********************************************************************************
NORMAL_MODE:
.
; User's application program
.
.
.
EXAMPLE 2:
;*****************************************************************************************************************************
;* Example of 4 KB LDROM program: This loader program will erase the 64KB APROM first, then reads the new
;* code from external SRAM and program them into 64 KB APROM bank. XTAL = 16 MHz
;*****************************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON
CHPENR
SFRAL
EQU
EQU
EQU
BFH
F6H
C4H
SFRAH
SFRFD
SFRCN
EQU C5H
EQU
EQU
C6H
C7H
ORG 000H
LJMP 100H
; JUMP TO MAIN PROGRAM
;************************************************************************
;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0
MOV TL0,R6
MOV TH0,R7
RETI
; TR0 = 0, STOP TIMER0
;************************************************************************
;* 4KB LDROM MAIN PROGRAM
;************************************************************************
ORG 100H
- 28 -
Preliminary W78LE516
MAIN_4K:
MOV CHPENR,#87H ; CHPENR = 87H, CHPCON WRITE ENABLE.
MOV CHPENR,#59H ; CHPENR = 59H, CHPCON WRITE ENABLE.
MOV A,CHPCON
ANL A,#80H
CJNE A,#80H,UPDATE_64K ; CHECK F04KBOOT MODE ?
MOV CHPCON,#03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.
MOV CHPENR,#00H ; DISABLE CHPCON WRITE ATTRIBUTE
MOV TCON,#00H
MOV TMOD,#01H
MOV IP,#00H
; TCON = 00H, TR = 0 TIMER0 STOP
; TMOD = 01H, SET TIMER0 A 16BIT TIMER
; IP = 00H
MOV IE,#82H
; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV R6,#FEH
MOV R7,#FFH
MOV TL0,R6
MOV TH0,R7
MOV TCON,#10H
MOV PCON,#01H
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE
UPDATE_64K:
MOV CHPENR,#00H ; DISABLE CHPCON WRITE-ATTRIBUTE
MOV TCON,#00H
MOV IP,#00H
; TCON = 00H , TR = 0 TIM0 STOP
; IP = 00H
MOV IE,#82H
MOV TMOD,#01H
MOV R6,#E0H
; IE = 82H, TIMER0 INTERRUPT ENABLED
; TMOD = 01H, MODE1
; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS.
DEPENDING
; ON USER'S SYSTEM CLOCK RATE.
MOV R7,#B1H
MOV TL0,R6
MOV TH0,R7
ERASE_P_4K:
MOV SFRCN,#22H
MOV TCON,#10H
MOV PCON,#01H
; SFRCN(C7H) = 22H ERASE 64K
; TCON = 10H, TR0 = 1,GO
; ENTER IDLE MODE (FOR ERASE OPERATION)
;*********************************************************************
;* BLANK CHECK
;*********************************************************************
MOV SFRCN,#0H
MOV SFRAH,#0H
MOV SFRAL,#0H
MOV R6,#FEH
MOV R7,#FFH
MOV TL0,R6
; READ 64KB APROM MODE
; START ADDRESS = 0H
; SET TIMER FOR READ OPERATION, ABOUT 1.5 mS.
MOV TH0,R7
BLANK_CHECK_LOOP:
SETB TR0
; ENABLE TIMER 0
MOV PCON,#01H
; ENTER IDLE MODE
Publication Release Date: June 2000
Revision A1
- 29 -
Preliminary W78LE516
MOV A,SFRFD
; READ ONE BYTE
CJNE A,#FFH,BLANK_CHECK_ERROR
INC SFRAL
; NEXT ADDRESS
MOV A,SFRAL
JNZ BLANK_CHECK_LOOP
INC SFRAH
MOV A,SFRAH
CJNE A,#0H,BLANK_CHECK_LOOP ; END ADDRESS = FFFFH
JMP PROGRAM_64KROM
BLANK_CHECK_ERROR:
MOV P1,#F0H
MOV P3,#F0H
JMP $
;*******************************************************************************
;* RE-PROGRAMMING 64KB APROM BANK
;*******************************************************************************
PROGRAM_64KROM:
MOV DPTR,#0H
MOV R2,#00H
MOV R1,#00H
MOV DPTR,#0H
MOV SFRAH,R1
MOV SFRCN,#21H
MOV R6,#BEH
MOV R7,#FFH
MOV TL0,R6
; THE ADDRESS OF NEW ROM CODE
; TARGET LOW BYTE ADDRESS
; TARGET HIGH BYTE ADDRESS
; EXTERNAL SRAM BUFFER ADDRESS
; SFRAH, TARGET HIGH ADDRESS
; SFRCN(C7H) = 21 (PROGRAM 64K)
; SET TIMER FOR PROGRAMMING, ABOUT 50 mS.
MOV TH0,R7
PROG_D_64K:
MOV SFRAL,R2
MOVX A,@DPTR
; SFRAL(C4H) = LOW BYTE ADDRESS
; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER?
; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE.
; SFRFD(C6H) = DATA IN
; TCON = 10H, TR0 = 1,GO
; ENTER IDLE MODE (PRORGAMMING)
MOV SFRFD,A
MOV TCON,#10H
MOV PCON,#01H
INC DPTR
INC R2
CJNE R2,#0H,PROG_D_64K
INC R1
MOV SFRAH,R1
CJNE R1,#0H,PROG_D_64K
;*****************************************************************************
; * VERIFY 64KB APROM BANK
;*****************************************************************************
MOV R4,#03H
MOV R6,#FEH
MOV R7,#FFH
MOV TL0,R6
MOV TH0,R7
MOV DPTR,#0H
MOV R2,#0H
; ERROR COUNTER
; SET TIMER FOR READ VERIFY, ABOUT 1.5 mS.
; The start address of sample code
; Target low byte address
- 30 -
Preliminary W78LE516
MOV R1,#0H
; Target high byte address
MOV SFRAH,R1
MOV SFRCN,#00H
; SFRAH, Target high address
; SFRCN = 00 (Read Flash code)
READ_VERIFY_64K:
MOV SFRAL,R2
MOV TCON,#10H
MOV PCON,#01H
INC R2
; SFRAL(C4H) = LOW ADDRESS
; TCON = 10H, TR0 = 1,GO
MOVX A,@DPTR
INC DPTR
CJNE A,SFRFD,ERROR_64K
CJNE R2,#0H,READ_VERIFY_64K
INC R1
MOV SFRAH,R1
CJNE R1,#0H,READ_VERIFY_64K
;******************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H
; CHPENR = 87H
; CHPENR = 59H
; CHPCON = 83H, SOFTWARE RESET.
ERROR_64K:
DJNZ R4,UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES.
; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
.
.
.
.
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
Headquarters
Unit 9 -15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852 -27513100
No. 4, Creation Rd. III,
Science -Based Industrial Park,
Hsinchu, Taiwan
TEL: 886 -3-5770066
FAX: 886 -3-5792766
2727 N. First Street, San Jose,
FAX: 852 -27552064
CA 95134, U.S.A.
http://www.winbond.com.tw/
TEL: 408 -9436666
FAX: 408 -5441798
Voice & Fax -on-demand: 886 -2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min -Sheng East Rd.,
Taipei, Taiwan
TEL: 886 -2-27190505
FAX: 886 -2-27197502
Note: All data and specifications are subject to change withou t notice.
Publication Release Date: June 2000
Revision A1
- 31 -
相关型号：
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