W83L197R-16_技术文档

W83L197R-16

2-CHIP 100MHZ CLOCK FOR BX NOTEBOOK

1.0 GENERAL DESCRIPTION

The W83L197R-16 is a Clock Synthesizer which provides all clocks required for high-speed RISC or

CISC microprocessor. Four different frequency of CPU, and PCI clocks are externally selectable with

smooth transitions. The 0.5% or 0.75% center type spread spectrum can be selected to reduce EMI.

The W83L197R-16 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU

¡ Ó

CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50

5% duty cycle. The fixed frequency outputs as REF, 48 MHz provide better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

·

Supports PentiumÔ II CPUs

4 sets of CPU frequencies selection

2 CPU clocks (one free running CPU clock)

6 PCI synchronous clocks(one free running PCI clock)

Optional single or mixed supply:

(Vdd3 = VddC= 3.3V±5%) or (VddC = 2.5V±5%)

Skew form CPU to PCI clock 1.5 to 4.0 ns, CPU leads.

CPU clock jitter less than 200ps

·

PCI_F,PCI1:6 clock skew less than 500ps

¡ Ó

0.5% or 0.75% center type spread spectrum function to reduce EMI

Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

·

48 MHz for USB

28-pin SOP package (209mil)

Publication Release Date: Mar. 1999

Revision 0.10

- 1 -

W83L197R-16

PRELIMINARY

3.0 BLOCK DIAGRAM

Vdd3

X1

X2

XTAL

OSC

REF2X

CPU_STOP#

SEL100/66#

VddC

PLL1

Spread

Spectrum

STOP

CPUCLK0

CPUCLK1

¡ Ò

2/3/4

Vdd3

PCI

clock

Divder

PCICLK_F

PCI_STOP#

PWR_DWN#

PCICLK(1:5)

STOP

Vdd3

5

Power

down

control

Vdd3

48MHz

PLL2

4.0 PIN CONFIGURATION

Vss

Vdd3

28

27

26

25

24

23

22

21

20

19

18

1

Xin

Xout

Vss

PCICLK_F

PCICLK1

2

3

4

5

6

7

8

9

REF2X/FS0*

VddC

CPUCLK0

CPUCLK1

Vss

Vdd3

Vss

PCI_STOP#

CPU_STOP#

PWR_DWN#

Vdd3

PCICLK2

PCICLK3

Vdd3

PCICLK4

PCICLK5

10

11

12

17

16

15

Vss

Vdd3

Vss

48MHz/SPREAD*

13

14

SEL100/66#

Publication Release Date: Mar. 1999

Revision 0.10

- 2 -

W83L197R-16

PRELIMINARY

5.0 PIN DESCRIPTION

IN - Input

OUT - Output

I/O - Bi-directional Pin

# - Low active

* - Internal 250kW pull-up

5.1 Crystal I/O

SYMBOL

I/O

FUNCTION

Xin

1

IN

Crystal input with internal loading capacitors and

feedback resistors.

Xout

2

OUT Crystal output at 14.318MHz nominally.

5.2 CPU, PCI Clock Outputs

SYMBOL

CPUCLK0

I/O

FUNCTION

24,23

OUT Low skew (< 250ps) clock outputs for host

frequencies such as CPU, Chipset and Cache.

VddC is the supply voltage for these outputs.

CPUCLK1

PCICLK [ 1:5 ]

PCICLK_F

5,7,8,10,11

OUT Low skew (< 250ps) PCI clock outputs.

4

PCI_STOP#

19

I/O

PCI_STOP# input used in power management mode

for synchronously stopping the all CPU clocks.

CPU_STOP#

18

this pin is CPU_STOP # and used in power

management mode for synchronously stopping the

all PCI clocks.

5.3 Fixed Frequency Outputs

SYMBOL

SEL100/66#

I/O

FUNCTION

15

26

IN

CPU clock frequency select pin.

REF2X / FS0*

I/O

Internal 250kW pull-up.

Latched input for FS0* to chose frequencies at initial

power up.

Reference clock during normal operation.

48MHz/SPREAD*

16

I/O

Internal 250kW pull-up.

48MHz output for USB during normal operation.

Latched input for SPREAD* to select the spread

spectrum spend at initial power up.

Publication Release Date: Mar. 1999

Revision 0.10

- 3 -

W83L197R-16

PRELIMINARY

5.4 Power Pins

SYMBOL

FUNCTION

VddC

25

Power supply for core logic and PLL circuitry. Connect

to 3.3V supply.

Vdd3

Vss

6,9,13,21,27

Power supply for others Connect to 3.3V supply.

3, 12,14,20,22,28 Circuit Ground.

6.0 FREQUENCY SELECTION

FS0*

SEL100/66#

CPUCLK0, CPUCLK1

100MHz

PCI

1

0

1

0

1

0

33.3MHz

33.4MHz

37.3MHz

34.33MHz

66.8MHz

112MHz

103MHz

7.0 FUNTION DESCRIPTION

7.1 SPREAD SPECTRUM FUNCTION SELECTION TABLE

SPREAD*

Spread Spectrum

¡ Ó

Type

Center

1

0

0.5%

¡ Ó

0.75%

7.2 POWER MANAGEMENT FUNCTIONS

The W83L197R-16 may be disabled in the low state according to the following table in order to

reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period

on transitions from running to stop. The CPU and PCI clocks transform between running and stop by

waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after

which high levels of the output are either enabled or disabled.

CPU_STOP#

PCI_STOP#

CPUCLK1

LOW

PCICLK1:5

LOW

PCICLK_F

RUNNING

XTAL & VCOs

RUNNING

0

1

0

1

0

1

LOW

RUNNING

LOW

RUNNING

Publication Release Date: Mar. 1999

Revision 0.10

- 4 -

W83L197R-16

PRELIMINARY

8.0 SPECIFICATIONS

8.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused

inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).

Symbol

Vdd , V_IN

T_STG

Parameter

Rating

Voltage on any pin with respect to GND

- 0.5 V to + 7.0 V

Storage Temperature

Ambient Temperature

Operating Temperature

- 65°C to + 150°C

- 55°C to + 125°C

0°C to + 70°C

T_B

T_A

8.2 AC CHARACTERISTICS

Vdd3 = VddCore = 3.3V

Parameter

±

5%, VddC = 2.5V

Symbol Min

45

±5% , T_A= 0°C to +70°C

Typ

Max

55

4

Units

%

Test Conditions

Output Duty Cycle

CPU to PCI Offset

50

Measured at 1.5V

1

ns

15 pF Load Measured at 1.5V

t_OFF

Skew (CPU-CPU), (PCI-

PCI)

250

ps

t_SKEW

Cycle to Cycle Jitter

200

500

ps

t_CCJ

t_JA

CPU

Absolute Jitter

Jitter Spectrum 20 dB

Bandwidth from Center

Output Rise (0.4V ~ 2.0V)

& Fall (2.0V ~0.4V) Time

BWJ

500

1.6

KHz

ns

0.4

15 pF Load on CPU and PCI

outputs

t_TLH

t_THL

Overshoot/Undershoot

Beyond Power Rails

Ring Back Exclusion

Vover

0.7

1.5

2.1

V

22 W at source of 8 inch PCB

run to 15 pF load

VRBE

Ring Back must not enter this

range.

Publication Release Date: Mar. 1999

Revision 0.10

- 5 -

W83L197R-16

PRELIMINARY

8.3 DC CHARACTERISTICS

Vdd3 = VddCore = 3.3V

Parameter

±

5%, VddC = 2.5V±5% , T_A= 0°C to +70°C

Symbol Min

Typ

Max

Units

Test Conditions

Input Low Voltage

0.8

V_IL

V_dc

mA

Input High Voltage

Input Low Current

Input High Current

2.0

V_IH

I_IL

-25

10

50

I_IH

Output Low Voltage

I_OL= 1 mA

CPU_F, CPU1

V_OL

mV_dc

Output High Voltage

I_OH= -1mA

3.1

CPU_F, CPU1

V_OH

V_dc

Output Low Current

27

20.5

40

57

53

85

74

37

55

87

88

44

97

139

140

152

76

mA

CPU_F,CPI1

PCI_F,PCI1:6

IOAPIC

I_OL

50

REF2X

25

48,24MHz

CPU_F,CPI1

PCI_F,PCI1:6

IOAPIC

Output High Current

I_OH

25

97

31

189

155

188

94

40

54

REF2X

27

48,24MHz

Publication Release Date: Mar. 1999

Revision 0.10

- 6 -

W83L197R-16

PRELIMINARY

8.4 BUFFER CHARACTERISTICS

8.4.1 TYPE 1 BUFFER FOR CPUCLK

Parameter

Symbol

I_OH(min)

I_OH(max)

Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

-27

mA

Vout = 1.0 V

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-27

mA

Vout = 2.0V

Vout = 1.2 V

I_OL(min)

I_OL(max)

T_RF(min)

27

mA

ns

Vout = 0.3 V

10 pF Load

Rise/Fall Time Min

Between 0.4 V and 2.0 V

0.4

Rise/Fall Time Max

Between 0.4 V and 2.0 V

1.6

ns

20 pF Load

T_RF(max)

8.4.2 TYPE 3 BUFFER FOR REF2X, 48MHZ

Parameter

Symbol Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

-29

mA

Vout = 1.0 V

I_OH(min)

I_OH(max)

I_OL(min)

I_OL(max)

T_RF(min)

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-23

mA

Vout = 3.135V

Vout = 1.95 V

29

mA

ns

Vout = 0.4 V

10 pF Load

Rise/Fall Time Min

Between 0.8 V and 2.0 V

1.0

Rise/Fall Time Max

4.0

ns

20 pF Load

T_RF(max)

Between 0.8 V and 2.0 V

8.4.3 TYPE 5 BUFFER FOR PCICLK(1:5,F)

Parameter

Symbol Min

Typ

Max

Units

Test Conditions

Pull-Up Current Min

-33

mA

Vout = 1.0 V

I_OH(min)

I_OH(max)

I_OL(min)

I_OL(max)

T_RF(min)

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

-33

mA

Vout = 3.135 V

Vout = 1.95 V

30

38

mA

ns

Vout = 0.4 V

15 pF Load

Rise/Fall Time Min

Between 0.8 V and 2.0 V

0.5

Rise/Fall Time Max

2.0

ns

30 pF Load

T_RF(max)

Between 0.8 V and 2.0 V

Publication Release Date: Mar. 1999

Revision 0.10

- 7 -

W83L197R-16

PRELIMINARY

9.0 OPERATION OF DUAL FUCTION PINS

Pin16 and pin26 are dual function pins and are used for selecting different functions in this device

(see Pin description). During power up, these pins are in input mode (see Fig1), therefore, and are

considered input select pins. When Vdd reaches 2.5V, the logic level that is present on these pins

are latched into their appropriate internal registers. Once the correct information are properly latched,

these pins will change into output pins and will be pulled low by default. At the end of the power up

timer (within 3 ms) outputs starts to toggle at the specified frequency.

2.5V

Vdd

Output

pull-low

#16 48/SPREAD*

#26 REF2X/FS0*

Output

tri-state

Within 3ms

Input

Output

pull-low

Output

tri-state

All other clocks

Each of these pins are a large pull-up resistor ( 250 kW @3.3V ) inside. The default state will be logic

1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these

dual function pins. Under these conditions, an external 10 kW resistor is recommended to be

connected to Vdd if logic 1 is expected. The same 10 kW connection to ground if a logic 0 is desired.

The 10 kW resistor should be place before the serious terminating resistor. Note that these logic will

only be latched at initial power on.

If optional EMI reducing capacitor are needed, they should be placed as close to the series

terminating resistor as possible and after the series terminating resistor. These capacitor has typical

values ranging from 4.7pF to 22pF.

Publication Release Date: Mar. 1999

- 8 -

Revision 0.10

W83L197R-16

PRELIMINARY

Vdd

Series

Terminating

Resistor

W

10k

Clock

Trace

Device

EMI

Reducing

Cap

10kW

Optional

Ground

Programming Header

Vdd Pad

Ground Pad

Series

Terminating

Resistor

10k

W

Clock

Trace

Device

EMI

Reducing

Cap

Optional

Ground

Publication Release Date: Mar. 1999

Revision 0.10

- 9 -

W83L197R-16

PRELIMINARY

10.0 ORDERING INFORMATION

Part Number

Package Type

Production Flow

W83L197R-16

28 PIN SOP (209mil)

Commercial, 0°C to +70°C

11.0 HOW TO READ THE TOP MARKING

W83L197R-16

28051234

814OBB

1st line: Winbond logo and the type number: W83L197R-16

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 814 G B B

814: packages made in '98, week 14

G: assembly house ID; A means ASE, S means SPIL, G means GR

BB: IC revision

All the trade marks of products and companies mentioned in this data sheet belong to

their respective owners.

Publication Release Date: Mar. 1999

- 10 -

Revision 0.10

W83L197R-16

PRELIMINARY

12.0 PACKAGE DRAWING AND DIMENSIONS

28-SOP

D

15

2

DIMENSION IN MM DIMENSION IN INCH

MIN. NOM MAX. MIN. NOM MAX.

SYMBOL

2.00

0.079

A

A1

A2

b

0.05

1.65 1.75 1.85

0.002

0.065

DTEAIL A

0.069

0.073

0.015

0.010

0.22

0.09

0.38 0.009

0.25 0.004

H

E

c

10.20

5.30 5.60

7.80 8.20

0.65

9.90

5.00

0.389 0.401 0.413

0.197 0.209 0.220

0.291 0.307 0.323

0.0256

10.50

D

E

H_E

7.40

e

L

L1

0.95

0.037

0.55 0.75

1.25

0.021 0.030

0.050

0.004

8

Y

0.10

8

1

14

0

q

A2

A

SEATING PLANE

Y

q

L

L1

DETAIL A

e

b

A1

Headquarters

No. 4, Creation Rd. III

Science-Based Industrial Park

Hsinchu, Taiwan

TEL: 886-35-770066

Winbond Electronics

(North America) Corp.

2730 Orchard Parkway

San Jose, CA 95134 U.S.A.

TEL: 1-408-9436666

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II

123 Hoi Bun Rd., Kwun Tong

Kowloon, Hong Kong

TEL: 852-27516023-7

FAX: 852-27552064

FAX: 886-35-789467

www: http://www.winbond.com.tw/

FAX: 1-408-9436668

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.

Taipei, Taiwan

TEL: 886-2-7190505

FAX: 886-2-7197502

TLX: 16485 WINTPE

Please note that all data and specifications are subject to change without notice. All the

trade marks of products and companies mentioned in this data sheet belong to their

respective owners.

These products are not designed for use in life support appliances, devices, or systems

where malfunction of these products can reasonably be expected to result in personal

injury. Winbond customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Winbond for any damages resulting

from such improper use or sale.

Publication Release Date: Mar. 1999

- 11 -

Revision 0.10


型号：	W83L197R-16
厂家：	WINBOND
描述：	2-CHIP 100MHZ CLOCK FOR BX NOTEBOOK 双芯片100MHZ时钟BX笔记本时钟
文件：	总11页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W83L197R-16 [WINBOND]

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