W981216BH75I [WINBOND]
Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54;
| 型号： | W981216BH75I |
| 厂家： | 
WINBOND |
| 描述： | Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, TSOP2-54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总43页 (文件大小：1373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W981216BH
´ 4 BANKS ´ 16 BITS SDRAM
2M
Table of Contents-
1. GENERAL DESCRIPTION ..................................................................................................................3
2. FEATURES..........................................................................................................................................3
3. AVAILABLE PART NUMBER ..............................................................................................................3
4. PIN CONFIGURATION........................................................................................................................4
5. PIN DESCRIPTION .............................................................................................................................5
6. BLOCK DIAGRAM...............................................................................................................................6
7. ELECRICAL CHARACTERISTICS......................................................................................................7
Absolute Maximum Ratings...................................................................................................................... 7
Recommended DC Operating Conditions ................................................................................................ 7
Capacitance.............................................................................................................................................. 7
AC Characteristics and Operating Condition............................................................................................ 8
DC Characteristics.................................................................................................................................... 9
8. OPERATION MODE..........................................................................................................................11
9. FUNCTIONAL DESCRIPTION ..........................................................................................................12
Power Up and Initialization ..................................................................................................................... 12
Programming Mode Register.................................................................................................................. 12
Bank Activate Command ........................................................................................................................ 12
Read and Write Access Modes .............................................................................................................. 12
Burst Read Command ............................................................................................................................ 13
Burst Write Command ............................................................................................................................ 13
Read Interrupted by a Read ................................................................................................................... 13
Read Interrupted by a Write.................................................................................................................... 13
Write Interrupted by a Write.................................................................................................................... 13
Write Interrupted by a Read.................................................................................................................... 13
Burst Stop Command ............................................................................................................................. 13
Addressing Sequence of Sequential Mode............................................................................................. 14
Addressing Sequence of Interleave Mode.............................................................................................. 14
Auto Pre-charge Command.................................................................................................................... 15
Pre-charge Command ............................................................................................................................ 15
Self Refresh Command .......................................................................................................................... 15
Power Down Mode ................................................................................................................................. 15
No Operation Command......................................................................................................................... 16
Deselect Command ................................................................................................................................ 16
Clock Suspend Mode.............................................................................................................................. 16
Publication Release Date: September 20, 2001
- 1 -
Revision A3
W981216BH
10. TIMING WAVEFORMS....................................................................................................................17
Command Input Timing .......................................................................................................................... 17
Read Timing ........................................................................................................................................... 18
Control Timing of Input/Output Data....................................................................................................... 19
11. OPERATING TIMING EXAMPLE....................................................................................................21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ................................................................ 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Pre-charge).................................... 22
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ................................................................ 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Pre-charge).................................... 24
Interleaved Bank Write (Burst Length = 8) ............................................................................................. 25
Interleaved Bank Write (Burst Length = 8, Auto Pre-charge) ................................................................. 26
Page Mode Read (Burst Length = 4, CAS Latency = 3)......................................................................... 27
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ............................................................... 28
Auto Pre-charge Read (Burst Length = 4, CAS Latency = 3)................................................................. 29
Auto Pre-charge Write (Burst Length = 4) .............................................................................................. 30
Auto Refresh Cycle................................................................................................................................. 31
Self Refresh Cycle.................................................................................................................................. 32
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ....................................................... 33
Power Down Mode ................................................................................................................................. 34
Auto Pre-charge Timing (Read Cycle).................................................................................................... 35
Auto Pre-charge Timing (Write Cycle).................................................................................................... 36
Timing Chart of Read to Write Cycle ...................................................................................................... 37
Timing Chart of Write to Read Cycle ...................................................................................................... 37
Timing Chart of Burst Stop Cycle (Burst Stop Command)...................................................................... 38
Timing Chart of Burst Stop Cycle (Pre-charge Command)..................................................................... 38
CKE/DQM Input Timing (Write Cycle) .................................................................................................... 39
CKE/DQM Input Timing (Read Cycle) .................................................................................................... 40
Self Refresh/Power Down Mode Exit Timing.......................................................................................... 41
12. PACKAGE DIMENSION ..................................................................................................................42
54L TSOP (II)-400 mil............................................................................................................................. 42
- 2 -
W981216BH
1. GENERAL DESCRIPTION
W981216BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words ´ 4 banks ´ 16 bits. Using pipelined architecture and 0.175 mm process technology,
W981216BH delivers a data bandwidth of up to 166M words per second (-6). For different application,
W981216BH is sorted into four speed grades: -6, -7, -75, and -8H. The -7 is compliant to the 166 MHz
/CL3 specification, the -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is
compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification. For
handheld device application, we also provide a low power option, the grade of 75L, with Self Refresh
Current under 600 mA, and an industrial temperature option, the grade of 75I, which is guaranteed to
support -40°C – 85°C.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981216BH is ideal for main memory in
high performance applications.
2. FEATURES
· 3.3V ±0.3V Power Supply
· Up to 166 MHz Clock Frequency
· 2,097,152 Words ´ 4 banks ´ 16 bits organization
· Self Refresh Mode: Standard and Low Power
· CAS Latency: 2 and 3
· Burst Length: 1, 2, 4, 8, and full page
· Burst Read, Single Writes Mode
· Byte Data Controlled by DQM
· Auto pre-charge and Controlled Pre-charge
· 4K Refresh cycles / 64 mS
· Interface: LVTTL
· Packaged in TSOP II 54 pin, 400 mil - 0.80
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED
MAXIMUM SELF
OPERATING
REFRESH CURRENT
TEMPERATURE
W981216BH-6
166 MHz/CL3
PC133/CL2
PC133/CL3
PC133/CL3
PC133/CL3
PC100/CL2
2 mA
2 mA
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
0°C - 70°C
W981216BH-7
W981216BH-75
W981216BH75L
W981216BH75I
W981216BH-8H
2 mA
600 mA
600 mA
2 mA
Publication Release Date: September 20, 2001
Revision A3
- 3 -
W981216BH
4. PIN CONFIGURATION
VCC
VSS
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
DQ15
DQ0
2
VSSQ
3
VCCQ
DQ1
DQ14
DQ13
4
DQ2
5
VSSQ
VCCQ
6
DQ12
DQ11
DQ3
DQ4
7
8
VCCQ
V
SSQ
9
DQ10
DQ9
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VSSQ
VCCQ
DQ8
VSS
NC
DQ7
VCC
LDQM
WE
UDQM
CLK
CKE
NC
CAS
RAS
CS
A11
A9
BS0
BS1
A10/AP
A0
A8
A7
A6
A1
A5
A2
A4
A3
VCC
VSS
- 4 -
W981216BH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME
FUNCTION
DESCRIPTION
Address
Multiplexed pins for row and column address.
23 - 26, 22,
29 - 35
A0 - A11
Row address: A0 - A11. Column address: A0 - A8.
20, 21
BS0, BS1
Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
Data Input/
Output
Multiplexed pins for data output and input.
DQ0 -
DQ15
19
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
CS
18
Row Address Command input. When sampled at the rising edge of
RAS
Strobe
the clock, RAS , CAS and WE define the
operation to be executed.
17
Column Address
Strobe
CAS
WE
Referred to RAS
16
Write Enable
Referred to RAS
39, 15
UDQM/
LDQM
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38
37
CLK
CKE
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
Clock Enable CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
1, 14, 27
28, 41, 54
3, 9, 43, 49
VCC
VSS
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
VCCQ
Power (+3.3V) Separated power from VCC, used for output buffers to
for I/O Buffer improve noise.
6, 12, 46, 52
36, 40
VSSQ
NC
Ground for I/O Separated ground from VSS, used for output buffers to
Buffer
improve noise.
No Connection No connection
Publication Release Date: September 20, 2001
Revision A3
- 5 -
W981216BH
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
CONTROL
SIGNAL
GENERATOR
RAS
COMMAND
DECODER
CAS
COLUMN DECODER
COLUMN DECODER
W E
R
R
O
W
O
W
D
E
C
O
D
E
R
D
E
C
O
D
E
R
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A10
MODE
REGISTER
A0
SENSE AMPLIFIER
SENSE AMPLIFIER
ADDRESS
BUFFER
A9
DMn
A11
BS0
BS1
DQ0
DATA CONTROL
CIRCUIT
DQ
DQ15
BUFFER
REFRESH
COUNTER
COLUMN
UDQM
LDQM
COUNTER
COLUMN DECODER
COLUMN DECODER
R
O
W
R
O
W
CELL ARRAY
BANK #3
CELL ARRAY
BANK #2
D
E
C
O
D
E
R
D
E
C
O
D
E
R
SENSE AMPLIFIER
SENSE AMPLIFIER
Note: The cell array configuration is 4096 * 512 * 16.
- 6 -
W981216BH
7. ELECRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Input/Output Voltage
SYMBOL
VIN, VOUT
VCC, VCCQ
TOPR
RATING
UNIT
V
-0.3 - VCC +0.3
-0.3 - 4.6
0 - 70
Power Supply Voltage
V
Operating Temperature (-6/-7/-75/75L/-8H)
Operating Temperature (75I)
Storage Temperature
°C
°C
°C
°C
W
TOPR
-40 - 85
-55 - 150
260
TSTG
Soldering Temperature (10s)
Power Dissipation
TSOLDER
PD
1
Short Circuit Output Current
IOUT
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Recommended DC Operating Conditions
(TA = 0 to 70°C for -6/-7/-75/75L/-8H, TA = -40 to 85°C for 75I)
PARAMETER
Power Supply Voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
VCCQ
VIH
3.0
3.0
2.0
-0.3
3.3
3.3
-
3.6
3.6
V
V
V
V
Power Supply Voltage (for I/O Buffer)
Input High Voltage
VCC +0.3
0.8
Input Low Voltage
VIL
-
Note: VIH (max) = VCC/ VCCQ +1.2V for pulse width < 5 nS
VIL (min) = VSS/ VSSQ -1.2V for pulse width < 5 nS
Capacitance
(VCC = 3.3V, f = 1 MHz, TA = 25°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
CI
-
3.8
pf
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM,
CKE)
Input Capacitance (CLK)
CCLK
CIO
-
-
3.5
6.5
pf
pf
Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested.
Publication Release Date: September 20, 2001
Revision A3
- 7 -
W981216BH
AC Characteristics and Operating Condition
(Vcc = 3.3V ±0.3V, TA = 0 to 70°C for -6/-7/-75/75L/-8H, TA = -40 to 85°C for 75I ; Notes: 5, 6, 7, 8)
PARAMETER
SYM.
UNIT
-6
-7
-75/75L/75I
-8H
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Ref/Active to Ref/Active
Command Period
57
57
65
68
tRC
tRAS
tRCD
tCCD
tRP
Active to Pre-charge Command
Period
42 100000 42 100000 45 100000 48 100000
nS
Active to Read/Write Command
Delay Time
15
1
15
1
20
1
20
1
Read/Write(a) to Read/Write(b)
Command Period
Cycle
Pre-charge to Active Command
Period
15
12
15
15
20
15
20
20
Active(a) to Active(b) Command
Period
tRRD
tWR
Write Recovery Time
CL* = 2
7.5
6
7.5
7
10
7.5
10
10
8
CL* = 3
CL* = 2
CL* = 3
CLK Cycle Time
7.5
6
1000
1000
7.5
7
1000
1000
1000
1000
10
8
1000
1000
tCK
7.5
2.5
2.5
CLK High Level width
CLK Low Level width
Access Time from
CLK
tCH
tCL
tAC
2
2.5
2.5
3
2
3
CL* = 2
CL* = 3
5.4
5
5.4
5.4
6
6
6
5.4
nS
Output Data Hold Time
2.75
2.75
3
3
3
3
3
3
tOH
tHZ
Output Data High Impedance
Time
6
7
7.5
8
Output Data Low Impedance Time
Power Down Mode Entry Time
0
0
0
0
0
0
0
0
tLZ
tSB
tT
6
7
7.5
10
8
Transition Time of CLK
(Rise and Fall)
0.5
10
0.5
10
0.5
0.5
10
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2
1
2
1
2
1
2
1
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
64
64
64
64
mS
nS
Mode Register Set Cycle Time
*CL = CAS Latency
12
14
15
16
- 8 -
W981216BH
DC Characteristics
(VCC = 3.3V ±0.3V, TA = 0 to 70°C for -6/-7/-75/75L/-8H, TA = -40 to 85°C for 75I)
PARAMETER
SYM.
-6
MAX.
85
-7
MAX.
80
-75/75L/75I
MAX.
-8H
MAX.
70
UNIT NOTES
Operating Current
1 bank
ICC1
75
3
operation
tCK = min., tRC = min.
Active pre-charge
command cycling without
burst operation
Standby Current
CKE = VIH
ICC2
45
40
35
30
3
3
tCK = min, CS = VIH
VIH/L = VI (min) /VIL (max.)
Bank: Inactive state
CKE = VIL
(Power Down
mode)
ICC2P
ICC2S
1
1
1
1
Standby Current
CKE = VIH
10
10
10
10
CLK = VIL, CS = VIH
VIH/L = VIH (min) /VIL (max)
BANK: Inactive state
CKE = VIL
(Power down
mode)
ICC2PS
1
1
1
1
mA
No Operating Current
CKE = VIH
ICC3
65
10
60
10
55
10
50
10
tCK = min., CS = VIH (min)
BANK: Active state
(4 banks)
CKE = VIL
(Power down
mode)
ICC3P
Burst Operating Current
ICC4
ICC5
105
180
100
170
95
90
3, 4
3
tCK = min.
Read/ Write command cycling
Auto Refresh Current
160
150
tCK = min.
Auto refresh command cycling
Self Refresh Current
Self Refresh Mode
CKE = 0.2V
Normal
(-6/-7/-75/-8H)
2
-
2
-
2
2
-
ICC6
Low Power
(75L/75I)
0.6
PARAMETER
Input Leakage Current
SYMBOL
MIN.
MAX.
UNIT
NOTES
II(L)
-5
-5
2.4
-
5
mA
mA
V
(0V £ VIN £ VCC, all other pins not under test = 0V)
Output Leakage Current
IO(L)
VOH
VOL
5
(Output disable, 0V £ VOUT £ VCCQ)
²
²
LVTTL Output H Level Voltage
(IOUT = -2 mA)
-
²
²
LVTTL Output L Level Voltage
(IOUT = 2 mA)
0.4
V
Publication Release Date: September 20, 2001
Revision A3
- 9 -
W981216BH
Notes:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the
devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the "Functional Description" section.
6. AC Testing Conditions
Output Reference Level
Output Load
1.4V/1.4V
See diagram below
2.4V/0.4V
2 nS
Input Signal Levels
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
1.4V
1.4 V
50 ohms
Z = 50 ohms
Output
50 pF
AC TEST LOAD
7. Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
- 10 -
W981216BH
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND
Bank Active
DEVICE
STATE
CKEN-1
CKEN
DQM BS0, 1 A10
A0
A11
- A9
CS
RAS
CAS
WE
Idle
Any
H
H
H
H
H
H
H
H
H
H
H
H
H
L
x
x
x
x
x
x
x
x
x
x
x
H
L
H
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
v
x
v
v
v
v
v
x
x
x
x
x
x
v
L
H
L
H
L
H
v
v
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
H
H
H
L
L
L
L
L
H
H
x
H
L
Bank Pre-charge
Pre-charge All
Write
x
Any
x
L
L
Active (3)
Active (3)
Active (3)
Active (3)
Idle
v
H
H
H
H
L
L
Write with Auto Pre-charge
Read
v
L
v
H
H
L
Read with Auto Pre-charge
Mode Register Set
No-operation
v
v
Any
x
x
H
H
x
H
L
Burst Stop
Active (4)
Any
x
x
Device Deselect
Auto Refresh
x
x
x
Idle
x
x
L
L
L
x
H
H
x
Self Refresh Entry
Self Refresh Exit
Idle
x
x
L
idle
x
x
x
(S.R.)
Active
L
H
L
x
x
x
x
x
x
x
x
L
x
H
x
H
x
x
x
Clock Suspend Mode Entry
Power Down Mode Entry
H
Idle
H
L
x
x
x
x
H
x
x
x
Active (5)
Active
H
L
L
x
x
x
x
x
x
x
x
L
x
H
x
H
x
x
x
Clock Suspend Mode Exit
Power Down Mode Exit
H
Any
L
H
x
x
x
x
H
x
x
x
(power
Active
L
H
x
x
x
x
x
x
x
x
L
x
H
x
H
x
x
x
Data Write/Output Enable
Data Write/Output Disable
H
L
Active
H
x
H
x
x
x
x
x
x
x
Notes:
(1) v = valid
x = Don't care
L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
Publication Release Date: September 20, 2001
Revision A3
- 11 -
W981216BH
9. FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when
the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V on
any of the input pins or Vcc supplies. After power up, an initial pause of 200 mS is required followed by
a pre-charge of all banks using the pre-charge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been pre-charged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a pre-charged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this
cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be pre-charged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max).
Read and Write Access Modes
After a bank has been activated , a read or write cycle can be followed. This is accomplished by
setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage
level defines whether the access cycle is a read operation (WE high), or a write operation (WE low).
The address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be pre-charged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank
Read or Write operations are possible. By using the programmed burst length and alternating the
access and pre-charge operations between multiple banks, seamless data access operation among
many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.
- 12 -
W981216BH
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS
and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding
RAS high at the rising edge of the clock. The address inputs determine the starting column address.
Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the
Write Command is issued. The remaining data inputs must be supplied on each subsequent rising
clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst
Publication Release Date: September 20, 2001
- 13 -
Revision A3
W981216BH
read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write
operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
BURST LENGTH
n
BL = 2 (disturb address is A0)
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
No address carry from A0 to A1
BL = 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
BL = 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Data 0
Data 1
ACCESS ADDRESS
BUST LENGTH
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
BL = 4
BL = 8
- 14 -
W981216BH
Auto Pre-charge Command
If A10 is set to high when the Read or Write Command is issued, then the auto pre-charge function is
entered. During auto pre-charge, a Read Command will execute as normal with the exception that the
active bank will begin to pre-charge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto pre-charge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Pre-charge Command is prohibited during
a read or write cycle with auto pre-charge. Once the pre-charge operation has started, the bank
cannot be reactivated until the Pre-charge time (tRP) has been satisfied. Issue of Auto Pre-charge
command is illegal if the burst is set to full page length. If A10 is high when a Write Command is
issued, the Write with Auto Pre-charge function is initiated. The SDRAM automatically enters the pre-
charge operation one clock delay from the last burst write cycle. This delay is referred to as Write tWR
.
The bank undergoing auto pre-charge can not be reactivated until tWR and tRP are satisfied. This is
referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto Pre-charge
Command, the interval between the Bank Activate Command and the beginning of the internal pre-
charge operation must satisfy tRAS (min).
Pre-charge Command
The Pre-charge Command is used to pre-charge or close a bank that has been activated. The Pre-
charge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the
clock. The Pre-charge Command can be used to pre-charge each bank separately or all banks
simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be pre-
charged when the command is issued. After the Pre-charge Command is issued, the pre-charged
bank must be reactivated before a new read or write access can be executed. The delay between the
Pre-charge Command and the Activate Command must be greater than or equal to the Pre-charge
time (tRP).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at
the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once
the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the
SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled.
The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits
Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC
cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
Publication Release Date: September 20, 2001
- 15 -
Revision A3
W981216BH
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the
clock. A No Operation Command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
- 16 -
W981216BH
10. TIMING WAVEFORMS
Command Input Timing
t
CL
tCH
t
CK
V
IH
IL
CLK
CS
V
t
T
tT
t
CMS
tCMH
t
CMH
t
CMS
t
CMS
t
CMH
RAS
t
t
CMS
t
t
CMH
CAS
WE
CMS
CMH
t
AS
tAH
A0-A11
BS0, 1
t
CKS
t
CKH
tCKH
tCKS
t
CKS
t
CKH
CKE
Publication Release Date: September 20, 2001
Revision A3
- 17 -
W981216BH
Timing Waveforms, continued
Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A11
BS0, 1
t
AC
t
AC
t
HZ
t
OH
t
OH
t
LZ
Valid
Data-Out
Valid
Data-Out
DQ
Read Command
Burst Length
- 18 -
W981216BH
Timing Waveforms, continued
Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
tCMS
tCMH
tCMH
tCMS
DQM
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0 -15
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0 -15
Control Timing of Output Data
(Output Enable)
CLK
tCMH
tCMH
tCMS
tCMS
DQM
tAC
tHZ
tAC
tAC
tOH
tAC
tLZ
tOH
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
OPEN
DQ0 -15
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tAC
tAC
tOH
tAC
tAC
tOH
tOH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ0 -15
Publication Release Date: September 20, 2001
Revision A3
- 19 -
W981216BH
Timing Waveforms, continued
Mode Register Set Cycle
tRSC
CLK
tCMS
tCMS
tCMS
tCMH
tCMH
tCMH
CS
RAS
CAS
WE
tCMS
tCMH
tAS
tAH
A0-A11
BS0,1
Register
set data
next
command
A2 A1A0
BurstLength
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Sequential
Interleave
Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
4
8
2
4
A8
Addressing Mode
CAS Latency
Reserved
FullPage
Reserved
A3
0
1
Addressing Mode
Sequential
Interleave
"0" (Test Mode)
"0"
Reserved
A6 A5A4
CAS Latency
Reserved
Reserved
2
3
Reserved
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
WriteMode
"0"
"0"
BS0 "0"
"0"
Reserved
A9
0
1
Single Write Mode
Burst read andBurst write
Burst read andsingle write
BS1
- 20 -
W981216BH
11. OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRP
tRP
tRAS
tRAS
WE
BS0
BS1
tRCD
tRCD
tRCD
tRCD
A10
RAa
RAa
RBb
RAc
RBd
RBd
RAe
A0-A9,
A11
CBx
RBb
RAc
CAy
RAe
CAw
CBz
DQM
CKE
DQ
tAC
tAC
tAC
tAC
bx3
bx1
aw0
aw2
aw3
bx0
bx2
cy0
cy1
cy2
cy3
aw1
tRRD
tRRD
tRRD
tRRD
Precharge
Read
Active
Read
Active
Bank #0
Bank #1
Read
Active
Precharge
Read
Precharge
Active
Active
Bank #2
Bank #3
Idle
Publication Release Date: September 20, 2001
Revision A3
- 21 -
W981216BH
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Pre-charge)
(CLK = 100 MHz)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRAS
tRP
tRP
tRAS
WE
BS0
BS1
A10
tRCD
tRCD
tRCD
tRCD
RAe
RBd
RAa
RBb
RAc
A0-A9,
A11
RAa
CAw
CAy
CBz
RAe
CBx
RBb
RAc
RBd
DQM
CKE
tAC
tAC
tAC
tAC
DQ
aw0 aw1 aw2
aw3
bx0 bx1
bx2 bx3
cy0
cy1
cy2
cy3
dz0
tRRD
tRRD
tRRD
tRRD
Read
AP*
Active
AP*
Read
Active
Active
Active
AP*
Bank #0
Bank #1
Bank #2
Bank #3
Read
Read
Active
Idle
* AP is the internal precharge start timing
- 22 -
W981216BH
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
0
CLK
CS
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
tRCD
tRCD
tRCD
RAa
RAa
RAc
RAc
A10
RBb
RBb
A0-A9,
A11
CAx
CBy
CAz
DQM
CKE
tAC
tAC
ax5 ax6
tAC
by7
ax0 ax1
ax2
ax3
ax4
by0
by1
by4 by5
by6
DQ
CZ0
tRRD
tRRD
Read
Active
Idle
Precharge
Active
Read
Precharge
Bank #0
Bank #1
Bank #2
Bank #3
Precharge
Active
Read
Publication Release Date: September 20, 2001
Revision A3
- 23 -
W981216BH
Operating Timing Example, continued
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Pre-charge)
(CLK = 100 MHz)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
0
CLK
CS
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRAS
tRP
WE
BS0
BS1
A10
tRCD
tRCD
tRCD
RBb
RAc
RAc
RAa
RAa
A0-A9,
A11
CAz
CAx
RBb
CBy
DQM
CKE
DQ
tCAC
tCAC
tCAC
ax3
ax4
ax0
ax2
ax5 ax6
ax7
by0
by1
by4
by5
by6
ax1
CZ0
tRRD
tRRD
AP*
Read
Active
Bank #0 Active
Bank #1
Read
Active
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
- 24 -
W981216BH
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8)
(CLK = 100 MHz)
10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
7
8
9
0
1
2
3
4
5
CLK
CS
tRC
RAS
CAS
tRAS
tRAS
tRP
tRAS
tRP
tRCD
tRCD
tRCD
WE
BS0
BS1
RBb
RAc
RAc
RAa
RAa
A10
A0-A9,
A11
CAx
RBb
CBy
CAz
DQM
CKE
DQ
ax0
ax1
ax4
ax5
ax6
ax7 by0
by1 by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
tRRD
tRRD
Active
Write
Precharge
Active
Write
Bank #0
Active
Write
Precharge
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date: September 20, 2001
Revision A3
- 25 -
W981216BH
Operating Timing Example, continued
Interleaved Bank Write (Burst Length = 8, Auto Pre-charge)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21 22 23
CLK
CS
tRC
RAS
CAS
tRP
tRAS
tRAS
tRAS
tRP
WE
BS0
BS1
tRCD
tRCD
tRCD
RAa
RAa
RBb
RBb
RAb
RAc
A10
A0-A9,
A11
CAx
CBy
CAz
DQM
CKE
DQ
ax4
by2
by5
ax0
ax1
ax5
ax6
ax7
by0 by1
by3
by4
by6
by7 CZ0
CZ1
CZ2
tRRD
tRRD
AP*
Write
AP*
Active
Active
Write
Bank #0
Active
Write
Bank #1
Bank #2
Bank #3
Idle
* AP is the internal precharge start timing
- 26 -
W981216BH
Operating Timing Example, continued
Page Mode Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15 16 17 18 19
20 21
22 23
CLK
CS
tCCD
t
CCD
t
CCD
t
RAS
tRP
t
RAS
t
RP
RAS
CAS
WE
BS0
BS1
t
RCD
tRCD
RAa
RAa
RBb
RBb
A10
A0-A9,
A11
CBx
CAy
CAm
CBz
CAI
DQM
CKE
tAC
tAC
t
AC
tAC
tAC
am1
am2 bz0
bz1
bz2
bz3
a0
a1
a3
bx0
Ay0
Ay1
Ay2
am0
a2
bx1
DQ
t
RRD
Read
Bank #0 Active
Bank #1
Read
Read
Precharge
Active
Read
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: September 20, 2001
Revision A3
- 27 -
W981216BH
Operating Timing Example, continued
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
5
CLK
CS
tRAS
tRP
RAS
CAS
WE
BS0
BS1
tRCD
RAa
RAa
A10
A0-A9,
A11
CAx
CAy
DQM
CKE
tAC
tWR
ax5
ay1
ax0
ax1
ax3
ay0
ay2
ay4
ax2
ax4
ay3
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
Write
Precharge
- 28 -
W981216BH
Operating Timing Example, continued
Auto Pre-charge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BS0
BS1
A10
tRCD
tRCD
RAa
RAb
A0-A9,
A11
CAx
RAa
CAw
RAb
DQM
CKE
DQ
tAC
tAC
aw0
aw1 aw2
aw3
bx0
bx1
bx2 bx3
Bank #0
AP*
Active
Idle
Read
Active
Read
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
Publication Release Date: September 20, 2001
Revision A3
- 29 -
W981216BH
Operating Timing Example, continued
Auto Pre-charge Write (Burst Length = 4)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRP
WE
BS0
BS1
t
RCD
tRCD
RAc
RAa
RAa
RAb
A10
A0-A9,
A11
CAw
RAb
CAx
RAc
DQM
CKE
DQ
bx0
aw1 aw2
bx1
bx3
bx2
aw0
aw3
Active
Idle
Bank #0
Write
Active
Write
AP*
Active
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
- 30 -
W981216BH
Operating Timing Example, continued
Auto Refresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
tRC
tRC
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
Publication Release Date: September 20, 2001
- 31 -
Revision A3
W981216BH
Operating Timing Example, continued
Self Refresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RP
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
tCKS
tCKS
tSB
CKE
DQ
t
CKS
t
RC
Self Refresh Cycle
No Operation Cycle
All Banks
Precharge
Self Refresh
Entry
Arbitrary Cycle
- 32 -
W981216BH
Operating Timing Example, continued
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
t
RCD
WE
BS0
BS1
A10
RBa
A0-A9,
A11
CBz
RBa
CBv
CBw
CBx CBy
DQM
CKE
t
AC
tAC
DQ
av0
av1
av3
aw0
ax0
ay0
az1
az2
az3
az0
av2
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Read
Active
Single Write
Read
Bank #0
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date: September 20, 2001
Revision A3
- 33 -
W981216BH
Operating Timing Example, continued
Power Down Mode
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
RAa
RAa
RAa
RAa
A10
A0-A9
A11
CAa
CAx
DQM
tSB
tSB
CKE
DQ
tCKS
tCKS
tCKS
tCKS
ax0
ax2
ax3
ax1
Active
NOP Read
Precharge
NOPActive
Precharge Standby
Power Down mode
Active Standby
Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
- 34 -
W981216BH
Operating Timing Example, continued
Auto Pre-charge Timing (Read Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Read AP
Read
Act
tRP
DQ
Q0
( b ) burst length = 2
Command
AP
Q0
Act
tRP
DQ
Q1
( c ) burst length = 4
Command
Read
AP
Q2
Act
Q4
tRP
DQ
Q0
Q0
Q1
Q1
Q3
( d ) burst length = 8
Command
Read
AP
Q6
Act
tRP
DQ
Q2
Act
Q3
Act
Q5
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read AP
Read
tRP
DQ
Q0
Q0
Q0
Q0
( b ) burst length = 2
Command
AP
tRP
DQ
Q1
AP
Q1
( c ) burst length = 4
Command
Read
Act
Q4
tRP
DQ
Q2
Q2
Q3
Q3
( d ) burst length = 8
Command
Read
AP
Q5
Act
tRP
DQ
Q1
Q6
Q7
Note )
Read
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
AP
Act
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least tRAS(min).
Publication Release Date: September 20, 2001
- 35 -
Revision A3
W981216BH
Operating Timing Example, continued
Auto Pre-charge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Write AP
Act
t
WR
t
RP
DQ
( b ) burst length = 2
Command
D0
Write
D0
AP
Act
AP
t
WR
tRP
DQ
( c ) burst length = 4
Command
D1
D1
D1
Write
D0
Act
D6
t
WR
t
RP
DQ
D2
D2
D3
D3
( d ) burst length = 8
Command
Write
D0
AP
Act
t
WR
tRP
DQ
D4
D5
D7
(2) CAS Latency=3
( a ) burst length = 1
Command
Write AP
Act
t
WR
tRP
DQ
D0
( b ) burst length = 2
Command
Write
D0
AP
Act
t
WR
tRP
DQ
( c ) burst length = 4
Command
D1
D1
D1
Write
D0
AP
D4
Act
D7
t
WR
tRP
DQ
D2
D2
D3
D3
( d ) burst length = 8
Command
Write
D0
AP
Act
t
WR
tRP
DQ
D5
D6
Note )
Write
represents the Write with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
AP
Act
When the Auto precharge command is asserted, the period from Bank Activate
command to the start of internal precgarging must be at least tRAS (min).
- 36 -
W981216BH
Operating Timing Example, continued
Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
( a ) Command
Read Write
DQM
DQ
D0
D1
D2
D1
D3
D2
( b ) Command
Read
Write
DQM
DQ
D0
D3
(2) CAS Latency=3
( a ) Command
DQM
Read Write
DQ
D0
D1
D2
D1
D3
D2
( b ) Command
Read
Write
DQM
DQ
D0
D3
Note: The Output data must be masked by DQM to avoid I/O conflict
Timing Chart of Write to Read Cycle
In the case of Burst Length=4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
Write Read
( a ) Command
DQM
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Read
Write
DQ
D0
D1
Q3
(2) CAS Latency=3
( a ) Command
DQM
Write Read
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Write
Read
DQ
Q3
D0
D1
Publication Release Date: September 20, 2001
Revision A3
- 37 -
W981216BH
Operating Timing Example, continued
Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
Command
Read
BST
Q3
DQ
Q0
Q1
Q0
Q2
Q1
Q4
Q3
( b )CAS latency = 3
Command
Read
BST
Q2
DQ
Q4
(2) Write cycle
Command
Write
Q0
BST
DQ
Q1
Q2
Q3
Q4
Note: BST
represents the Burst stop command
Timing Chart of Burst Stop Cycle (Pre-charge Command)
In the case of Burst Lenght = 8
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a )CAS latency =2
Command
Read
PRCG
DQ
Q0
Q1
Q0
Q2
Q1
Q3
Q4
Q3
( b )CAS latency = 3
Command
PRCG
Read
DQ
Q2
Q4
(2) Write cycle
PRCG
PRCG
( a ) CAS latency =2
Write
tWR
Command
DQM
DQ
D0
D1
D1
D2
D2
D3
D3
D4
D4
( b )CAS latency = 3
Write
Command
tWR
DQM
DQ
D0
- 38 -
W981216BH
Operating Timing Example, continued
CKE/DQM Input Timing (Write Cycle)
1
CLK cycle No.
2
3
4
5
7
6
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D5
D6
DQM MASK
CKE MASK
( 1 )
CLK cycle No.
External
2
3
4
5
7
1
6
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D5
D6
DQM MASK
( 2 )
CKE MASK
1
2
3
4
5
6
7
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
( 3 )
Publication Release Date: September 20, 2001
Revision A3
- 39 -
W981216BH
Operating Timing Example, continued
CKE/DQM Input Timing (Read Cycle)
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q1
Q2
Q3
Q4
Open
Open
( 1 )
1
2
3
4
5
7
CLK cycle No.
External
6
CLK
Internal
CKE
DQM
DQ
Q3
Q4
Q6
Q1
Q2
Open
( 2 )
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q3
Q1
Q5
Q4
Q2
( 3 )
- 40 -
W981216BH
Operating Timing Example, continued
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control
Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min)
A ) tCK < tCKS(min)+tCK(min)
tCK
CLK
CKE
tCKS(min)+tCK(min)
Command
Command
NOP
Input Buffer Enable
B) tCK >= tCKS(min) + tCK (min)
tCK
CLK
CKE
tCKS(min)+tCK(min)
Command
Command
Note )
Input Buffer Enable
All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode
and Self Refresh mode
NOP
Represents the No-Operation command
Command
Represents one command
Publication Release Date: September 20, 2001
Revision A3
- 41 -
W981216BH
12. PACKAGE DIMENSION
54L TSOP (II)-400 mil
54
28
HE
E
1
27
e
b
C
D
L
A2
A1
A
L1
ZD
Y
SEATING PLANE
Controlling Dimension: Millimeters
DIMENSION
(MM)
DIMENSION
(INCH)
SYM.
MIN.
MAX.
MIN.
NOM.
MAX.
NOM.
1.20
0.15
0.047
0.006
A
A1
0.10
0.05
0.24
0.002
0.009
0.004
0.039
1.00
0.32
0.15
A2
b
0.40
0.016
0.012
0.006
c
D
E
22.12
10.06
11.56
22.62
10.26
11.96
0.871
0.396
0.455
0.875
0.400
0.905
0.404
0.471
22.22
10.16
11.76
0.80
HE
e
0.463
0.0315
0.020
L
0.40
0.50
0.60
0.10
0.016
0.024
0.004
0.80
0.032
L1
Y
0.71
0.028
ZD
- 42 -
W981216BH
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
2727 N. First Street, San Jose,
FAX: 852-27552064
FAX: 886-3-5792766
CA 95134, U.S.A.
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Publication Release Date: September 20, 2001
Revision A3
- 43 -
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