WM2604IDT [WOLFSON]
Quad 10-Bit Serial Input Voltage Output DAC; 四通道10位串行输入电压输出DAC
| 型号： | WM2604IDT |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | Quad 10-Bit Serial Input Voltage Output DAC |
| 文件： | 总10页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM2604
Quad 10-Bit Serial Input Voltage Output DAC
Production Data, June 1999, Rev 1.0
FEATURES
DESCRIPTION
·
·
Four 10-bit voltage output DACs
Dual 2.7V to 5.5V supply (separate digital and analogue
supplies)
DNL ±0.1 LSB, INL ±0.4 LSB
Low power consumption:
The WM2604 is a quadruple 10-bit voltage output, resistor string,
digital-to-analogue converter. Each DAC can be individually
powered down under software control. A hardware controlled mode
is provided that powers down all DACs. Power down reduces
current consumption to 10nA.
·
·
-
-
5.5mW, slow mode - 5V supply
3.3mW, slow mode - 3V supply
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2604 is programmed with a 16-bit serial word
comprising of a DAC address, individual DAC control bits and a
10-bit value.
·
·
TMS320, (Q)SPIä , and Microwireä compatible serial
interface
Programmable settling time of 4ms or 12ms typical
APPLICATIONS
The WM2604 has provision for two supplies: one supply for the
serial interface (DVDD, DGND), and one for the DACs, reference
buffers and output buffers (AVDD, AGND). This enables a typical
·
·
·
·
·
·
·
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
application where the device can be controlled via
a
microprocessor operating on a 3V supply, with the DACs operating
on a 5V supply. Alternatively, the supplies can be tied together in a
single supply application.
Arbitrary waveform generation
Excellent performance is delivered with a typical DNL of ±0.1 LSB.
The settling time of the DAC is programmable to allow the designer
to optimize speed versus power dissipation. The output stage is
buffered by a x2 gain near rail-to-rail amplifier, which features a
Class AB output stage. DACs A and B can have a different
reference voltage to DACs C and D.
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
The device is available in a 16-pin TSSOP package. Commercial
temperature (0° to 70°C) and Industrial temperature (-40° to 85°C)
variants are supported.
WM2604CDT
WM2604IDT
0° to 70°C
16-pin TSSOP
16-pin TSSOP
-40° to 85°C
BLOCK DIAGRAM
TYPICAL PERFORMANCE
AVDD
(16)
DVDD
(1)
1
REFINAB (15)
REFINCD (10)
AVDD = DVDD =5V, VREF
=
2.048V, Speed = Fast mode, Load = 10k/100pF
REFERENCE
INPUT BUFFER
0.8
0.6
0.4
0.2
0
DAC A
X1
DAC
OUTPUT
BUFFER
WM2604
10-BIT
DAC
LATCH
DIN (4)
(14) OUTA
X2
data
16-BIT
12-BIT
FS (7)
SHIFT
REGISTER
AND
DATA AND
CONTROL
HOLDING
LATCH
CONTROL
LOGIC
SCLK (5)
NCS (6)
POWERDOWN/
SPEED
CONTROL
-0.2
-0.4
-0.6
-0.8
-1
2-BIT
CONTROL
LATCH
(13) OUTB
(12) OUTC
(11) OUTD
DAC B
DAC C
0
256
512
767
1023
POWER-ON
RESET
CODE
DAC D
(9)
AGND
(8)
DGND
(3)
NLDAC
(2)
NPD
WOLFSON MICROELECTRONICS LTD
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and Conditions.
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Ó1999 Wolfson Microelectronics Ltd.
WM2604
Production Data
PIN CONFIGURATION
DVDD
NPD
1
2
3
4
5
6
7
16
15
14
13
12
11
10
AVDD
REFINAB
OUTA
NLDAC
DIN
OUTB
SCLK
NCS
OUTC
OUTD
FS
REFINCD
DGND
8
9
AGND
PIN DESCRIPTION
PIN NO
NAME
DVDD
NPD
TYPE
DESCRIPTION
Digital supply.
Supply
1
2
Digital input
Power down. Powers down all DACs overriding their individual power down
settings and all output stages. This pin is active low.
NLDAC
Digital input
Load DAC. Digital input active low. NLDAC must be taken low to update
the DAC latch from the holding latches.
3
DIN
SCLK
Digital input
Digital input
Digital input
Digital input
Ground
Serial data input.
4
5
Serial clock input.
NCS
Chip select. This pin is active low.
Frame synchronisation for serial input data.
Digital ground.
6
FS
7
DGND
AGND
REFINCD
OUTD
OUTC
OUTB
OUTA
REFINAB
AVDD
8
Ground
Analogue ground.
9
Analogue input
Analogue output
Analogue output
Analogue output
Analogue output
Analogue input
Supply
Voltage reference input for DACs C and D.
DAC D output.
10
11
12
13
14
15
16
DAC C output.
DAC B output.
DAC A output.
Voltage reference input for DACs A and B.
Analogue supply.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 1999
2
WM2604
Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
CONDITION
MIN
MAX
7V
Supply voltages, AVDD to AGND, DVDD to DGND
Supply voltage differences, AVDD to DVDD
Digital input voltage
-2.8V
-0.3V
-0.3V
2.8V
DVDD + 0.3V
AVDD + 0.3V
Reference input voltage
Operating temperature range, TA
WM2604C
WM2604I
0°C
70°C
85°C
-40°C
-65°C
Storage temperature
150°C
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
260°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
2.7
2
TYP
MAX
UNIT
Supply voltage
AVDD, DVDD
5.5
V
V
V
V
High-level digital input voltage
Low-level digital input voltage
VIH
VIL
DVDD = 2.7V to 5.5V
DVDD = 2.7V to 5.5V
See Note
0.8
Reference voltage to REFINAB,
REFINCD
VREF
AVDD - 1.5
Load resistance
RL
CL
2
10
kW
Load capacitance
100
20
pF
Serial clock rate
fSCLK
TA
MHz
Operating free-air temperature
WM2604CDT
WM2604IDT
0
70
85
°C
°C
-40
Note: Reference voltages greater than AVDD/2 will cause output saturation for large DAC codes.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 99
3
WM2604
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions:
RL = 10kW, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static DAC Specifications
Resolution
10
bits
LSB
Integral non-linearity
INL
DNL
See Note 1
See Note 2
See Note 3
See Note 4
See Note 5
See Note 6
See Note 6
±0.4
±0.1
3
±1
±0.25
±12
Differential non-linearity
Zero code error
LSB
ZCE
mV
Gain error
GE
0.25
0.5
10
% FSR
mV/V
ppm/°C
ppm/°C
±0.6
d.c. power supply rejection ratio
Zero code error temperature coefficient
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
DC PSRR
10
0
AVDD - 0.1
0.25
V
Output load regulation
2kW to 10kW load
0.1
%
See Note 7
Power Supplies
Active supply current
IDD
No load, VIH = DVDD, VIL = 0V
mA
AVDD = 5V,
VREF = 2.048V Slow
1.4
3.5
1.0
3.0
2.2
5.5
1.5
4.5
AVDD = 5V,
VREF = 2.048V Fast
AVDD = 3V,
VREF = 1.024V Slow
AVDD = 3V,
VREF = 1.024V Fast
See Note 8
Power down supply current
No load, all digital inputs
0V or DVDD
0.01
10
mA
See Note 9
Dynamic DAC Specifications
Slew rate
DAC code 32 to 1023,
10% to 90%
Slow
Fast
0.5
2.5
1.0
4.0
V/ms
V/ms
See Note 10
DAC code 32 to 1023
Slow
Settling time
12.0
4.0
ms
ms
Fast
See Note 11
Code 511 to 512
Glitch energy
10
68
nV-s
dB
Signal to noise ratio
SNR
SNRD
THD
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
60
54
See Note 12
Signal to noise and distortion ratio
Total harmonic distortion
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
65
-68
70
dB
dB
dB
See Note 12
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
-54
See Note 12
Spurious free dynamic range
SPFDR
fs = 400ksps, fOUT = 1kHz,
BW = 20kHz
54
See Note 12
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 1999
4
WM2604
Production Data
Test Conditions:
RL = 10kW, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference
Reference input resistance
Reference input capacitance
Reference feedthrough
RREFIN
CREFIN
10
5
MW
pF
VREF = 1VPP at 1kHz
-75
dB
+ 1.024V dc, DAC code 0
Reference input bandwidth
VREF = 0.2VPP + 1.024V dc
DAC code 512
Slow
0.5
1
MHz
MHz
Fast
Digital Inputs
High level input current
Low level input current
Input capacitance
IIH
IIL
CI
Input voltage = DVDD
Input voltage = 0V
1
mA
mA
pF
-1
3
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of
zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A
guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on
the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kW load and 2kW load. It is expressed as a
percentage of the full scale output voltage with a 10kW load.
8. IDD is measured while continuously writing code 512 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase.
9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates.
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits
are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 99
5
WM2604
Production Data
SERIAL INTERFACE
tWL
tWH
3
tSUC16CS
1
2
4
5
15
16
SCLK
tSUD
tHD
D15
tSUCSFS
D14
D13
D12
D1
D0
DIN
NCS
FS
tWHFS
tSUFSCLK
tSUC16FS
Figure 1 Timing Diagram
Test Conditions:
RL = 10kW, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise)
SYMBOL
tSUCSFS
TEST CONDITIONS
MIN
10
8
TYP
MAX
UNIT
ns
Setup time NCS low before negative FS edge.
Setup time FS low before first negative SCLK edge.
tSUFSCLK
ns
Setup time, sixteenth negative SCLK edge after FS low
on which D0 is sampled before rising edge of FS.
tSUC16FS
10
10
ns
ns
Setup time, sixteenth positive SCLK edge (first positive
after D0 sampled) before NCS rising edge.
If FS is used instead of the sixteenth positive edge to
update the DAC, then the setup time is between the FS
rising edge and the NCS rising edge.
tSUC16CS
Pulse duration, SCLK high.
tWHCLK
tWLCLK
tSUDCLK
tHDCLK
tWHFS
25
25
8
ns
ns
ns
ns
ns
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
Pulse duration, FS high.
5
20
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 1999
6
WM2604
Production Data
TYPICAL PERFORMANCE GRAPHS
1
AVDD = DVDD =5V, VREF =2.048V, Speed = Fast mode, Load = 10k/100pF
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
256
512
767
1023
DIGITAL CODE
Figure 2 Integral Non-Linearity
0.4
0.4
0.35
0.3
AVDD = DVDD = 3V, VREF = 1V, Input Code = 0
AVDD = DVDD = 5V, VREF = 2V, Input Code = 0
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
0
1
2
3
4
5
6
7
8
9
10
ISINK - mA
0
1
2
3
4
5
6
7
8
9
10
Slow
Fast
ISINK - mA
Slow
Fast
Figure 3 Sink Current AVDD = DVDD = 3V
Figure 4 Sink Current AVDD = DVDD = 5V
4.092
2.054
AVDD = DVDD = 3V, VREF = 1V, Input Code = 1023
2.052
AVDD = DVDD = 5V, VREF = 2V, Input Code = 1023
4.09
4.088
4.086
4.084
4.082
4.08
2.05
2.048
2.046
2.044
2.042
2.04
4.078
4.076
4.074
4.072
4.07
2.038
2.036
2.034
2.032
0
1
2
3
4
5
6
7
8
9
10
Fast
ISOURCE - mA
Slow
0
1
2
3
4
5
6
7
8
9
10
ISOURCE - mA
Slow
Fast
Figure 5 Source Current AVDD = DVDD = 3V
WOLFSON MICROELECTRONICS LTD
Figure 6 Sink Current AVDD = DVDD = 5V
PD Rev 1.0 June 99
7
WM2604
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to analogue
voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and
the input code according to the following relationship:
CODE
Output voltage =
1111
(
REF
)
2 V
1024
INPUT
OUTPUT
1023
1024
11
1111
2
2
(
V
REF
)
)
:
:
513
10
10
01
0000
0001
0000
1111
(V
REF
1024
512
0000
1111
(
REF
)
=
REF
2 V
V
1024
511
2
(V
REF
)
)
1024
:
:
1
00
00
0000
0001
0000
2
(V
REF
1024
0000
0V
Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kW load
with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code.
REFINAB and REFINCD pins have an input resistance of 10MW and an input capacitance of typically
5pF. The reference voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
The device has two configuration options that are controlled by device pins.
DEVICE POWER DOWN
The device can be powered-down by pulling pin NPD (Pin 2) high. This powers down all DACs overriding
their individual power down settings. This will reduce power consumption to typically 10nA. When the
power down function is released the device reverts to the DAC code set prior to power down.
SIMULTANEOUS DAC UPDATE
The NLDAC pin (Pin 3) can be held high to prevent serial word writes from updating the DAC latches. By
writing new values to multiple DACs then pulling NLDAC low, all new DAC codes are loaded into the DAC
latches simultaneously.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 1999
8
WM2604
Production Data
SERIAL INTERFACE
Explanation of data transfer:
First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the data
bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have
been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be moved
to the DAC holding latch. If NLDAC is low, the DAC latch will also be updated immediately.
The serial interface of the device can be used in two basic modes:
·
·
four wire (with chip select)
three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port
of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial
bus, then NCS can be tied low.
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
fSCLKmax =
= 20MHz
tWCH min+ tWCL min
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling
time to 10 bits limits the update rate for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the
10-bit data word. D15-D12 hold the programmable options.
D15 D14 D13 D12 D11 D10 D9
A1 A0 PWR SPD
D8
D7
D6
D5
D4
D3
D2
D1
X
D0
X
New DAC value (10 bits)
Table 2 Register Map
DAC ADDRESSING
A particular DAC (A, B, C, D) within the device is selected by A1 and A0 within the input word.
A1
0
A0
0
DAC ADDRESS
DAC A
0
1
DAC B
1
0
DAC C
1
1
DAC D
PROGRAMMABLE SETTLING TIME (SPD – BIT D12)
Settling time is a software selectable 12ms or 4ms, typical to within ±0.5LSB of final value. This is
controlled by the value of SPD – Bit D12 and an associated DAC address. A ONE defines a settling time
of 4ms, a ZERO defines a settling time of 12ms for that DAC.
PROGRAMMABLE POWER DOWN
The power down function is controlled by PWR - Bit D13 and an associated DAC address. A ZERO
configures that DAC as active, a ONE configures that DAC into power down mode.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 99
9
WM2604
Production Data
PACKAGE DIMENSIONS
DT: 16 PIN TSSOP (5.0 x 4.4 x 1.0 mm)
DM013.A
b
e
16
9
E1
E
GAUGE
PLANE
q
1
8
D
0.25
c
L
A1
A
A2
-C-
C
0.05
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
MAX
1.20
0.15
1.05
0.30
0.20
5.10
A
A1
A2
b
c
D
e
E
E1
L
-----
0.05
0.80
0.19
0.09
4.90
-----
1.00
-----
-----
5.00
0.65 BSC
6.4 BSC
4.40
4.30
0.45
0o
4.50
0.75
8o
0.60
-----
q
REF:
JEDEC.95, MO-153
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 June 1999
10
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