WM2610CDT [WOLFSON]
Octal 12-bit, Serial Input, Voltage Output DAC with Power Down; 八通道12位，串行输入，电压输出DAC，具有掉电
| 型号： | WM2610CDT |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | Octal 12-bit, Serial Input, Voltage Output DAC with Power Down |
| 文件： | 总13页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM2610
Octal 12-bit, Serial Input, Voltage Output DAC
with Power Down
Production Data, February 2001, Rev 1.0
FEATURES
DESCRIPTION
•
•
•
•
Eight 12-bit DACs in one package
Dual supply 2.7V to 5.5V operation
DNL ±0.5 LSBs, INL ±2.0 LSBs typical
Programmable settling time / power
(1.0µs typ. in fast mode)
Microcontroller compatible Serial Interface
Power Down Mode ( < 0.1µA)
Monotonic over Temperature
The WM2610 is an octal, 12-bit, resistor string digital-to-
analogue converter. The eight individual DACs contained in the
IC can be switched in pairs between fast and slow (low power)
operation modes, or powered down, under software control.
Alternatively, the whole device can be powered down, reducing
•
•
•
•
current consumption to less than 0.1µA.
The DAC outputs are buffered by a rail-to-rail amplifier with a
gain of two, which is configurable as Class A (fast mode) or
Class AB (for low-power mode).
Data Output for Daisy Chaining
The WM2610 has been designed to interface directly to industry
standard microprocessors and DSPs, and can operate on two
separate analogue and digital power supplies. It is programmed
with a 16-bit serial word comprising 4 address bits and up to 12
DAC or control register data bits. All eight DACs can be
simultaneously forced to a preset value using a preset input pin.
APPLICATIONS
•
•
•
•
•
•
•
•
Battery powered test instruments
Digital offset and gain adjustment
Battery operated / remote industrial controls
Programmable Loop Controllers
CNC Machine Tools
Machine and motion control devices
Wireless telephone and communication systems
Robotics
A daisy-chain data output makes it possible to control several of
Wolfson’s octal DACs from the same interface, without
increasing the number of control lines.
The device is available in
a 20-pin TSSOP package.
Commercial temperature (0° to 70°C) and Industrial
temperature (-40° to 85°C) variants are supported.
ORDERING INFORMATION
DEVICE
TEMP. RANGE
0° to 70°C
PACKAGE
20-pin TSSOP
20-pin TSSOP
WM2610CDT
WM2610IDT
-40° to 85°C
BLOCK DIAGRAM
TYPICAL PERFORMANCE
REF
(16)
AVDD
(11)
DVDD
(20)
1
0.75
0.5
DAC A
DIN (2)
SCLK (3)
FS (4)
RESISTOR
STRING
0.25
0
(12) OUT A
SERIAL
INTERFACE
AND
CONTROL
LOGIC
LATCH
MODE (17)
PREB (5)
DOUT (19)
POWER/SPEED
CONTROL
-0.25
-0.5
-0.75
-1
VREF/2
DACs B, C, D, E, F, G, H
as DAC A
(6-9, 13-15)
OUT B to H
0
512
1024
1536
2048
2560
3072
3584
4096
LOADB
(18)
AGND
(10)
DGND
(1)
DIGITAL CODE
WOLFSON MICROELECTRONICS LTD
Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Production Data datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and Conditions.
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
www.wolfsonmicro.co.uk
2001 Wolfson Microelectronics Ltd.
WM2610
Production Data
PIN CONFIGURATION
DGND
DIN
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
DVDD
DOUT
LOADB
MODE
REF
SCLK
FS
PREB
OUTE
OUTF
OUTG
OUTD
OUTC
OUTB
OUTH
AGND
9
12
11
OUTA
AVDD
10
PIN DESCRIPTION
PIN NO
1
NAME
DGND
DIN
TYPE
DESCRIPTION
Supply
Digital Ground
2
Digital input
Digital input
Digital input
Digital input
Digital serial data input
Serial clock input
Frame sync input
Preset input
3
SCLK
FS
4
5
PREB
OUTE
OUTF
OUTG
OUTH
AGND
AVDD
OUTA
OUTB
OUTC
OUTD
REF
6
Analogue output DAC Output E
Analogue output DAC Output F
Analogue output DAC Output G
Analogue output DAC Output H
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Supply
Supply
Analogue Ground
Analogue positive power supply
Analogue output DAC Output A
Analogue output DAC Output B
Analogue output DAC Output C
Analogue output DAC Output D
Analogue I/O
Digital input
Digital input
Digital output
Supply
Voltage reference input / output
MODE
LOADB
DOUT
DVDD
Input mode
Load DAC
Data serial data output
Digital positive power supply
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
2
Production Data
WM2610
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of
this device.
CONDITION
MIN
MAX
7V
Digital supply voltages, AVDD or DVDD to GND
Reference voltage
-0.3V
-0.3V
AVDD + 0.3V
DVDD + 0.3V
Digital input voltage range to GND
Operating temperature range, TA
WM2610CDT
WM2610IDT
0°C
70°C
85°C
-40°C
-65°C
Storage temperature
150°C
Soldering temperature, 1.6mm (1/16 inch) from package body for 10
seconds
260°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage
AVDD,
DVDD
VIH
2.7
2
5.5
V
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REF
V
V
VIL
0.8
VREF
AVDD = 5V
AVDD = 3V
GND
GND
2
4.096
2.048
AVDD
AVDD
V
Output Load Resistance
Load capacitance
RL
CL
TA
kΩ
pF
°C
°C
100
70
Operating free-air temperature
WM2610CDT
0
WM2610IDT
-40
85
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
3
WM2610
Production Data
ELECTRICAL CHARACTERISTICS
Test Characteristics:
Over recommended operating conditions (unless noted otherwise).
TEST
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
Static DAC Specifications
Resolution
12
±2
bits
LSB
Integral non-linearity
Differential non-linearity
Zero code error
INL
DNL
ZCE
GE
Code 40 to 4095 (see Note 1)
Code 40 to 4095 (see Note 2)
See Note 3
±6
±1
±0.5
LSB
±30
±0.6
mV
Gain error
See Note 4
% FSR
dB
DC power supply rejection ratio
PSRR
See Note 5
-60
30
Zero code error temperature
coefficient
See Note 6
µV/°C
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
See Note 6
10
ppm/°C
10kΩ Load
0
AVDD-0.4
±0.3
V
Output load regulation
2kΩ to 10kΩ load
% Full
Scale
See Note 7
Power Supplies
Active supply current
IDD
No load, VIH=DVDD, VIL=0V
AVDD = DVDD = 5V,
V
REF = 2.048V
Slow
6
8
mA
mA
Fast
16
21
See Note 8
Power down supply current
No load, all inputs 0V
or DVDD
0.1
µA
Dynamic DAC Specifications
Slew rate
DAC code 10%-90%
Load = 10kΩ, 100pF
Fast
4
1
10
3
V/µs
V/µs
Slow
See Note 9
Settling time
DAC code 10%-90%
Load = 10kΩ, 100pF
Fast
1
3
3
7
µs
µs
Slow
See Note 10
Code 2047 to code 2048
Glitch energy
4
nV-s
dB
Channel Crosstalk
10kHz sine wave, 4V pk-pk
-90
Reference Input
Reference input resistance
Reference input capacitance
Reference feedthrough
RREF
CREF
100
5
kΩ
pF
dB
V
REF=2VPP at 1kHz
-84
+ 2.048V DC, DAC code 0
Reference input bandwidth
V
REF= 0.4VPP + 2.048V DC,
DAC code 2048
Slow
1.9
2.2
MHz
MHz
Fast
Digital Inputs
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
4
Production Data
WM2610
Test Characteristics:
Over recommended operating conditions (unless noted otherwise).
TEST
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
High level input current
Low level input current
Input capacitance
IIH
IIL
CI
Input voltage = DVDD
1
µA
µA
pF
Input voltage = 0V
-1
8
Digital Output
High level digital output voltage
Low level digital output voltage
Output voltage rise time
VOH
VOL
Load = 10kΩ
Load = 10kΩ
2.6
V
V
0.4
20
Load = 10kΩ, 20pF, includes
7
ns
propagation delay
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding
the effects of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same
direction (or remains constant) as a change in digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ
load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.
8.
I
DD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V
supply current will increase.
9. Slew rate results are for the lower value of the rising and falling edge slew rates.
10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
5
WM2610
Production Data
SERIAL INTERFACE
tWL tWH
3
SCLK
X
tSUD
X
1
2
4
16
X
tHD
DIN
D15
D15 *
D14
D14 *
D13
D1
D0
D0 *
X
X
2
DOUT
X
D13 *
D12 *
D1 *
tWHFS tSUFSCLK
tSUC16-FS
* DIN data from previous word
(delayed by 16 clock cycles)
FS
(
µ
C MODE)
tWLFS
FS
No high to low transitions
(DSP MODE)
Figure 1 Timing Diagram
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
tSUFSCLK
tC16-FS
Setup time, FS pin low before first falling edge of SCLK
8
ns
ns
Setup time, 16th falling clock edge after FS low to rising edge of FS
(only used in microcontroller mode)
10
tWLOADB
tWH
Pulse duration, LOADB low
10
16
16
8
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SCLK high
tWL
Pulse duration, SCLK low
tSUD
tHD
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
5
tWHFS
tWLFS
ts
10
10
Pulse duration, FS low
DAC Output settling time
see Dynamic DAC Specifications
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
6
Production Data
WM2610
TYPICAL PERFORMANCE GRAPHS
4
3
2
1
0
-1
-2
-3
-4
0
512
1024
1536
2048
2560
3072
3584
4096
DIGITAL CODE
Figure 2 Integral Non-Linearity
1
0.8
0.6
0.4
0.2
0
1
VDD = 3V
VREF = 1.024V
VDD = 5V
Slow
Fast
Slow
Fast
VREF = 2.048V
Input Code = 0
0.8
Input Code = 0
0.6
0.4
0.2
0
0
0.5
1
1.5
2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Sink Current (mA)
Sink Current (mA)
Figure 3 Output Load Regulation (Sink) AVDD = 3V
Figure 4 Output Load Regulation (Sink) AVDD = 5V
2.1
4.15
VDD=3V
VREF=1.024V
VDD=5V
VREF=2.048V
Slow
Slow
Fast
Input Code = 4095
Fast
Input Code = 4095
2.08
2.06
2.04
2.02
2
4.13
4.11
4.09
4.07
4.05
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
Sourcing Current (mA)
Sourcing Current (mA)
Figure 5 Output Load Regulation (Source) AVDD = 3V
WOLFSON MICROELECTRONICS LTD
Figure 6 Output Load Regulation (Source) AVDD = 5V
PD Rev 1.0 February 2001
7
WM2610
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The WM2610 is an octal 12-bit, voltage output DAC. It contains a serial interface, control logic for
speed and power down, a programmable voltage reference, and eight digital to analogue converters.
Each converter uses a resistor string network buffered with an op amp to convert 12-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
CODE
Output voltage = V
×
REF
4096
INPUT
OUTPUT
4095
1111
1111
1111
V
V
×
REF
4096
:
:
1000
1000
0000
0001
2049
4096
×
REF
0000
1111
0000
1111
V
2048
4096
REF
V
×
=
REF
2
0111
2047
4096
V
×
REF
:
:
0000
0000
0000
0001
0000
V
REF
4096
0V
0000
Table 1 Binary Code Table
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2kΩ load with a 100pF load capacitance.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
8
Production Data
WM2610
SERIAL INTERFACE
INTERFACE MODES
The control interface can operate in two different modes:
•
•
In the microcontroller mode, FS needs to be held low until all 16 data bits have been
transferred. If FS is driven high before the 16th falling clock edge, the data transfer is cancelled.
The DAC is updated after a rising edge on FS.
In DSP mode, FS only needs to stay low for 20ns, and can go high before the 16th falling clock
edge.
SCLK
FS
DIN
X
D15 D14
D1
D0
X
E15 E14
E1
E0
X
X
F15 F14
Figure 7 Interface Timing in Microcontroller Mode
SCLK
FS
DIN
X
D15 D14
D1
D0 E15 E14
E1
E0
X
X
X
F15 F14
Figure 8 Interface Timing in DSP Mode
The operating mode is selected using pin 17 (MODE).
MODE PIN (17)
HIGH
INTERFACE MODE
Microcontroller
DSP mode
LOW or unconnected
Table 2 Interface Mode Selection
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the interface timing. The maximum serial clock rate is:
1
fSCLK max
=
= 31MHz
tWH min + tWLmin
Since a data word contains 16 bits, the sample rate is limited to
1
fs max
=
=1.95MHz
16(
tWH min + tWL min
)
However, the DAC settling time to 12 bits accuracy limits the response time of the analogue output
for large input step transitions.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
9
WM2610
Production Data
DAISY CHAINING MULTIPLE DEVICES
The DOUT output (pin 19) provides the data sampled on DIN with a delay of 16 clock cycles. This
signal can be used to control another WM2610 or similar device in a daisy-chain type circuit.
OCTAL DAC #1
OCTAL DAC #2
OCTAL DAC #3
Figure 9 Daisy Chaining
SOFTWARE CONFIGURATION OPTIONS
DATA FORMAT
The WM2610 is controlled with a 16-bit code consisting of four address bits, A0-A3, and 12 data bits.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A3
A2
A1
A0
Data
Table 3 Input Data Format
Using the four address bits, 16 different registers can be addressed.
A3
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
REGISTER
DAC A Code
0
0
DAC B Code
0
DAC C Code
0
DAC D Code
0
DAC E Code
0
DAC F Code
0
DAC G Code
0
DAC H Code
1
Control Register 0
Control Register 1
Preset all DACs
RESERVED
1
1
1
1
DAC A and complement B
DAC C and complement D
DAC E and complement F
DAC G and complement H
1
1
1
Table 4 Register Map
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
10
Production Data
WM2610
DAC A TO H CODE REGISTERS
Addresses 0 to 7 are the DAC registers. The data written to these registers is transferred to the
respective DAC when the LOADB input (pin 18) is low. For instantaneous updating, LOADB can be
held low permanently.
CONTROL REGISTER 0
Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power
Down and Data Input Format.
BIT
D11
X
D10
X
D9 D8 D7 D6 D5
D4
PD
0
D3
DO
0
D2
X
D1
X
D0
IM
0
Function
Default
X
X
X
X
X
X
X
X
X
X
X
X
0
0
Table 5 Register Map
BIT
DESCRIPTION
0
1
PD
Full device Power Down
DOUT Enable
Input Mode
Normal
Disabled
Power Down
Enabled
DO
IM
Straight Binary
Two’s Complement
X
Reserved
Table 6 Register Map
CONTROL REGISTER 1
Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling
time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of
the device. The settling time in fast mode is typically 1µs. In slow mode, the settling time is typically
3µs and power consumption is reduced.
BIT
D11
X
D10
X
D9 D8 D7 D6 D5
D4
D3
SGH
0
D2
SEF
0
D1
SCD
0
D0
SAB
0
Function
Default
X
X
X
X
PGH PEF PCD PAB
X
X
0
0
0
0
Table 7 Register Map
BIT
DESCRIPTION
Power Down DACs X and Y
Speed Setting for DACs X and Y
0
1
PXY
Normal
Slow
Power Down
Fast
SXY
Table 8 Register Map
DAC PRESET REGISTER
The Preset register (address 10) makes it possible to update all eight DACs at the same time. The
value stored in this register becomes the digital input to all the DACs when the asynchronous PREB
input (pin 5) is driven low. If no data has previously been written to the preset register, all DACs are
set to zero scale.
TWO-CHANNEL REGISTERS
The two-channel registers (addresses 12 to 15) provide a ‘differential output’ function where writing
data to one DAC will automatically write the complement to the other DAC in the pair. For example,
writing a hexadecimal value of FFFF to address 12 will set DAC A to full scale and DAC B to zero
scale.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
11
WM2610
Production Data
APPLICATIONS INFORMATION
LINEARITY, OFFSET, AND GAIN ERROR
Amplifiers operating from a single supply can have positive or negative voltage offsets. With a
positive offset, the output voltage changes on the first code transition. However, if the offset is
negative, the output voltage may not change with the first code, depending on the magnitude of the
offset voltage. This is because with the most negative supply rail being ground, any attempt to drive
the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at
zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the
transfer function shown in Figure 10.
Output
Voltage
0 V
Negative
DAC code
Offset
Figure 10 Effect of Negative Offset
This offset error, not the linearity error, produces the breakpoint. The transfer function would follow
the dotted line if the output buffer could drive below the ground rail.
DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs
at 1), disregarding offset and full-scale errors. However, due to the breakpoint in the transfer function,
single supply operation does not allow for adjustment when the offset is negative. In such cases, the
linearity is therefore measured between full-scale and the lowest code that produces a positive (non-
zero) output voltage.
POWER SUPPLY DECOUPLING AND GROUNDING
Printed circuit boards with separate analogue and digital ground planes deliver the best system
performance. The two ground planes should be connected together at the low impedance power
supply source. Ground currents should be managed so as to minimise voltage drops across the
ground planes.
A 0.1µF decoupling capacitor should be connected between the positive supply and ground pins of
the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate
the system analogue supply from the digital supply.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
12
Production Data
WM2610
PACKAGE DIMENSIONS
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm)
DM008.D
b
e
20
11
E1
E
GAUGE
PLANE
θ
1
10
D
0.25
c
L
A1
A
A2
-C-
0.1
C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
1.20
0.15
1.05
0.30
0.20
6.60
A
A1
A2
b
c
D
e
E
E1
L
0.05
0.80
0.19
0.09
6.40
-----
1.00
-----
-----
6.50
0.65 BSC
6.4 BSC
4.40
4.30
0.45
0o
4.50
0.75
8o
0.60
-----
θ
REF:
JEDEC.95, MO-153
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM.
D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 February 2001
13
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