WM8731SED_13 [WOLFSON]
Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates; 便携式因特网音频编解码器与耳机驱动器和可编程的采样率
| 型号： | WM8731SED_13 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates |
| 文件： | 总65页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8731 / WM8731L
w
Portable Internet Audio CODEC with Headphone Driver
and Programmable Sample Rates
DESCRIPTION
FEATURES
Highly Efficient Headphone Driver
Audio Performance
The WM8731 or WM8731L (WM8731/L) are low power
stereo CODECs with an integrated headphone driver. The
WM8731/L is designed specifically for portable MP3 audio
and speech players and recorders. The WM8731 is also
ideal for MD, CD-RW machines and DAT recorders.
-
-
ADC SNR 90dB (‘A’ weighted) at 3.3V, 85dB at 1.8V
DAC SNR 100dB (‘A’ weighted) at 3.3V, 95dB at 1.8V
Low Power
-
-
-
-
-
Playback only 22mW, 8mW (‘L’ Variant)
Stereo line and mono microphone level audio inputs are
provided, along with a mute function, programmable line
level volume control and a bias voltage output suitable for
an electret type microphone.
Analogue Pass Through 12mW, 3.5mW (‘L’ variant)
1.42 – 3.6V Digital Supply Operation
2.7 – 3.6V Analogue Supply Operation
1.8 – 3.6V Analogue Supply Operation (‘L’ Variant)
Stereo 24-bit multi-bit sigma delta ADCs and DACs are used
with oversampling digital interpolation and decimation filters.
Digital audio input word lengths from 16-32 bits and
sampling rates from 8kHz to 96kHz are supported.
ADC and DAC Sampling Frequency: 8kHz – 96kHz
Selectable ADC High Pass Filter
2 or 3-Wire MPU Serial Control Interface
Programmable Audio Data Interface Modes
Stereo audio outputs are buffered for driving headphones
from a programmable volume control, line level outputs are
also provided along with anti-thump mute and power
up/down circuitry.
-
-
-
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
Master or Slave Clocking Mode
Microphone Input and Electret Bias with Side Tone Mixer
Available in 28-lead SSOP or 28-lead QFN package
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including
volume controls, mutes, de-emphasis and extensive power
management facilities. The device is available in a small 28-
lead SSOP package or the smaller 28 lead quad flat
leadless package (QFN).
APPLICATIONS
Portable MP3 Players and Recorders
CD and Minidisc Recorders
PDAs / smartphones
BLOCK DIAGRAM
AVDD
W
CONTROL INTERFACE
WM8731
VMID
HPVDD
HPGND
Bypass
MUTE
AGND
ATTEN
MUTE
/
+ 6 to -73 dB
dB Steps
1
Side Tone
H /P
DRIVER
MICBIAS
RLINEIN
VOL
/
RHPOUT
MUTE
VOL
MUTE
MUTE
MUTE
MUX
ADC
ADC
DAC
DAC
+ 12 to -34 .5 dB , 1.5 dB
Steps
ROUT
LOUT
0 dB /
20 dB
DIGITAL
FILTERS
MICIN
MUTE
MUTE
MUX
MUTE
VOL
LLINEIN
VOL
/
H/P
DRIVER
LHPOUT
MUTE
+ 12 to -34 .5 dB , 1.5 dB
Steps
Side Tone
+ 6 to -73 dB
dB Steps
ATTEN
MUTE
/
1
MUTE
CLKOUT
DIVIDER
CLKIN
DIVIDER
Bypass
DIGTAL AUDIO INTERFACE
OSC
( Div x 1 , x2)
( Div x 1 , x2)
Production Data, October 2012, Rev 4.9
WOLFSON MICROELECTRONICS plc
Copyright 2012 Wolfson Microelectronics plc
WM8731 / WM8731L
Production Data
TABLE OF CONTENTS
DESCRIPTION....................................................................................................... 1
FEATURES............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
BLOCK DIAGRAM ................................................................................................ 1
PIN CONFIGURATION - 28 PIN SSOP................................................................ 3
ORDERING INFORMATION.................................................................................. 3
PIN CONFIGURATION – 28 PIN QFN................................................................... 4
ORDERING INFORMATION.................................................................................. 4
PIN DESCRIPTION................................................................................................ 5
ABSOLUTE MAXIMUM RATINGS........................................................................ 6
RECOMMENDED OPERATING CONDITIONS – WM8731 .................................. 6
RECOMMENDED OPERATING CONDITIONS – WM8731L ................................ 6
ELECTRICAL CHARACTERISTICS – WM8731 ................................................... 7
TERMINOLOGY .............................................................................................................. 9
POWER CONSUMPTION – WM8731.................................................................. 10
ELECTRICAL CHARACTERISTICS – WM8731L............................................... 11
TERMINOLOGY ............................................................................................................ 13
POWER CONSUMPTION – WM8731L ............................................................... 14
MASTER CLOCK TIMING................................................................................... 15
DIGITAL AUDIO INTERFACE – MASTER MODE ........................................................ 16
DIGITAL AUDIO INTERFACE – SLAVE MODE............................................................ 17
MPU INTERFACE TIMING............................................................................................ 18
DEVICE DESCRIPTION ...................................................................................... 20
INTRODUCTION ........................................................................................................... 20
AUDIO SIGNAL PATH................................................................................................... 21
DEVICE OPERATION ................................................................................................... 34
AUDIO DATA SAMPLING RATES ................................................................................ 41
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE................................................ 45
SOFTWARE CONTROL INTERFACE........................................................................... 45
POWER DOWN MODES............................................................................................... 47
REGISTER MAP............................................................................................................ 49
DIGITAL FILTER CHARACTERISTICS .............................................................. 54
TERMINOLOGY ............................................................................................................ 55
DAC FILTER RESPONSES................................................................................. 56
ADC FILTER RESPONSES................................................................................. 57
ADC HIGH PASS FILTER ............................................................................................. 58
DIGITAL DE-EMPHASIS CHARACTERISTICS.................................................. 58
DIGITAL DE-EMPHASIS CHARACTERISTICS.................................................. 59
APPLICATIONS INFORMATION ........................................................................ 60
RECOMMENDED EXTERNAL COMPONENTS ........................................................... 60
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS......................................... 61
PACKAGE DIMENSIONS - SSOP....................................................................... 62
PACKAGE DIMENSIONS - QFN......................................................................... 63
IMPORTANT NOTICE ......................................................................................... 64
ADDRESS: .................................................................................................................... 64
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Production Data
PIN CONFIGURATION - 28 PIN SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
1
DGND
DCVDD
XTO
DBVDD
CLKOUT
BCLK
2
3
4
XTI/MCLK
SCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
5
6
SDIN
CSB
7
8
MODE
9
LLINEIN
RLINEIN
MICIN
10
11
12
13
14
MICBIAS
VMID
ROUT
AGND
15
AVDD
ORDERING INFORMATION
TEMPERATURE
AVDD
RANGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
DEVICE
RANGE
PACKAGE
28-lead SSOP
(Pb-free)
-40 to +85oC
-40 to +85oC
2.7 to 3.6V
2.7 to 3.6V
MSL3
MSL3
260°C
WM8731SEDS/V
WM8731SEDS/RV
28-lead SSOP
260°C
(Pb-free,
tape and reel)
Note:
Reel quantity = 2,000
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Production Data
PIN CONFIGURATION – 28 PIN QFN
TOP VIEW
ORDERING INFORMATION
TEMPERATURE
RANGE
AVDD
RANGE
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
DEVICE
PACKAGE
28-lead QFN
(Pb-free)
WM8731CLSEFL
WM8731CLSEFL/R
WM8731CSEFL
WM8731CSEFL/R
-40 to +85oC
-40 to +85oC
-40 to +85oC
-40 to +85oC
1.8 to 3.6V
1.8 to 3.6V
2.7 to 3.6V
2.7 to 3.6V
MSL1
MSL1
MSL1
MSL1
260°C
260°C
260°C
260°C
28-lead QFN
(Pb-free,
tape and reel)
28-lead QFN
(Pb-free)
28-lead QFN
(Pb-free,
tape and reel)
Note:
Reel quantity = 3,500
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PIN DESCRIPTION
Production Data
28 PIN
SSOP
1
28 PIN
QFN
5
NAME
TYPE
DESCRIPTION
Digital Buffers VDD
DBVDD
CLKOUT
BCLK
Supply
Digital Output
Digital Input/Output
Digital Input
Buffered Clock Output
2
6
Digital Audio Bit Clock, Pull Down, (see Note 1)
DAC Digital Audio Data Input
3
7
4
8
DACDAT
DACLRC
ADCDAT
ADCLRC
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)
ADC Digital Audio Data Output
ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)
Headphone VDD
5
9
Digital Input/Output
Digital Output
Digital Input/Output
Supply
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
7
8
Left Channel Headphone Output
Right Channel Headphone Output
Headphone GND
9
Analogue Output
Analogue Output
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
Left Channel Line Output
Analogue Output
Analogue Output
Supply
Right Channel Line Output
ROUT
Analogue VDD
AVDD
Analogue GND
AGND
Ground
Mid-rail reference decoupling point
Electret Microphone Bias
VMID
Analogue Output
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Digital Input
MICBIAS
MICIN
Microphone Input (AC coupled)
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull Up (see Note 1)
RLINEIN
LLINEIN
MODE
3-Wire MPU Chip Select/ 2-Wire MPU interface address
selection, active low, Pull up (see Note 1)
CSB
Digital Input
3-Wire MPU Data Input / 2-Wire MPU Data Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Crystal Input or Master Clock Input (MCLK)
Crystal Output
23
24
25
26
27
28
27
28
1
SDIN
SCLK
Digital Input/Output
Digital Input
Digital Input
Digital Output
Supply
XTI/MCLK
XTO
2
Digital Core VDD
3
DCVDD
DGND
Digital GND
4
Ground
Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.
2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.
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WM8731 / WM8731L
Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
CONDITION
MIN
-0.3V
MAX
+3.63V
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, TA
Storage temperature after soldering
-0.3V
+3.63V
DGND -0.3V
AGND -0.3V
-40C
DVDD +0.3V
AVDD +0.3V
+85C
-65C
+150C
Notes:
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD)
RECOMMENDED OPERATING CONDITIONS – WM8731
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
DCVDD
DBVDD
1.42
2.7
3.6
3.6
3.6
V
V
V
V
AVDD, HPVDD
DGND,AGND,HPGND
2.7
0
Notes:
1. DCVDD must be lower than or equal to DBVDD.
2. USB Mode should not be used with DCVDD lower than 2V
RECOMMENDED OPERATING CONDITIONS – WM8731L
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
DCVDD
DBVDD
1.42
1.8
3.6
3.6
3.6
V
V
V
V
AVDD, HPVDD
DGND,AGND,HPGND
1.8
0
Notes:
1. If DBVDD is lower than 2.5V, DCVDD must be at least 0.225V lower than DBVDD.
2. If DBVDD is higher than or equal to 2.5V, DCVDD must be lower than or equal to DBVDD.
3. USB Mode should not be used with DCVDD lower than 2V
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WM8731 / WM8731L
Production Data
ELECTRICAL CHARACTERISTICS – WM8731
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
VOL
0.3 x DBVDD
V
V
V
Input HIGH level
0.7 x DBVDD
0.9 x DBVDD
Output LOW
0.10 x
DBVDD
Output HIGH
VOH
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Hysteresis
Vth
VIH
VOL
0.9
0.3
0.6
V
V
V
DCVDD Threshold Off -> On
Analogue Reference Levels
Reference voltage (VMID)
Potential divider resistance
Line Input to ADC
VVMID
RVMID
AVDD/2
50k
V
Ω
Input Signal Level (0dB)
VINLINE
1.0
AVDD/3.3
90
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
SNR
A-weighted, 0dB gain
@ fs = 48kHz
85
85
A-weighted, 0dB gain
@ fs = 96kHz
90
88
A-weighted, 0dB gain
@ fs = 48kHz,
AVDD = 2.7V
Dynamic Range (Note 3)
Total Harmonic Distortion
DR
A-weighted, -60dB full
scale input
90
dB
THD
-1dB input, 0dB gain
-84
0.006
50
-74
dB
%
0.02
Power Supply Rejection Ratio
PSRR
1kHz, 100mVpp
dB
20Hz to 20kHz,
100mVpp
45
ADC channel separation
Programmable Gain
1kHz input
1kHz input
90
0
dB
dB
-34.5
+12
Rsource < 50Ω
Guaranteed Monotonic
0dB, 1kHz input
0dB gain
Programmable Gain Step Size
Mute attenuation
1.5
80
dB
dB
Ω
Input Resistance
RINLINE
20k
10k
30k
15k
10
12dB gain
Input Capacitance
CINLINE
pF
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Production Data
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
Microphone Input to ADC @ 0dB Gain, fs = 48kHz (40kΩ Source Impedance. See Figure 12)
Input Signal Level (0dB)
VINMIC
SNR
DR
1.0
AVDD/3.3
85
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
A-weighted, 0dB gain
Dynamic Range (Note 3)
A-weighted, -60dB full
scale input
85
dB
Total Harmonic Distortion
THD
0dB input, 0dB gain
1kHz 100mVpp
-60
50
45
-55
dB
dB
dB
Power Supply Rejection Ratio
PSRR
20Hz to 20kHz
100mVpp
Programmable Gain Boost
MICBOOST bit
set
1kHz input
34
14
dB
dB
Rsource < 50Ω
MICBOOST = 0
Rsource < 50Ω
Mic Path gain (MICBOOST gain
is additional to this nominal
gain)
Mute attenuation
Input Resistance
Input Capacitance
Microphone Bias
Bias Voltage
0dB, 1kHz input
80
10k
10
dB
Ω
RINMIC
CINMIC
pF
VMICBIAS
0.75*AVDD – 0.75*AVDD 0.75*AVDD +
V
100mV
100mV
Bias Current Source
Output Noise Voltage
IMICBIAS
Vn
3
mA
1K to 20kHz
25
nV/Hz
Line Output for DAC Playback Only (Load= 10kΩ. 50pF)
0dBfs Full scale output voltage
At LINE outputs
1.0 x
AVDD/3.3
100
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
SNR
A-weighted,
@ fs = 48kHz
A-weighted
95
98
98
@ fs = 96kHz
A-weighted,
fs = 48kHz,
AVDD = 2.7V
Dynamic Range (Note 3)
Total Harmonic Distortion
DR
A-weighted, -60dB
full scale input
85
95
dB
dB
THD
1kHz, 0dBfs
1kHz, -3dBfs
1kHz 100mVpp
-88
-92
50
-80
Power Supply Rejection Ratio
PSRR
dB
20Hz to 20kHz
100mVpp
45
DAC channel separation
1kHz, 0dB
100
dB
Vrms
dB
Analogue Line Input to Line Output (Load= 10kΩ. 50pF, No Gain on Input ) Bypass Mode
0dB Full scale output voltage
1.0 x
AVDD/3.3
95
Signal to Noise Ratio
(Note 1,3)
SNR
THD
90
Total Harmonic Distortion
1kHz, 0dB
1kHz, -3dB
-86
-92
50
-80
dB
Power Supply Rejection Ratio
PSSR
1kHz 100mVpp
dB
20Hz to 20kHz
100mVpp
45
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WM8731 / WM8731L
Production Data
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
Mute attenuation
1kHz, 0dB
80
dB
Stereo Headphone Output
0dB Full scale output voltage
1.0 x
AVDD/3.3
30
Vrms
mW
Max Output Power
PO
RL = 32Ω
RL = 16Ω
50
Signal to Noise Ratio (Note 1, 3)
Total Harmonic Distortion
SNR
THD
A-weighted
90
97
dB
%
1kHz, RL = 32Ω
PO = 10mW rms (-5dB)
1kHz, RL = 32Ω
PO = 20mW rms (-2dB)
1kHz 100mVpp
20Hz - 20kHz, 100mVpp
1kHz
0.056
-65
0.1
60
dB
%
0.56
-45
1.0
40
dB
dB
Power Supply Rejection Ratio
PSRR
50
45
Programmable Gain
-73
0
6
dB
dB
dB
Programmable Gain Step Size
Mute attenuation
1kHz
1
1kHz, 0dB
80
Microphone Input to Headphone Output Side Tone Mode
0dB Full scale output voltage
1.0 x
AVDD/3.3
95
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
SNR
90
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
50
45
dB
20Hz to 20kHz
100mVpp
Programmable Attenuation
1kHz
1kHz
6
15
dB
dB
Programmable Attenuation Step
Size
3
Mute attenuation
1kHz, 0dB
80
dB
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz
to 20kHz bandwidth using an Audio analyser.
2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a
20Hz to 20kHz bandwidth.
3. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will
result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass
filter removes out of band noise; although it is not audible it may affect dynamic specification values.
4. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
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Production Data
POWER CONSUMPTION – WM8731
MODE
CURRENT CONSUMPTION
DESCRIPTION
TYPICAL
AVDD
(3.3V)
HP
DC
DB
UNIT
VDD
(3.3V)
VDD
(1.5V)
VDD
(3.3V)
Record and Playback
Oscillator enabled
External MCLK
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
13.1
13.1
12.2
1.7
1.7
1.7
3.0
3.2
3.2
1.5
0.8
mA
mA
mA
Oscillator and
0.07
CLKOUT disabled,
No microphone
Playback Only
Oscillator enabled
External MCLK
Record Only
0
0
0
1
0
1
0
0
0
0
1
1
1
1
1
1
3.4
3.3
1.7
1.7
2.1
2.3
1.5
mA
mA
0.07
Line Record,
oscillator enabled
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
9.2
9.2
8.6
8.6
-
-
-
-
2.6
2.6
2.7
2.6
1.3
0.7
1.5
0.7
mA
mA
mA
mA
Line Record, using
external MCLK
Mic Record,
oscillator enabled
Mic Record, using
external MCLK
Side Tone (Microphone Input to Headphone Output)
External clock still
running
0
0
1
0
1
1
0
1
1
1.6
1.5
1.7
1.7
0.08
-
0.7
-
mA
mA
Clock stopped
0
0
1
0
1
1
0
Analogue Bypass (Line-in to Line-out)
External clock still
running
0
0
1
1
0
0
1
1
1
1
1
1
0
0
2.1
2.2
1.7
1.7
0.08
-
0.7
-
mA
mA
Clock stopped
0
0
Standby
External clock still
running
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
16
0.3
0.3
77
65
A
A
Clock stopped
0.3
0.2
Power Down
External clock still
running
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0.2
0.3
0.3
0.3
77
65
A
A
Clock stopped
0.3
0.3
Table 1 Powerdown Mode Current Consumption Examples
Notes:
1. TA = +25oC. fs = 48kHz, XTI/MCLK = 256fs (12.288MHz).
2. The data presented here was measured with the audio interface in master mode whenever the internal clock oscillator
was used, and in slave mode whenever an external clock was used (i.e. MS = 1 when OSCPD = 0 and vice versa).
However, it is also possible to use the WM8731 with MS = OSCPD = 0 or MS = OSCPD = 1.
3. All figures are quiescent, with no signal.
4. The power dissipation in the headphone itself not included in the above table.
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ELECTRICAL CHARACTERISTICS – WM8731L
Test Conditions
AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
VOL
0.3 x DBVDD
V
V
V
Input HIGH level
0.7 x DBVDD
0.9 x DBVDD
Output LOW
0.10 x
DBVDD
Output HIGH
VOH
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Hysteresis
Vth
VIH
VOL
0.9
0.3
0.6
V
V
V
DCVDD Threshold Off -> On
Analogue Reference Levels
Reference voltage (VMID)
Potential divider resistance
Line Input to ADC
VVMID
RVMID
AVDD/2
50k
V
Ω
Input Signal Level (0dB)
VINLINE
SNR
1.0
AVDD/3.3
85
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
A-weighted, 0dB gain
@ fs = 48kHz
75
80
A-weighted, 0dB gain
@ fs = 96kHz
85
88
Dynamic Range (Note 3)
DR
A-weighted, -60dB full
scale input
dB
Total Harmonic Distortion
THD
-1dB input, 0dB gain
1kHz, 100mVpp
-76
50
45
-60
dB
dB
Power Supply Rejection Ratio
PSRR
20Hz to 20kHz,
100mVpp
ADC channel separation
Programmable Gain
1kHz input
1kHz input
90
0
dB
dB
-34.5
+12
Rsource < 50Ω
Guaranteed Monotonic
0dB, 1kHz input
0dB gain
Programmable Gain Step Size
Mute attenuation
1.5
80
dB
dB
Ω
Input Resistance
RINLINE
20k
10k
30k
15k
10
12dB gain
Input Capacitance
CINLINE
pF
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Test Conditions
AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
Microphone Input to ADC @ 0dB Gain, fs = 48kHz (40kΩ Source Impedance. See Figure 12)
Input Signal Level (0dB)
VINMIC
SNR
DR
1.0
AVDD/3.3
80
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
A-weighted, 0dB gain
Dynamic Range (Note 3)
A-weighted, -60dB full
scale input
70
dB
Total Harmonic Distortion
THD
0dB input, 0dB gain
1kHz 100mVpp
-55
50
45
dB
dB
dB
Power Supply Rejection Ratio
PSRR
20Hz to 20kHz
100mVpp
Programmable Gain Boost
MICBOOST bit
set
1kHz input
34
14
dB
dB
Rsource < 50Ω
MICBOOST = 0
Rsource < 50Ω
0dB, 1kHz input
Mic Path gain (MICBOOST gain
is additional to this nominal gain)
Mute attenuation
Input Resistance
Input Capacitance
Microphone Bias
Bias Voltage
80
10k
10
dB
Ω
RINMIC
CINMIC
pF
VMICBIAS
0.75*AVDD – 0.75*AVDD 0.75*AVDD +
V
100mV
100mV
Bias Current Source
Output Noise Voltage
IMICBIAS
Vn
3
mA
1K to 20kHz
25
nV/Hz
Line Output for DAC Playback Only (Load= 10k Ω. 50pF)
0dBfs Full scale output voltage
At LINE outputs
1.0 x
AVDD/3.3
95
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
SNR
A-weighted,
@ fs = 48kHz
A-weighted
85
85
93
90
@ fs = 96kHz
Dynamic Range (Note 3)
Total Harmonic Distortion
DR
A-weighted, -60dB
full scale input
dB
dB
THD
1kHz, 0dBfs
1kHz, -3dBfs
1kHz 100mVpp
-80
-90
50
-75
Power Supply Rejection Ratio
PSRR
dB
20Hz to 20kHz
100mVpp
45
DAC channel separation
1kHz, 0dB
100
dB
Vrms
dB
Analogue Line Input to Line Output (Load= 10k Ω. 50pF, No Gain on Input ) Bypass Mode
0dB Full scale output voltage
1.0 x
AVDD/3.3
90
Signal to Noise Ratio
(Note 1,3)
SNR
THD
85
Total Harmonic Distortion
1kHz, 0dB
1kHz, -3dB
-83
-92
50
-76
dB
Power Supply Rejection Ratio
Mute attenuation
PSSR
1kHz 100mVpp
dB
20Hz to 20kHz
100mVpp
45
1kHz, 0dB
80
dB
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Test Conditions
AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
Stereo Headphone Output
0dB Full scale output voltage
1.0 x
Vrms
mW
dB
AVDD/3.3
Max Output Power
PO
RL = 32 Ω
RL = 16 Ω
A-weighted
9
18
95
Signal to Noise Ratio
(Note 1,3)
SNR
THD
86
Total Harmonic Distortion
1kHz, -5dB FS signal
RL = 32Ω
0.08
-62
0.1
-60
1
%
dB
1kHz, -2dB FS signal
RL = 32Ω
-40
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
20Hz - 20kHz, 100mVpp
1kHz
50
45
0
dB
Programmable Gain
-73
6
dB
dB
dB
Programmable Gain Step Size
Mute attenuation
1kHz
1
1kHz, 0dB
80
Microphone Input to Headphone Output Side Tone Mode
0dB Full scale output voltage
1.0 x
AVDD/3.3
90
Vrms
dB
Signal to Noise Ratio
(Note 1,3)
SNR
85
Power Supply Rejection Ratio
PSRR
1kHz 100mVpp
50
45
dB
20Hz to 20kHz
100mVpp
Programmable Attenuation
1kHz
1kHz
6
15
dB
dB
Programmable Attenuation Step
Size
3
Mute attenuation
1kHz, 0dB
80
dB
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz
to 20kHz bandwidth using an Audio analyser.
2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a
20Hz to 20kHz bandwidth.
3. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will
result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass
filter removes out of band noise; although it is not audible it may affect dynamic specification values.
4. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
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POWER CONSUMPTION – WM8731L
MODE
CURRENT CONSUMPTION
DESCRIPTION
TYPICAL
AVDD
(1.8V)
6
HP
DC
DB
UNIT
VDD
(1.8V)
VDD
(1.5V)
VDD
(1.8V)
Record and Playback
All active, oscillator
enabled
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0.6
0.6
2.7
1.8
0.9
0.9
mA
mA
Playback Only
Oscillator enabled
Record Only
1.7
Line Record,
oscillator enabled
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
1
3.9
3.6
-
-
2.4
2.4
0.9
0.9
mA
mA
Mic Record,
oscillator enabled
Side Tone (Microphone Input to Headphone Output)
Clock stopped
Analogue Bypass (Line-in to Line-out)
0
0
1
1
1
1
0
0
1
1
1
1
0
1
0
1
1
0.8
1.1
8
0.6
0.6
-
-
-
-
-
mA
mA
A
Clock stopped
Standby
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
Clock stopped
Power Down
Clock stopped
-
-
0.2
0.2
0.3
0.2
A
Table 2 Powerdown Mode Current Consumption Examples
Notes:
1. AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC. Slave Mode, fs = 48kHz,
XTI/MCLK = 256fs (12.288MHz).
2. All figures are quiescent, with no signal.
3. All figures are measured with the audio interface in master mode (MS = 1).
4. The power dissipation in the headphone itself is not included in the above table.
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MASTER CLOCK TIMING
tXTIL
XTI/MCLK
tXTIH
tXTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
XTI/MCLK System clock pulse width
high
tXTIH
tXTIL
tXTIY
18
18
ns
ns
ns
XTI/MCLK System clock pulse width
low
XTI/MCLK System clock cycle time
XTI/MCLK Duty cycle
54
40:60
60:40
XTI/MCLK
CLKOUT
tCOP
CLKOUT
(DIV X2)
Figure 2 Clock Out Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
CLKOUT propagation delay from
XTI/MCLK falling edge
tCOP
0
10
ns
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DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
WM8731
DSP
ENCODER/
DECODER
DACLRC
CODEC
ADCDAT
DACDAT
Note: ADC and DAC can run at different rates
Figure 3 Master Mode Connection
BCLK
(Output)
tDL
ADCLRC
DAC/LRC
(Outputs)
tDDA
ADCDAT
DACDAT
tDST
tDHT
Figure 4 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, HPVDD, DBDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC
propagation delay from
BCLK falling edge
tDL
0
10
ns
ADCDAT propagation delay
from BCLK falling edge
tDDA
tDST
tDHT
0
35
ns
ns
ns
DACDAT setup time to
BCLCK rising edge
10
10
DACDAT hold time from
BCLK rising edge
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DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
ADCLRC
WM8731
DSP
ENCODER/
DECODER
DACLRC
CODEC
ADCDAT
DACDAT
Note: The ADC and DAC can run at different rates
Figure 5 Slave Mode Connection
tBCH
tBCL
BCLK
tBCY
DACLRC/
ADCLRC
tLRSU
tDS
tLRH
DACDAT
ADCDAT
tDD
tDH
Figure 6 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tLRSU
DACLRC/ADCLRC hold
time from BCLK rising edge
tLRH
tDS
10
10
10
ns
ns
ns
DACDAT set-up time to
BCLK rising edge
DACDAT hold time from
BCLK rising edge
tDH
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Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADCDAT propagation delay
from BCLK falling edge
tDD
0
35
ns
MPU INTERFACE TIMING
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 7 Program Register Input Timing - 3-Wire MPU Serial Control Mode
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
CSB pulse width high
CSB rising to SCLK rising
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t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t10
Figure 8 Program Register Input Timing – 2-Wire MPU Serial Control Mode
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
526
kHz
us
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulsewidth
SCLK High Pulsewidth
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t10
1.3
600
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
300
300
600
900
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DEVICE DESCRIPTION
INTRODUCTION
The WM8731/L is a low power audio CODEC designed specifically for portable audio products. It’s
features, performance and low power consumption make it ideal for portable MP3 players and
portable mini-disc players.
The CODEC includes line and microphone inputs to the on-board ADC, line and headphone outputs
from the on-board DAC, a crystal oscillator, configurable digital audio interface and a choice of 2 or 3
wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard
microprocessors, controllers and DSPs.
The CODEC includes three low noise inputs - mono microphone and stereo line. Line inputs have
+12dB to -34dB logarithmic volume level adjustments and mute. The Microphone input has -6dB to
34dB volume level adjustment. An electret microphone bias level is also available. All the required
input filtering is contained within the device with no external components required.
The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit high-
order oversampling architecture delivering optimum performance with low power consumption. The
output from the ADC is available on the digital audio interface. The ADC includes an optional digital
high pass filter to remove unwanted dc components from the audio signal.
The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio
interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data
under software control. The DAC employs a high quality multi-bit high-order oversampling architecture
to again deliver optimum performance with low power consumption.
The DAC outputs, Microphone (SIDETONE) and Line Inputs (BYPASS) are available both at line level
and through a headphone amplifier capable of efficiently driving low impedance headphones. The
headphone output volume is adjustable in the analogue domain over a range of +6dB to –73dB and
can be muted.
The design of the WM8731/L has given much attention to power consumption without compromising
performance. It includes the ability to power off selective parts of the circuitry under software control,
thus conserving power. Nine separate power save modes be configured under software control
including a standby and power off mode.
Special techniques allow the audio to be muted and the device safely placed into standby, sections of
the device powered off and volume levels adjusted without any audible clicks, pops or zipper noises.
Therefore standby and power off modes maybe used dynamically under software control, whenever
recording or playing is not required.
The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz,
44.1kHz, 48kHz, 88.2kHz and 96kHz. Additionally, the device has an ADC and DAC that can operate
at different sample rates.
There are two unique schemes featured within the programmable sample rates of the WM8731/L:
Normal industry standard 256/384fs sampling mode may be used, with the added ability to mix
different sampling rates. Also a special USB mode is included, whereby all audio sampling rates can
be generated from a 12.00MHZ USB clock. Thus, for example, the ADC can record to the DSP at
44.1kHz and be played back from the CODEC at 8kHz with no external digital signal processing
required. The digital filters used at for both record and playback are optimised for each sampling rate
used.
The digitised output is available in a number of audio data formats I2S, DSP Mode (a burst mode in
which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First,
right justified. The digital audio interface can operate in both master or slave modes.
The software control uses either 2 or 3-wire MPU interface.
A crystal oscillator is included on board the device. The device can generate the system master clock
or alternatively it can accept an external master clock from the audio system.
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AVDD
VMID
CONTROL INTERFACE
WM8731
HPVDD
Bypass, Reg 08h
MUTE
HPGND
AGND
ATTEN/
MUTE
+6 to -73dB
1 dB Steps, Reg 06h
SIDEATT,
Reg 08h
H/P
DRIVER
VOL/
MUTE
RLINEIN Mute
Reg 02h
MICBIAS
RLINEIN
RHPOUT
INSEL, Reg 08h
VOL
MUTE
MUTE
ADC
ADC
MUX
DAC
DAC
MUTE
+12 to -34.5dB, 1.5dB Steps,
Reg 02h
SIDETONE
Reg 08h
DACMUTE
Reg 0Ah
ROUT
LOUT
0dB/
20dB
DIGITAL
FILTERS
MICIN
DACMUTE
Reg 0Ah
SIDETONE
Reg 08h
MIC BOOST Reg 08h
MUTE
MUTE
MUX
MUTE
VOL
LLINEIN
VOL/
MUTE
H/P
DRIVER
LLINEIN Mute
Reg 00h
INSEL, Reg 08h
LHPOUT
+12 to -34.5dB, 1.5dB Steps,
Reg 00h
SIDEATT,
Reg 08h
+6 to -73dB
1 dB Steps, Reg 04h
ATTEN/
MUTE
OSCPD
Reg 0Ch
MUTE
CLKODIV2, Reg 10h
CLKOUT
DIVIDER
CLKIN
DIVIDER
Bypass, Reg 08h
OSC
DIGTAL AUDIO INTERFACE
(Div x1, x2)
(Div x1, x2)
CLKIDIV2, Reg 10h
CLKOUTPD, Reg 0Ch
Figure 9 Functional Block Diagram
AUDIO SIGNAL PATH
LINE INPUTS
The WM8731/L provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are
high impedance and low capacitance, thus ideally suited to receiving line level signals from external
hi-fi or audio equipment.
Both line inputs include independent programmable volume level adjustments and ADC input mute.
The scheme is illustrated in Figure 10. Passive RF and active Anti-Alias filters are also incorporated
within the line inputs. These prevent high frequencies aliasing into the audio band or otherwise
degrading performance.
LINEIN
12.5k
To
ADC
VMID
Figure 10 Line Input Schematic
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The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in
1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any
voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full
scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left
Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both
channels are simultaneously updated with the same value. Use of INBOTH reduces the required
number of software writes required. The line inputs to the ADC can be muted in the analogue domain
under software control. The software control registers are shown Table 3. Note that the Line Input
Mute only mutes the input to the ADC, this will still allow the Line Input signal to pass to the line
output in Bypass Mode.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000000
4:0
LINVOL[4:0]
10111
( 0dB )
Left Channel Line Input Volume
Control
Left Line In
11111 = +12dB . . 1.5dB steps down
to 00000 = -34.5dB
7
8
LINMUTE
1
0
Left Channel Line Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
LRINBOTH
Left to Right Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
LINVOL[4:0] and LINMUTE to
RINVOL[4:0] and RINMUTE
0 = Disable Simultaneous Load
0000001
4:0
7
RINVOL[4:0]
RINMUTE
10111
( 0dB )
Right Channel Line Input Volume
Control
Right Line In
11111 = +12dB . .1.5dB steps down
to 00000 = -34.5dB
1
0
Right Channel Line Input Mute to
ADC
1 = Enable Mute
0 = Disable Mute
8
RLINBOTH
Right to Left Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
RINVOL[4:0] and RINMUTE to
LINVOL[4:0] and LINMUTE
0 = Disable Simultaneous Load
Table 3 Line Input Software Control
The line inputs are biased internally through the operational amplifier to VMID. Whenever the line
inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID
using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when
re-activating the inputs.
The external components required to complete the line input application is shown in the Figure 11.
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C2
R1
LINEIN
C1
R2
AGND
AGND AGND
Figure 11 Line Input Application Drawing
For interfacing to a typical CD system, it is recommended that the input is scaled to ensure that there
is no clipping of the signal. R1 = 5.6k, R2 = 5.6k, C1 = 220pF, C2 = 1F.
R1 and R2 form a resistive divider to attenuate the 2 Vrms output from a CD player to a 1 Vrms level,
so avoiding overloading the inputs. R2 also provides a discharge path for C2, thus preventing the
input to C2 charging to an excessive voltage which may otherwise damage any equipment connected
that is not suitably protected against high voltages. C1 forms an RF low pass filter for increasing the
rejection of RF interference picked up on any cables. C2 forms a DC blocking capacitor to remove the
DC path between the WM8731/L and the driving audio equipment. C2 together with the input
impedance of the WM8731/L form a high pass filter.
MICROPHONE INPUT
MICIN is a high impedance, low capacitance input suitable for connection to a wide range of
monophonic microphones of different dynamics and sensitivities.
The MICIN includes programmable volume adjustments and a mute function. The scheme is shown in
Figure 12. Passive RF and active Anti-Alias filters are also incorporated within the microphone
inputs. These allow a matched interface to the multi-bit oversampling ADC and preventing high
frequencies aliasing into the audio band or otherwise degrading performance.
50k
20dB GAIN BOOST
MICIN
10k
VMID
To
ADC
VMID
Figure 12 Microphone Input Schematic
There are 2 stages of gain made up of two low noise inverting operational amplifiers.
The 1st stage comprises a nominal gain of G1 = 50k/10k = 5. By adding an external resistor (Rmic) in
series with MICIN the gain of stage can be adjusted. For example adding Rmic = 40K sets the gain of
stage 1 to x1 (0dB). The equation below can be used to calculate the gain versus Rmic.
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G1 = 50k/ (Rmic + 10k)
Or alternatively to calculate the value of Rmic to achieve a given gain, G1.
Rmic = (50k/G1) – 10k
The internal 50k and 10k resistors have a tolerance of 15%. For Rmicext = 90k G = 0.5 (-6dB) and for
Rmicext = 0 G = x10 (14dB).
The 2nd stage comprises a 0dB gain stage that can be software configured to provide a fixed 20dB of
gain for low sensitivity microphones.
The microphone input can therefore be configured with a variable gain of between -6dB and 14dB on
the 1st stage, and an additional fixed 0dB or 20dB on the 2nd stage. This allows for all gains to the
input signal in the range –6dB to 34dB to be catered for.
The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will
possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with
AVDD. Stage 1 and Stage 2 gains should be configured so that the ADC receives a maximum signal
equal to its full scale for maximising the signal to noise.
The software control for the MICIN is shown in Table 4. Note that the Microphone Mute only mutes
the input to the ADC, this will still allow the Microphone Input signal to pass to the line output in
Sidetone Mode.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000100
0
MICBOOST
0
Microphone Input Level Boost
1 = Enable Boost
Analogue Audio
Path Control
0 = Disable Boost
1
MUTEMIC
1
Line Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
Table 4 Microphone Input Software Control
The microphone input is biased internally through the operational amplifier to VMID. Whenever the
line inputs are muted the MICIN input is kept biased to VMID using special anti-thump circuitry. This
reduces any audible clicks that may otherwise be heard when re-activating the input.
The application drawing for the microphone is shown in Figure 13.
MICBIAS
R1
Rmic
C2
FROM
MICIN
MICROPHONE
C1
R2
AGND
AGND AGND
Figure 13 Microphone Input and Bias Application Drawing
Recommended component values are C1 = 220pF (npo ceramic), C2 = 1F, R1 = 680 Ω, R2 = 47k.
Rmic values depends on gain setting (see above).
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R1 and R2 form part of the biasing network (refer to Microphone Bias section below). R1 connected to
MICBIAS is necessary only for electret type microphones that require a voltage bias. R2 should
always be present to prevent the microphone input from charging to a high voltage which may
damage the microphone on connection. R1 and R2 should be large so as not to attenuate the signal
from the microphone, which can have source impedance greater than 2k. C1 together with the source
impedance of the microphone and the input impedance of MICIN forms an RF filter. C2 is a DC
blocking capacitor to allow the microphone to be biased at a different DC voltage to the MICIN signal.
MICROPHONE BIAS
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type
microphones and the associated external resistor biasing network. Refer to the Microphone Input
section for an application drawing and further description.
The scheme for MICBIAS is shown in Figure 14. Note that there is a maximum source current
capability of 3mA available for the MICBIAS. This limits the smallest value of external biasing
resistors that can safely be used.
Note that the MICBIAS output is not active in standby mode.
VMID
MICBIAS
AGND
Figure 14 Microphone Bias Schematic
ADC
The WM8731/L uses a multi-bit oversampled sigma-delta ADC. A single channel of the ADC is
illustrated in the Figure 15.
FROM MICROPHONE
INPUT
ANALOG
INTEGRATOR
TO ADC DIGITAL FILTERS
FROM LINE INPUT
MULTI
BITS
INSEL
Figure 15 Multi-Bit Oversampling Sigma Delta ADC Schematic
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The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high
frequency noise.
The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will
possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with
AVDD.
The device employs a pair of ADCs. The input can be selected from either the Line Inputs or the
Microphone input under software control. The two channels cannot be selected independently. The
control is shown in Table 5.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000100
2
INSEL
0
Microphone/Line Input Select to ADC
1 = Microphone Input Select to ADC
0 = Line Input Select to ADC
Analogue
Audio Path
Control
Table 5 ADC Software Control
The digital data from the ADC is fed for signal processing to the ADC Filters.
ADC FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 16
illustrates the digital filter path.
TO DIGITAL
AUDIO
INTERFACE
DIGITAL
DIGITAL
DIGITAL
HPF
DECIMATION
FILTER
FROM ADC
DECIMATOR
HPFEN
Figure 16 ADC Digital Filter
The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass
filter response detailed in Digital Filter Characteristics. When the high-pass filter is enabled the dc
offset is continuously calculated and subtracted from the input signal. By setting HPOR the last
calculated dc offset value is stored when the high-pass filter is disabled and will continue to be
subtracted from the input signal. If the dc offset changes, the stored and subtracted value will not
change unless the high-pass filter is enabled. The software control is shown in Table 6.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000101
0
ADCHPD
0
ADC High Pass Filter Enable
(Digital)
Digital Audio
Path Control
1 = Disable High Pass Filter
0 = Enable High Pass Filter
Store dc offset when High Pass
Filter disabled
4
HPOR
0
1 = store offset
0 = clear offset
Table 6 ADC Software Control
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There are several types of ADC filters, frequency and phase responses of these are shown in Digital
Filter Characteristics. The filter types are automatically configured depending on the sample rate
chosen. Refer to the sample rate section for more details.
DAC FILTERS
The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from
the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by
the analogue DAC. Figure 17 illustrates the DAC digital filter path.
FROM DIGITAL
DIGITAL
TO LINE
DIGITAL
MUTE
INTERPOLATION
AUDIO
INTERFACE
DE_EMPHASIS
OUTPUTS
FILTER
DEEMP
DACMU
Figure 17 DAC Filter Schematic
The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 7.The
DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This
removes any abrupt step changes in the audio that might otherwise result in audible clicks in the
audio outputs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000101
2:1
DEEMP[1:0]
00
De-emphasis Control
(Digital)
Digital
Audio Path
Control
11 = 48kHz
10 = 44.1kHz
01 = 32kHz
00 = Disable
3
DACMU
1
DAC Soft Mute Control
(Digital)
1 = Enable soft mute
0 = Disable soft mute
Table 7 DAC Software Control
Notes:
1. Not valid when SR[3:0] = 1111 or 0111.
2. To ensure correct DACMU operation at fs = 88.2kHz, set SR[3:0] = 1000.
3. To ensure correct DACMU operation at fs = 96kHz, set SR[3:0] = 0000.
DAC
The WM8731/L employs a multi-bit sigma delta oversampling digital to analogue converter. The
scheme for the converter is illustrated in Figure 18.
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FROM DAC
DIGITAL
FILTERS
TO LINE OUTPUT
Figure 18 Multi-Bit Oversampling Sigma Delta Schematic
The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality
analogue audio.
LINE OUTPUTS
The WM8731/L provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for
driving typical line loads of impedance 10K and capacitance 50pF. The line output is used to
selectively sum the outputs from the DAC or/and the Line inputs in bypass mode.
The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level
adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC
full scale level the output level is 1.0Vrms at AVDD = 3.3 volts. Note that the DAC full scale level
tracks directly with AVDD. The scheme is shown in Figure 19. The line output includes a low order
audio low pass filter for removing out-of band components from the sigma-delta DAC. Therefore no
further external filtering is required in most applications.
SIDETONE
FROM MICROPHONE
INPUT
BYPASS
FROM LINE
INPUTS
DACSEL
FROM DAC
LINEOUT
VMID
TO HEADPHONE AMP
Figure 19 Line Output Schematic
The DAC output, Line Input and microphone are summed into the Line Output. In DAC mode only the
output from the DAC is routed to the line outputs. In Bypass mode the Line Input is summed into the
Line Outputs. In Side Tone mode the Microphone Input is summed into the Line Output. These
features can be used for either over-dubbing or, if the DAC is muted, as a pure analogue bypass or
Side Tone feature, so avoiding any digital signal processing.
The line output is muted by either muting the DAC (analogue) or Soft Muting (digital) and disabling
the BYPASS and SIDETONE paths. Refer to the DAC section for more details. Whenever the DAC is
muted or the device placed into standby mode the DC voltage is maintained at the line outputs to
prevent any audible clicks from being present.
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The software control for the line outputs is shown in Table 8.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000100
Bypass Switch
1 = Enable Bypass
3
BYPASS
1
Analogue
Audio Path
Control
0 = Disable Bypass
DAC Select
4
5
DACSEL
0
0
1 = Select DAC
0 = Don’t select DAC
Side Tone Switch
1 = Enable SideTone
0 = Disable Side Tone
SIDETONE
Table 8 Output Software Control
The recommended external components are shown in Figure 20.
R2
LINEOUT
C1
R1
AGND
AGND
Figure 20 Line Outputs Application Drawing
Recommended values are C1 = 10F, R1 = 47k, R2 = 100 Ω.
C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so
protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing
abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can
have dramatic effects on the measured signal distortion at the output
HEADPHONE AMPLIFIER
The WM8731/L has a stereo headphone output available on LHPOUT and RHPOUT. The output is
designed specifically for driving 16 or 32 Ω headphones with maximum efficiency and low power
consumption. The headphone output includes a high quality volume level adjustment and mute
function.
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The scheme of the circuit is shown in Figure 21.
FROM
DAC VIA
LINEOUT
HPOUT
VMID
Figure 21 Headphone Amplifier Schematic
LHPOUT and RHPOUT volumes can be independently adjusted under software control using the
LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The
adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB.
The headphone outputs can be separately muted by writing codes less than 0110000 to LHPVOL[6:0]
or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device placed into standby
mode, the DC voltage is maintained at the line outputs to prevent any audible clicks from being
present.
A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN
and RZCEN bits of the headphone output control register. Using these controls the volume control
values are only updated when the input signal to the gain stage is close to the analogue ground level.
This minimises and audible clicks and zipper noise as the gain values are changed or the device
muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage
input of more than approximately 20mV, then the gain will not be updated. This zero cross function is
enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is
concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set
high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low
will force a volume update, regardless of the DC level.
LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively,
the user can lock the two channels together, allowing both to be updated simultaneously, halving the
number of serial writes required, provided that the same gain is needed for both channels. This is
achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing
to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The
corresponding effect on updating RLHPBOTH is also achieved.
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The software control is given in Table 9.
REGISTER
ADDRESS
BIT
6:0
LABEL
DEFAULT
DESCRIPTION
0000010
LHPVOL[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
Left
Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
LZCEN
0
0
Left Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
LRHPBOTH
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
0000011
6:0
RHPVOL[6:0]
1111001
( 0dB )
Right Channel Headphone Output
Volume Control
Right
Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
RZCEN
0
0
Right Channel Zero Cross Detect
Enable
1 = Enable
0 = Disable
RLHPBOTH
Right to Left Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
RHPVOL[6:0] and RZCEN to
LHPVOL[6:0] and LZCEN
0 = Disable Simultaneous Load
Table 9 Headphone Output Software Control
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The recommended external components required to complete the application are shown in Figure 22.
HPOUT
C1
AGND
R1
AGND
Figure 22 Headphone Output Application Drawing
Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k
C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a
pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from
rising to a level that may damage the headphones.
BYPASS MODE
The WM8731/L includes a bypass mode whereby analogue line inputs are routed directly to the
analogue line outputs and headphone outputs. The scheme for this is in Figure 23.
LINEIN
12.5K
SIDETONE (OFF)
BYPASS (ON)
VMID
FROM
LINE
INPUTS
DACSEL (OFF)
FROM
DAC
LINEOUT
VMID
HPOUT
VMID
Figure 23 Signal Routing in Bypass Mode
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The bypass mode is selected under software control using the BYPASS microphone bit as shown in
Table 10. In true bypass mode, the output from the DAC (DACSEL) and (SIDETONE) should be de-
selected from the line output block. However this can also be used to sum the DAC output, Line
Inputs together and microphone inputs. The analogue line input and headphone output volume
controls and mutes are still operational in bypass mode. The 0dB gain setting is recommended for the
Line Input volume control to avoid distortion. The maximum signal at any point in the bypass path
must be no greater than 1.0V rms at AVDD = 3.3V, to avoid distortion. This amplitude tracks linearly
with AVDD. This means that if the DAC is producing a 1Vrms signal, and it is being summed with
1Vrms line BYPASS signal, the resulting LINEOP signal will be clipped.
REGISTER
ADDRESS
BIT
LABEL
BYPASS
DEFAULT
DESCRIPTION
0000100
3
1
Bypass Switch (Analogue)
1 = Enable Bypass
Analogue
Audio Path
Control
0 = Disable Bypass
Table 10 Bypass Mode Software Control
SIDETONE MODE
The WM8731/L also includes a side tone mode where the microphone input is routed to line and
headphone outputs. The scheme for this is shown in Figure 24.
The side tone mode allows the microphone input to be attenuated to the outputs for telephone and
headset applications.
50k
10dB GAIN BOOST
MICIN
10k
VMID
SIDETONE (ON)
VMID
BYPASS (OFF)
FROM
LINE
INPUTS
DACSEL (OFF)
FROM
DAC
LINEOUT
VMID
HPOUT
VMID
Figure 24 Side Tone Mode Schematic
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
0000100
5
SIDETONE
0
Side Tone Switch (Analogue)
1 = Enable Side Tone
0 = Disable Side Tone
Side Tone Attenuation
11 = -15dB
Analogue
Audio Path
Control
7:6
SIDEATT[1:0]
00
10 = -12dB
01 = -9dB
00 = -6dB
Table 11 Side Tone Mode Table
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The side tone mode and attenuation is selected under software control using the SIDETONE bit as
shown in Table 11. In true side tone the output from the DAC (DACSEL) and line inputs (BYPASS)
should be deselected from the line output block. However, this can also be used to sum the DAC
output, line inputs and microphone inputs together. The microphone boost gain control and
headphone output volume control and mutes are still operational in side tone mode. The maximum
signal at any point in the side tone path must be no greater than 1.0V rms at VDD = 3.3V, to avoid
distortion. This amplitude tracks linearly with AVDD.
DEVICE OPERATION
DEVICE RESETTING
The WM8731/L contains a power on reset circuit that resets the internal state of the device to a
known condition. The power on reset is applied as DCVDD powers on and released only after the
voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum
turn on threshold voltage then the power on reset is re-applied. The threshold voltages and
associated hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
BIT
LABEL
RESET
DEFAULT
DESCRIPTION
0001111
Reset Register
8:0
not reset
Reset Register
Writing 00000000 to register resets
device
Table 12 Software Control of Reset
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 34).
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. To allow WM8731/L to be used in a centrally clocked system, the WM8731/L is capable
of either generating this system clock itself or receiving it from an external source as will be
discussed.
For applications where it is desirable that the WM8731/L is the system clock source, then clock
generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input
and XTO output pins (see CRYSTAL OSCILLATOR section).
For applications where a component other than the WM8731/L will generate the reference clock, the
external system can be applied directly through the XTI/MCLK input pin with no software configuration
necessary. Note that in this situation, the oscillator circuit of the WM8731/L can be safely powered
down to conserve power (see POWER DOWN section).
CORE CLOCK
The WM8731/L DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 13 below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
6
CLKIDIV2
0
Core Clock divider select
Sampling
Control
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
Table 13 Software Control of Core Clock
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
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CRYSTAL OSCILLATOR
The WM8731/L includes a crystal oscillator circuit that allows the audio system’s reference clock to be
generated on the device. This is available to the rest of the audio system in buffered form on
CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application
circuit is shown in Figure 25.
XTI/MCLK
XTO
Cp
Cp
DGND
DGND
Figure 25 Crystal Oscillator Application Circuit
The WM8731/L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a
requirement for high quality audio ADC and DACs, regardless of the converter architecture. The
WM8731/L architecture is less susceptible than most converter techniques but still requires clocks
with less than approximately 1ns of jitter to maintain performance. In applications where there is more
than one source for the master clock, it is recommended that the clock is generated by the WM8731/L
to minimise such problems.
CLOCKOUT
The Core Clock is internally buffered and made available externally to the audio system on the
CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for
driving external loads.
There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will
inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to
Electrical Characteristics.
CLKOUT can also be divided by 2 under software control, refer to Table 14. Note that if CLKOUT is
not required then the CLKOUT buffer on the WM8731/L can be safely powered down to conserve
power (see POWER DOWN section). If the system architect has the choice between using FCLKOUT
=
FMCLK or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the
divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical
Characteristics for timing information.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
7
CLKODIV2
0
CLKOUT divider select
Sampling
Control
1 = CLOCKOUT is Core Clock
divided by 2
0 = CLOCKOUT is Core Clock
Table 14 Programming CLKOUT
CLKOUT is disabled and set low whenever the device is in reset.
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DIGITAL AUDIO INTERFACES
WM8731/L may be operated in either one of the 4 offered audio interface modes. These are:
Right justified
Left justified
I2S
DSP mode
All four of these modes are MSB first and operate with data 16 to 32 bits.
Note that 32 bit data is not supported in right justified mode.
The digital audio interface takes the data from the internal ADC digital filter and places it on the
ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital
filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls
whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are
synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. BCLK maybe an input or an output dependent on whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section
The digital audio interface also receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether
Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DACDAT is
always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in
master or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8731/L. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR
or DACLRC transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DACDAT/
ADCDAT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 26 Left Justified Mode
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC or
ADCLRC transition.
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1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
1 BCLK
1 BCLK
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 27 I2S Mode
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC
or ADCLRC transition, yet MSB is still transmitted first.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 28 Right Justified Mode
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately
follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be
unused BCLK cycles between the LSB of the right channel data and the next sample.
Figure 29 DSP/PCM Mode Audio Interface (mode A, LRP=1)
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Figure 30 DSP/PCM Mode Audio Interface (mode B, LRP=0)
In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure
26, Figure 27, Figure 28, Figure 29 and Figure 30.
Operating the digital audio interface in DSP mode allows ease of use for supporting the various
sample rates and word lengths. The only requirement is that all data is transferred within the correct
number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
I2S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space
ratios need more careful consideration.
In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio.
BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for
each DACLRC/ADCLRC transition to clock the chosen data word length. The non-50:50 requirement
on the LRCs is of use in some situations such as with a USB 12MHZ clock. Here simply dividing
down a 12MHz clock within the DSP to generate LRCs and BCLK will not generate the appropriate
DACLRC or ADCLRC since they will no longer change on the falling edge of BCLK. For example,
with 12MHz/32k fs mode there are 375 MCLK per LRC. In these situations DACLRC/ADCLRC can be
made non 50:50.
In Master mode, DACLRC and ADCLRC will be output with a 50:50 mark-space ratio with BCLK
output at 64 x base frequency (i.e. 48 kHz).. The exception again is in USB mode where BCLK is
always 12MHz. So for example in 12MHz/32k fs mode there are 375 master clocks per DACLRC
period. Therefore DACLRC and ADCLRC outputs will have a mark space ratio of 187:188.
The ADC and DAC digital audio interface modes are software configurable as indicated in Table 14.
Note that dynamically changing the software format may result in erroneous operation of the
interfaces and is therefore not recommended.
The length of the digital audio data is programmable at 16/20/24 or 32 bits, in I2S or left justified
modes only. Refer to the software control table below. The data is signed 2’s complement. Both ADC
and DAC are fixed at the same data length. The ADC and DAC digital filters process data using 24
bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data.
If the ADC is programmed to output 32 bits then it packs the LSBs with zeros. If the DAC is
programmed to receive 16 or 20 bit data, the WM8731/L packs the LSBs with zeros. If the DAC is
programmed to receive 32 bit data, then it strips the LSBs.
The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in Table
15. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the
order so that a Left sample goes to the right DAC output and a Right sample goes to the left DAC
output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the
correct channel phase difference.
To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is
controlled vias the software shown in Table 15. This is especially appropriate for DSP mode.
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ADCDAT lines are always outputs. They power up and return from standby low.
DACDAT is always an input. It is expected to be set low by the audio interface controller when the
WM8731/L is powered off or in standby.
ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is
configured as a master or slave. If the device is a master then the DACLRC and BCLK signals are
outputs that default low. If the device is a slave then the DACLRC and BCLK are inputs. It is expected
that these are set low by the audio interface controller when the WM8731/L is powered off or in
standby.
REGISTER
ADDRESS
BIT
1:0
LABEL
DEFAULT
10
DESCRIPTION
0000111
FORMAT[1:0]
Audio Data Format Select
Digital Audio
Interface
Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
3:2
IWL[1:0]
10
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right
or I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising
edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising
edge
5
6
7
LRSWAP
MS
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
Table 15 Digital Audio Interface Control
Note: If right justified 32 bit mode is selected then the WM8731/L defaults to 24 bits.
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MASTER AND SLAVE MODE OPERATION
The WM8731/L can be configured as either a master or slave mode device. As a master mode device
the WM8731/L controls sequencing of the data and clocks on the digital audio interface. As a slave
device the WM8731/L responds with data to the clocks it receives over the digital audio interface. The
mode is set with the MS bit of the control register as shown in Table 16.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
6
MS
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Digital Audio Interface
Format
Table 16 Programming Master/Slave Modes
As a master mode device the WM8731/L controls the sequencing of data transfer (ADCDAT,
DACDAT) and output of clocks (BCLK, ADCLRC, DACLRC) over the digital audio interface. It uses
the timing generated from either its on-board crystal or the MCLK input as the reference for the clock
and data transitions. This is illustrated in Figure 31. ADCDAT is always an output from and DACDAT
is always an input to the WM8731/L independent of master or slave mode.
BCLK
ADCLRC
DSP
WM8731
CODEC
ENCODER/
DECODER
DACLRC
ADCDAT
DACDAT
Note: ADC and DAC can run at different rates
Figure 31 Master Mode
As a slave device the WM8731/L sequences the data transfer (ADCDAT, DACDAT) over the digital
audio interface in response to the external applied clocks (BCLK, ADCLRC, DACLRC). This is
illustrated in Figure 32.
BCLK
ADCLRC
DSP
WM8731
CODEC
ENCODER/
DECODER
DACLRC
ADCDAT
DACDAT
Note: The ADC and DAC can run at different rates
Figure 32 Slave Mode
Note that the WM8731/L relies on controlled phase relationships between audio interface BCLK,
DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section
for detailed information.
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AUDIO DATA SAMPLING RATES
The WM8731/L provides for two modes of operation (normal and USB) to generate the required DAC
and ADC sampling rates. Normal and USB modes are programmed under software control according
to the table below.
In Normal mode, the user controls the sample rate by using an appropriate MCLK or crystal frequency
and the sample rate control register setting. The WM8731/L can support sample rates from 8ks/s up
to 96ks/s.
In USB mode, the user must use a fixed MLCK or crystal frequency of 12MHz to generate sample
rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock
is at 12MHz and the WM8731/L can be directly used within such systems. WM8731/L can generate
all the normal audio sample rates from this one Master Clock frequency, removing the need for
different master clocks or PLL circuits.
Uniquely, the WM8731/L offers the user the ability to sample the ADC and DAC at different rates
under software control in both Normal and USB modes. This reduces the burden on any controlling
DSP. However, the signal processing in the ADC and DAC over-sampling filters is tightly coupled
together in order to minimise power consumption. To this end, only the combinations of sample rates
listed in the following sections are supported. Note that these rates supported are anticipated to be
the likely combinations used in typical audio systems.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
0
USB/
0
Mode Select
NORMAL
BOSR
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
1
0
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
96/88.2kHz
0 = 256fs
0 = 128fs
1 = 384fs
1 = 192fs
5:2
SR[3:0]
0000
ADC and DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Table 17 Sample Rate Control
NORMAL MODE SAMPLE RATES
In normal mode MCLK/crystal oscillator is set up according to the desired sample rates of the ADC
and DAC. For ADC or DAC sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either
12.288MHz (256fs) or 18.432MHz (384fs) can be used. For ADC or DAC sampling rates of 8, 44.1 or
88.2kHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.
Table 18 should be used to set up the device to work with the various sample rate combinations. For
example if the user wishes to use the WM8731/L in normal mode with the ADC and DAC sample
rates at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 =
0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1, SR3 = 0, SR2 = 0, SR1
= 0 and SR0 = 0 with a 18.432MHz MCLK. The ADC and DAC will then operate with a Digital Filter of
type 1, refer to Digital Filter Characteristics section for an explanation of the different filter types.
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SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
kHz
48
kHz
MHz
BOSR
SR3
0
SR2
0
SR1
0
SR0
0
48
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (128fs)
1 (192fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (256fs)
1 (384fs)
0 (128fs)
1 (192fs)
1
1
1
1
1
2
1
1
1
1
2
0
0
0
0
48
8
8
48
8
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
8
0
0
1
1
0
0
1
1
32
96
44.1
44.1
8
32
96
44.1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
8
1
0
0
1
(Note 1)
44.1
1
0
0
1
1
0
1
0
(Note 1)
8
1
0
1
0
8
1
0
1
1
(Note 1) (Note 1)
88.2 88.2
1
0
1
1
1
1
1
1
1
1
1
1
Table 18 Normal Mode Sample Rate Look-up Table
Notes:
1. 8k not exact, actual = 8.018kHz
2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital
signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at
256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the
actual audio data rate produced by the ADC and required by the DAC.
Example scenarios are:
1. with a requirement that the ADC data rate is 8kHz and DAC data rate is 48kHz, then choosing
MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1
= 1, SR0 = 0.The ADC output data rate will then be exactly 8kHz (derived from 12.288MHz/256
x1/6) and the DAC expects data at exactly 48kHz (derived from 12.288MHz/256)
2. with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz, then choosing
MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1
= 1, SR0 = 0. The ADC will no longer output data at exactly 8.000kHz, instead it will be 8.018kHz
(derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1kHz (derived from
16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio data and
(importantly) the user must ensure that the data across the digital interface is correctly
synchronised at the 8.018kHz rate.
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The exact sample rates achieved are defined by the relationships in Table 19 below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
MCLK=11.2896
kHz
BOSR=1
MCLK=12.288
MCLK=18.432
kHz
MCLK=16.9344
kHz
kHz
kHz
8
8
8.018
8
8.018
(12.288MHz/256) x 1/6
32
(11.2896MHz/256) x 2/11
not available
(18.432MHz/384) x 1/6
32
(16.9344MHz/384) x 2/11
not available
32
44.1
48
(12.288MHz/256) x 2/3
not available
(18.432MHz/384) x 2/3
not available
44.1
44.1
11.2896MHz/256
not available
16.9344MHz /384
not available
48
48
12.288MHz/256
not available
18.432MHz/384
not available
88.2
96
88.2
88.2
(11.2896MHz/256) x 2
not available
(16.9344MHz /384) x 2
not available
96
96
(12.288MHz/256) x 2
(18.432MHz/384) x 2
Table 19 Normal Mode Actual Sample Rates
128/192fs NORMAL MODE
The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the
WM8731/L is also capable of being clocked from a 128 or 192fs MCLK for application over limited
sampling rates as shown in the table below.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
kHz
48
kHz
MHz
6.144
9.216
5.6448
8.4672
BOSR
SR3
SR2
SR1
SR0
48
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
44.1
44.1
Table 20 128fs Normal Mode Sample Rate Look-up Table
512/768fs NORMAL MODE
512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bit (Register 8, bit 6).
The core clock to the DSP will be divided by 2 so an external 512/768 fs MCLK will become 256/384
fs internally and the device otherwise operates as in Table 18 but with MCLK at twice the specified
rate. See Table 17 for software control.
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USB MODE SAMPLE RATES
In USB mode the MCLK/crystal oscillator input is 12MHz only.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
kHz
48
kHz
MHz
BOSR
SR3
SR2
SR1
SR0
48
12.000
0
0
0
0
0
0
1
0
1
0
1
0
1
0
3
2
44.1
44.1
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
1
1
(Note 2) (Note 2)
48
8
44.1
8
(Note 2) (Note 1)
8
48
8
44.1
((Note 1) (Note 2)
8
8
8
8
(Note 1) (Note 1)
32
32
96
96
88.2
88.2
(Note 3) (Note 3)
Table 21 USB Mode Sample Rate Look-up Table
Notes:
1. 8k not exact, actual = 8.021kHz
2. 44.1k not exact, actual = 44.118kHz
3. 88.2k not exact, actual = 88.235kHz
4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The table above can be used to set up the device to work with various sample rate combinations. For
example if the user wishes to use the WM8731/L in USB mode with the ADC and DAC sample rates
at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0,
SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0,
refer to Digital Filter Characteristics section for an explanation of the different filter types.
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital
signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB
mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base over-
sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate
produced by the ADC and required by the DAC.
Example scenarios are, :-
1. with a requirement that the ADC data sampling rate is 8kHz and DAC data sampling rate is
48kHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 =
0.The ADC will then be exactly 8kHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects
data at exactly 48kHz ( derived from 12MHz/250 ).
2. with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz the device is
programmed with BOSR = 1 (272fs), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not
output data at exactly 8kHz, instead it will be 8.021kHz ( derived from 12MHz/272 x 2/11 ) and
the DAC at 44.118kHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore
results in the 8kHz and 44.1kHz audio data and (more importantly) the user must ensure that
the data across the digital interface is correctly synchronised at the 8.021kHz and 44.117kHz
rates.
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The exact sample rates supported for all combinations are defined by the relationships in Table 22
below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
BOSR=1
(272fs)
( 250fs)
kHz
kHz
kHz
8
8
8.021
12MHz/(250 x 48/8)
32
12MHz/(272 x 11/2)
not available
32
44.1
48
12MHz/(250 x 48/32)
not available
44.117
12MHz/272
48
not available
12MHz/250
88.2
96
not available
88.235
12MHz/136
96
not available
12MHz/125
Table 22 USB Mode Actual Sample Rates
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface the Audio
Interface is disabled (tristate with weak 100k pulldown). Once the Audio Interface and the Sampling
Control has been programmed it is activated by setting the ACTIVE bit under Software Control.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001001
Active Control
0
ACTIVE
0
Activate Interface
1 = Active
0 = Inactive
Table 23 Activating DSP and Digital Audio Interface
It is recommended that between changing any content of Digital Audio Interface or Sampling Control
Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire (SPI-compatible) or 2-wire MPU
interface. Selection of interface format is achieved by setting the state of the MODE pin.
In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and
CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is
used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two
addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved
by setting the state of the MODE pin.
MODE
INTERFACE
FORMAT
0
1
2 wire
3 wire
Table 24 Control Interface Mode Selection
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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8731/L can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 33.
CSB
SCLK
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SDIN
Figure 33 3-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
3. CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB.
2-WIRE SERIAL CONTROL MODE
The WM8731/L supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8731/L has one of two slave addresses that are selected by setting the state of pin 15,
(CSB).
ACK
ACK
ACK
DATA B15-8
R ADDR
R/W
DATA B7-0
SDIN
SCLK
START
STOP
Figure 34 2-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
CSB STATE
ADDRESS
0
1
0011010
0011011
Table 25 2-Wire MPU Interface Address Selection
To control the WM8731/L on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see Table 24). If the correct address is received and the R/W
bit is ‘0’, indicating a write, then the WM8731/L will respond by pulling SDIN low on the next clock
pulse (ACK). The WM8731/L is a write only device and will only respond to the R/W bit indicating a
write. If the address is not recognised the device will return to the idle condition and wait for a new
start condition and valid address.
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Once the WM8731/L has acknowledged a correct address, the controller will send eight data bits (bits
B15-B8). WM8731/L will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B7-B0) and the WM8731/L will then
acknowledge again by pulling SDIN low.
A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start
or stop condition is detected out of sequence at any point in the data transfer then the device will
jump to the idle condition.
After receiving a complete address and data sequence the WM8731/L returns to the idle state and
waits for another start condition. Each write to a register requires the complete sequence of start
condition, device address and R/W bit followed by the 16 register address and data bits.
POWER DOWN MODES
The WM8731/L contains power conservation modes in which various circuit blocks may be safely
powered down in order to conserve power. This is software programmable as shown in the table
below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000110
0
1
LINEINPD
1
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
Power Down
Control
MICPD
1
Microphone Input an Bias
Power Down
1 = Enable Power Down
0 = Disable Power Down
ADC Power Down
2
3
4
5
6
7
ADCPD
1
1
1
0
0
1
1 = Enable Power Down
0 = Disable Power Down
DAC Power Down
DACPD
1 = Enable Power Down
0 = Disable Power Down
Line Output Power Down
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
CLKOUT power down
1 = Enable Power Down
0 = Disable Power Down
Power Off Device
OUTPD
OSCPD
CLKOUTPD
POWEROFF
1 = Device Power Off
0 = Device Power On
Table 26 Power Conservation Modes Software Control
The power down control can be used to either a) permanently disable functions when not required in
certain applications or b) to dynamically power up and down functions depending on the operating
mode, e.g.: during playback or record. Please follow the special instructions below if dynamic
implementations are being used.
LINEINPD: Simultaneously powers down both the Line Inputs. This can be done dynamically without
any audible effects either on the ADC or to the Line Outputs in Bypass mode. This is of use when the
device enters Playback, Pause or Stop modes or the Microphone input has been selected.
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MICPD: Simultaneously powers down both the Microphone Input and Microphone Bias. If this is done
dynamically, audible pops through the ADC will result. This will only be audible if the Microphone
Input is selected to the ADC at the time. If the state of MICPD is changed then the controlling DSP or
microprocessor should switch to select the Line Inputs as input to the ADC (INSEL) before changing
MICPD. This is of use when the device enters Playback, Pause or Stop modes or the Microphone
Input is not selected.
ADCPD: Powers down the ADC and ADC Filters. If this is done dynamically then audible pops will
result if any signals were present through the ADC. To overcome this whenever the ADC is to be
powered down, either mute the Microphone Input (MUTEIN) or MUTELINEIN, then change ADCPD.
This is of use when the device enters Playback, Pause or Stop modes regardless of whether
Microphone or Line Inputs are selected.
DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops
will result unless the following guidelines are followed. In order to prevent pops, the DAC should first
be soft-muted (DACMU), the output should then be de-selected from the line and headphone output
(DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Record,
Pause, Stop or Bypass modes.
OUTPD: Powers down the Line and Headphone outputs. If this is done dynamically then audible pops
may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters
Record, Pause or Stop modes.
OSCPD: Powers off the on board crystal oscillator. The MCLK input will function independently of the
Oscillator being powered down.
CLKOUTPD: Powers down the CLOCKOUT pin. This conserves power, reduces digital noise and RF
emissions if not required. CLKOUT is tied low when powered down.
The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry
under software control as shown in Table 27. If the crystal oscillator and/or CLOKOUT pins are being
used to derive the system master clock, these should probably never be powered off in standby.
Provision has been made to independently power off these areas according to Table 27.
DESCRIPTION
STANDBY, but with Crystal
Oscillator OS and CLKOUT
available
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
STANDBY, but with Crystal
Oscillator OS available,
CLKOUT not-available
STANDBY, Crystal
oscillator and CLKOUT not-
available.
Table 27 Standby Mode
In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue
circuitry remain active. The active analogue includes the analogue VMID reference so that the
analogue line inputs, line outputs and headphone outputs remain biased to VMID. This reduces any
audible effects caused by DC glitches when entering or leaving STANDBY mode.
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The device can be powered off by writing to the POWEROFF bit of the Power Down register. In
POWEROFF mode the Control Interface and a small portion of the digital remain active. The
analogue VMID reference is disabled. As in STANDBY mode the crystal oscillator and/or CLKOUT pin
can be independently controlled. Refer to Table 28.
DESCRIPTION
POWEROFF, but with Crystal
Oscillator OS and CLKOUT
available
1
1
1
0
1
1
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
POWEROFF, but with Crystal
Oscillator OS available, CLKOUT
not-available
POWEROFF, Crystal oscillator
and CLKOUT not-available.
Table 28 Poweroff Mode
REGISTER MAP
The complete register map is shown in Table 29. The detailed description can be found in Table 30
and in the relevant text of the device description. There are 11 registers with 16 bits per register (7 bit
address + 9 bits of data). These can be controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
BIT[8]
BIT[7]
BIT[6]
BIT[5]
BIT[4]
BIT[3]
BIT[2]
BIT[1]
BIT[0]
DEFAULT
R0 (00h)
LRINBOTH
LINMUTE
0
0
LINVOL[4:0]
0_1001_0111
Left Line In
R1 (01h)
Right Line In
RLINBOTH
LRHPBOTH
RINMUTE
LZCEN
0
0
RINVOL[4:0]
0_1001_0111
0_0111_1001
R2 (02h)
Left
Headphone Out
LHPVOL[6:0]
RHPVOL[6:0]
BYPASS
R1 (01h)
Right
Headphone Out
RLHPBOTH
RZCEN
0_0111_1001
0_0000_1010
0_0000_1000
0_1001_1111
0_1001_1111
0_0000_0000
0_0000_0000
not reset
R4 (04h)
Analogue Audio
Path Control
0
0
0
0
0
0
SIDEATT[1:0]
SIDETONE
0
DACSEL
HPOR
OUTPD
LRP
INSEL
MUTEMIC
MICPD
MICBOOST
ADCHPD
R5 (05h)
Digital Audio
Path Control
0
0
DACMU
DEEMPH[1:0]
R6 (06h)
Power Down
Control
POWEROFF CLKOUTPD
OSCPD
LRSWAP
DACPD
ADCPD
LINEINPD
R7 (07h)
Digital Audio
Interface Format
BCLKINV
CLKODIV2
0
MS
CLKIDIV2
0
IWL[1:0]
FORMAT[1:0]
R8 (08h)
Sampling
Control
SR[3:0]
BOSR
0
USB/
NORMAL
R9 (09h)
Active Control
0
0
0
0
Active
R15 (0Fh)
RESET[8:0]
Reset
Table 29 Register Map
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000000
4:0
LINVOL[4:0]
10111
( 0dB )
Left Channel Line Input Volume
Control
Left Line In
11111 = +12dB . . 1.5dB steps down
to 00000 = -34.5dB
7
8
LINMUTE
1
0
Left Channel Line Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
LRINBOTH
Left to Right Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
LINVOL[4:0] and LINMUTE to
RINVOL[4:0] and RINMUTE
0 = Disable Simultaneous Load
0000001
4:0
7
RINVOL[4:0]
RINMUTE
10111
( 0dB )
Right Channel Line Input Volume
Control
Right Line In
11111 = +12dB . .1.5dB steps down
to 00000 = -34.5dB
1
0
Right Channel Line Input Mute to
ADC
1 = Enable Mute
0 = Disable Mute
8
RLINBOTH
Right to Left Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
RINVOL[4:0] and RINMUTE to
LINVOL[4:0] and LINMUTE
0 = Disable Simultaneous Load
0000010
6:0
LHPVOL
[6:0]
1111001
( 0dB )
Left Channel Headphone Output
Volume Control
Left Headphone
Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
LZCEN
0
0
Left Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
LRHPBOTH
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
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DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
0000011
6:0
RHPVOL
[6:0]
1111001
( 0dB )
Right Channel Headphone Output
Volume Control
Right
Headphone Out
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
7
8
RZCEN
0
0
Right Channel Zero Cross detect
Enable
1 = Enable
0 = Disable
RLHPBOTH
Right to Left Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
RHPVOL[6:0] and RZCEN to
LHPVOL[6:0] and LZCEN
0 = Disable Simultaneous Load
Microphone Input Level Boost
1 = Enable Boost
0000100
0
MICBOOST
MUTEMIC
INSEL
0
Analogue Audio
Path Control
0 = Disable Boost
1
1
Mic Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
2
0
Microphone/Line Input Select to ADC
1 = Microphone Input Select to ADC
0 = Line Input Select to ADC
Bypass Switch
3
BYPASS
1
1 = Enable Bypass
0 = Disable Bypass
DAC Select
4
DACSEL
0
1 =Select DAC
0 = Don’t select DAC
Side Tone Switch
5
SIDETONE
SIDEATT[1:0]
0
1 = Enable Side Tone
0 = Disable Side Tone
Side Tone Attenuation
11 = -15dB
7:6
00
10 = -12dB
01 = -9dB
00 = -6dB
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DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
0000101
0
ADCHPD
0
ADC High Pass Filter Enable
1 = Disable High Pass Filter
0 = Enable High Pass Filter
De-emphasis Control
11 = 48kHz
Digital Audio
Path Control
2:1
DEEMP[1:0]
00
10 = 44.1kHz
01 = 32kHz
00 = Disable
3
4
DACMU
HPOR
1
0
DAC Soft Mute Control
1 = Enable soft mute
0 = Disable soft mute
Store dc offset when High Pass Filter
disabled
1 = store offset
0 = clear offset
0000110
0
1
LINEINPD
MICPD
1
1
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
Power Down
Control
Microphone Input an Bias Power
Down
1 = Enable Power Down
0 = Disable Power Down
ADC Power Down
2
3
4
5
6
7
ADCPD
1
1
1
0
0
1
1 = Enable Power Down
0 = Disable Power Down
DAC Power Down
DACPD
1 = Enable Power Down
0 = Disable Power Down
Outputs Power Down
1 = Enable Power Down
0 = Disable Power Down
Oscillator Power Down
1 = Enable Power Down
0 = Disable Power Down
CLKOUT power down
1 = Enable Power Down
0 = Disable Power Down
POWEROFF mode
OUTPD
OSCPD
CLKOUTPD
POWEROFF
1 = Enable POWEROFF
0 = Disable POWEROFF
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DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
0000111
1:0
FORMAT[1:0]
10
Audio Data Format Select
Digital Audio
Interface Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
Input Audio Data Bit Length Select
11 = 32 bits
3:2
IWL[1:0]
10
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right
or I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising edge
5
6
7
0
1
LRSWAP
MS
0
0
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
0001000
USB/
NORMAL
Mode Select
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
BOSR
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
0 = 256fs
1 = 384fs
5:2
6
SR[3:0]
0000
0
ADC and DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
CLKIDIV2
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
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DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
7
CLKODIV2
0
CLKOUT divider select
1 = CLOCKOUT is Core Clock
divided by 2
0 = CLOCKOUT is Core Clock
Activate Interface
1 = Active
0001001
0
ACTIVE
RESET
0
Active Control
0 = Inactive
0001111
8:0
not reset
Reset Register
Reset Register
Writing 00000000 to register resets
device
Table 30 Register Map Description
DIGITAL FILTER CHARACTERISTICS
The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2
and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is
shown in the proceeding pages.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Filter Type 0 (USB Mode, 250fs operation)
Passband
+/- 0.05dB
-6dB
0
0.416fs
+/- 0.05
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-60
Stopband Attenuation
f > 0.584fs
ADC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.05dB
-6dB
0
0.4535fs
+/- 0.05
0.5fs
Passband Ripple
Stopband
dB
0.5465fs
-60
Stopband Attenuation
f > 0.5465fs
-3dB
dB
Hz
High Pass Filter Corner
Frequency
3.7
-0.5dB
10.4
-0.1dB
21.6
DAC Filter Type 0 (USB mode, 250fs operation)
Passband
+/- 0.03dB
-6dB
0
0.416fs
+/-0.03
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-50
Stopband Attenuation
f > 0.584fs
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.03dB
-6dB
0
0.4535fs
+/- 0.03
0.5fs
Passband Ripple
Stopband
dB
dB
0.5465fs
-50
Stopband Attenuation
f > 0.5465fs
Table 31 Digital Filter Characteristics
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DAC FILTERS
ADC FILTERS
Group Delay
Mode
Group Delay
Mode
0
1
2
3
11/FS
18/FS
5/FS
0
1
2
3
12/FS
20/FS
3/FS
5/FS
6/FS
Table 32 ADC/DAC Digital Filters Group Delay
TERMINOLOGY
1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
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DAC FILTER RESPONSES
0.04
0.03
0.02
0.01
0
0
-20
-40
-60
-0.01
-0.02
-0.03
-0.04
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.4
0.2
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 35 DAC Digital Filter Frequency Response –Type 0
Figure 36 DAC Digital Filter Ripple –Type 0
0.04
0.03
0.02
0.01
0
0
-20
-40
-60
-0.01
-0.02
-0.03
-0.04
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 37 DAC Digital Filter Frequency Response –Type 1
Figure 38 DAC Digital Filter Ripple –Type 1
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.25
Frequency (Fs)
Frequency (Fs)
Figure 39 DAC Digital Filter Frequency Response –Type 2
Figure 40 DAC Digital Filter Ripple –Type 2
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0
0.05
0
-20
-40
-0.05
-0.1
-0.15
-0.2
-0.25
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 41 DAC Digital Filter Frequency Response –Type 3
Figure 42 DAC Digital Filter Ripple –Type 3
ADC FILTER RESPONSES
0.02
0.01
0
0
-20
-40
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 43 ADC Digital Filter Frequency Response –Type 0
Figure 44 ADC Digital Filter Ripple –Type 0
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 45 ADC Digital Filter Frequency Response –Type 1
Figure 46 ADC Digital Filter Ripple –Type 1
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0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 47 ADC Digital Filter Frequency Response –Type 2
Figure 48 ADC Digital Filter Ripple –Type 2
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 49 ADC Digital Filter Frequency Response –Type 3
Figure 50 ADC Digital Filter Ripple –Type 3
ADC HIGH PASS FILTER
The WM8731/L has a selectable digital high pass filter to remove DC offsets. The filter response is
characterised by the following polynomial.
H(z) =
1 – z-1
1 – 0.9995 z-1
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
2000
4000
6000
8000
10000 12000 14000 16000
0
2000
4000
6000
8000
10000 12000 14000 16000
Frequency (Fs)
Frequency (Fs)
Figure 51 De-Emphasis Frequency Response (32kHz)
Figure 52 De-Emphasis Error (32kHz)
0
-2
0.4
0.3
0.2
0.1
0
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5000
10000
Frequency (Fs)
15000
20000
0
5000
10000
Frequency (Fs)
15000
20000
Figure 53 De-Emphasis Frequency Response (44.1kHz)
Figure 54 De-Emphasis Error (44.1kHz)
0
-2
0.4
0.3
0.2
0.1
0
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5000
10000
15000
20000
0
5000
10000
15000
20000
Frequency (Fs)
Frequency (Fs)
Figure 55 De-Emphasis Frequency Response (48kHz)
Figure 56 De-Emphasis Error (48kHz)
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 57 External Components Diagram
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MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS
To minimise any pop or click noise when the system is powered up or down, the following procedures
are recommended.
POWER UP SEQUENCE
Switch on power supplies. By default the WM8731 is in Standby Mode, the DAC is
digitally muted and the Audio Interface and Outputs are all OFF.
Set all required bits in the Power Down register (0Ch) to ‘0’; EXCEPT the OUTPD bit,
this should be set to ‘1’ (Default).
Set required values in all other registers except 12h (Active).
Set the ‘Active’ bit in register 12h.
The last write of the sequence should be setting OUTPD to ‘0’ (active) in register
0Ch, enabling the DAC signal path, free of any significant power-up noise.
POWER DOWN SEQUENCE
Set the OUTPD bit to ‘1’ (power down).
Remove the WM8731 supplies.
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PACKAGE DIMENSIONS - SSOP
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)
DM007.E
b
e
28
15
E1
E
GAUGE
PLANE
14
1
D
0.25
L
c
A1
L1
A
A2
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
A
A1
A2
b
c
D
e
E
E1
L
2.0
0.25
1.85
0.38
0.25
10.50
0.05
1.65
0.22
0.09
9.90
-----
1.75
0.30
-----
10.20
0.65 BSC
7.80
7.40
5.00
0.55
8.20
5.60
0.95
5.30
0.75
L1
1.25 REF
0o
4o
8o
JEDEC.95, MO-150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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Production Data
PACKAGE DIMENSIONS - QFN
FL: 28 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.85 mm BODY, 0.50 mm LEAD PITCH
DM109.A
D2
0.10
C
A
B
B
D2/2
27 28
D
22
INDEX AREA
(D/2 X E/2)
L
21
1
2
EXPOSED
GROUND
PADDLE
6
E2/2
A
A
E2
E
15
7
SEE DETAIL A
aaa
C
14 13
e
8
2 X
2 X
b
M
A
ccc
C
B
B
aaa
C
TOP VIEW
BOTTOM VIEW
0.10
C
(A3)
1
DETAIL A
A
0.08
C
A1
SEATING PLANE
C
SIDE VIEW
Dimensions (mm)
Symbols
MIN
0.80
0
NOM
0.85
MAX
0.90
0.05
NOTE
A
A1
A3
b
0.035
0.203 REF
0.25
0.20
3.00
3.00
0.30
3.20
3.20
0.60
1
2
2
2
D
5.00 BSC
3.10
D2
E
5.00 BSC
3.10
E2
e
0.5 BSC
0.55
L
0.50
R
b(min)/2
Tolerances of Form and Position
aaa
0.10
0.10
bbb
ccc
0.10
JEDEC, MO-220, VARIATION VHHD-3
REF:
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2 AND L:
D2,E2: SMALLER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION, L IS SLIGHTLY LARGER THAN JEDEC SPEC.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY.
6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
PD, Rev 4.9, October 2012
63
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WM8731 / WM8731L
IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
PD, Rev 4.9, October 2012
64
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WM8731 / WM8731L
REVISION HISTORY
Production Data
DATE
REV
ORIGINATOR
CHANGES
and WM8731LSELF/R
15/05/12
4.9
JMacD
Order
Code
WM8731LSEFL
changed
to
WM8731CLSEFL and WM8731CLSEFL/R to reflect change to copper wire
bonding.
15/05/12
23/07/12
4.9
4.9
JMacD
JMacD
QFN Package Diagram changed to DM109.A
Order Code WM8731SEFL and WM8731SEFL/R changed to WM8731CSEFL
and WM8731CSEFL/R to reflect change to copper wire bonding.
PD, Rev 4.9, October 2012
65
w
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