WM8785 [WOLFSON]
24-Bit, 192kHz Stereo ADC; 24位， 192kHz立体声ADC
| 型号： | WM8785 |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 24-Bit, 192kHz Stereo ADC |
| 文件： | 总31页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8785
w
24-Bit, 192kHz Stereo ADC
DESCRIPTION
FEATURES
•
•
•
•
•
•
SNR 111dB (‘A’ weighted @ 48kHz)
THD -102dB (at -0.1dB)
Sampling Frequency: 8 – 192kHz
2 or 3 Wire Microprocessor Control Interface
Master or Slave Clocking Mode
The WM8785 is a stereo audio ADC with differential inputs
designed for high performance recordable media applications.
Data is provided as a PCM output.
Stereo 24-bit multi-bit sigma-delta ADCs are used with digital
audio output word lengths of 16 to 32 bits, and sampling rates
from 8kHz to 192kHz. The device has a selectable high pass
filter to remove residual DC offsets. The device also supports a
TDM bus for data out.
Programmable Audio Data Interface Modes
-
-
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
•
•
A TDM bus is supported for data out
Supply Voltages
The device is controlled via a 2 or 3 wire serial interface. The
interface provides access to all features including oversampling
rate, audio format, powerdown, master/slave control and digital
signal manipulation. The device is supplied in a 20-lead SSOP
package.
-
-
Analogue 4.5 to 5.5V
Digital core: 2.7V to 3.6V
•
20-lead SSOP package
APPLICATIONS
•
•
•
•
Recordable DVD Players
Personal Video Recorders
High End Sound Cards
Studio Audio Processing Equipment
BLOCK DIAGRAM
Pre-Production, December 2005, Rev 3.0
WOLFSON MICROELECTRONICS plc
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Copyright 2005 Wolfson Microelectronics plc
WM8785
Pre-Production
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
BLOCK DIAGRAM .................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY............................................................................................................ 7
SIGNAL TIMING REQUIREMENTS.......................................................................8
SYSTEM CLOCK TIMING ............................................................................................. 8
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA ...................................... 8
AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA ......................................... 9
CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 9
CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 10
POWER-ON RESET ................................................................................................... 11
DIGITAL FILTER CHARACTERISTICS...............................................................12
TERMINOLOGY.......................................................................................................... 12
FILTER RESPONSES..........................................................................................13
DEVICE DESCRIPTION.......................................................................................16
INTRODUCTION......................................................................................................... 16
DIGITAL AUDIO INTERFACE..................................................................................... 16
DIGITAL HIGH PASS.................................................................................................. 20
DATA OUT PIN DISABLE ........................................................................................... 21
CONTROL INTERFACE.............................................................................................. 21
TIME DIVISION MULTIPLEXED DATA OUT............................................................... 22
TDM SELECTION ....................................................................................................... 23
OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY.......... 26
MASTER CLOCK AND AUDIO SAMPLE RATES........................................................ 26
MLCK AND LRCLK PHASE RELATIONSHIP.............................................................. 27
POWER DOWN CONTROL........................................................................................ 27
REGISTER MAP ......................................................................................................... 28
APPLICATIONS INFORMATION .........................................................................29
RECOMMENDED EXTERNAL COMPONENTS.......................................................... 29
PACKAGE DIMENSIONS ....................................................................................30
IMPORTANT NOTICE..........................................................................................31
ADDRESS: .................................................................................................................. 31
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PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AINL+
AINR+
AINR-
VREF
AINL-
VREFGND
AVDD
VMID
DGND
AGND
DVDD
NC
LRCLK
DOUT
CSB
BCLK
SDIN
MCLK
SCLK
NC
ORDERING INFORMATION
ORDER CODE
WM8785GEDS/V
WM8785GEDS/RV
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
-25°C to +85°C
20-lead SSOP
(Pb-free)
MSL3
MSL3
260oC
-25°C to +85°C
20-lead SSOP
260oC
(Pb-free, tape and reel)
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
PIN
1
NAME
AINL+
AINL-
VREFGND
AVDD
AGND
LRCLK
DOUT
BCLK
MCLK
NC
TYPE
Analogue Input
Analogue Input
Analogue Reference
Supply
DESCRIPTION
Left Channel Positive Input
Left Channel Negative Input
2
3
Negative Reference Connection
Analogue Supply
4
5
Supply
Analogue Ground (return path for AVDD)
Audio Interface Left / Right Clock
ADC Digital Audio Data
6
Digital Input / Output
Digital Output
Digital Input / Output
Digital Input
7
8
Audio Interface Bit Clock
Master Clock
9
10
11
12
13
14
15
16
17
18
19
20
NC
No Connection
SCLK
SDIN
Digital Input
Control Interface Clock Input / 2 wire output
Control Interface Data Input
Digital Input / Output
Digital Input
CSB
Chip Select / Control Interface Format Selection / 3 wire address select
No connection
NC
NC
DVDD
DGND
VMID
Supply
Digital Supply
Supply
Digital Ground (return path for DVDD)
Midrail Voltage Decoupling Capacitor
Reference Voltage Decoupling Capacitor
Right Channel Negative Input
Analogue Output
Analogue Reference
Analogue Input
Analogue Input
VREF
AINR-
AINR+
Right Channel Positive Input
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+3.63V
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Master Clock Frequency
-0.3V
+7V
DGND -0.3V
AGND -0.3V
DVDD + 0.3V
AVDD +0.3V
40MHz
Operating temperature range, TA
-25°C
-65°C
+85°C
+150°C
Storage temperature after soldering
Note: Analogue and digital grounds must always be within 0.3V of each other.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
DVDD
TEST CONDITIONS
MIN
2.7
TYP
MAX
3.6
UNIT
Digital supply range
Analogue supply range
Ground
V
V
V
AVDD
4.5
5.5
DGND,AGND
0
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ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Performance
Full Scale Input Signal Level
(for ADC 0dB Input)
Input resistance
2.0
Vrms
10
10
kΩ
pF
dB
Input capacitance
Signal to Noise Ratio (Note
1,2,4)
SNR
A-weighted,
@ fs = 48kHz
Unweighted,
@ fs = 48kHz
A-weighted,
104
111
108
111
108
111
108
dB
dB
dB
dB
dB
Signal to Noise Ratio (Note
1,2,4)
SNR
SNR
THD
@ fs = 96kHz
Unweighted,
@ fs = 96kHz
A-weighted,
Signal to Noise Ratio (Note
1,2,4)
@ fs = 192kHz
Unweighted,
@ fs = 192kHz
Total Harmonic Distortion
Total Harmonic Distortion
1kHz, -0.1dB Full Scale
@ fs = 48kHz
-102
-102
dB
dB
dB
%
1kHz, -0.1dB Full Scale
@ fs = 96kHz
1kHz, -0.1dB Full Scale
@ fs = 192kHz
-102
THD
DNR
1kHz, -0.1dB Full Scale
@ fs = 48kHz
0.0008
0.0008
0.0008
1kHz, -0.1dB Full Scale
@ fs = 96kHz
%
1kHz, -0.1dB Full Scale
@ fs = 192kHz
%
Dynamic Range
-60dBFS
104
5
111
0.1
dB
dB
Channel Level Matching
Power Supply Rejection Ratio
20kHz signal
PSRR
1kHz 100mVpp, applied
to AVDD, DVDD
0 dB
20Hz to 20kHz
100mVpp
45
dB
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
0.3 x DVDD
+1
V
V
Input HIGH level
0.7 x DVDD
-1
Input leakage current
Input capacitance
Output LOW
0.2
5
µA
pF
V
VOL
VOH
I
OL=1mA
0.1 x DVDD
Output HIGH
I
OH= -1mA
0.9 x DVDD
V
Analogue Reference Levels
Midrail Reference Voltage
VMID
RVMID
VREF
AVDD to VMID and
VMID to VREFGND
–3%
5
AVDD/2
0 k
+3%
+3%
V
Ω
V
Potential Divider Resistance
Buffered Reference Voltage
AVDD to VMID and
VMID to GND
–3%
0.8 x AVDD
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Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
27
MAX
UNIT
mA
Supply Current
Analogue supply current
Digital supply current
Power Down
5
mA
22
uA
Note:
1. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce
performance.
TERMINOLOGY
1. Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the
digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these
results).
2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it.
(e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
5. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter, except
where noted. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than
are found in the Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible,
it may affect dynamic specification values
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock cycle time
MCLK duty cycle
T
MCnLKsY 25
TMCLKDS
60:40
40:60
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
DOUT propagation delay from BCLK falling edge
tDL
0
0
10
11
ns
ns
tDDA
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AUDIO INTERFACE TIMING – SLAVE MODE, PCM DATA
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY 25
ns
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
tLRSU
tLRH
tDD
10
10
0
ns
ns
ns
11
CONTROL INTERFACE TIMING – 3-WIRE MODE
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise
stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
tSCS
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
tps
80
200
80
80
40
40
40
40
40
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
6
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CONTROL INTERFACE TIMING – 2-WIRE MODE
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t9
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DVDD = 3.3V, DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise
stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
5
MHz 0
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
80
80
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
300
300
600
4
900
6
Pulse width of spikes that will be suppressed
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POWER-ON RESET
The WM8785 has an internal power-on reset circuit. The reset sequence is entered at power-on or
power-up (DVDD). Until the internal reset is removed, DOUT is forced to zero. DOUT remains zero
for a count equal to 32 sample clocks, after power up. (This count is driven by MCLK and is
independent of any external LRCLK).
Figure 6 POR Circuit
Figure 7 POR Timing
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DIGITAL FILTER CHARACTERISTICS
The WM8785 digital filter characteristics scale with sample rate.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.454fs
+/- 0.005
UNIT
ADC Sample Rate (Single Rate – 48KHz typically)
Passband
+/- 0.005dB
-6dB
0
0.5fs
Passband Ripple
Stopband
dB
0.546fs
-85
Stopband Attenuation
Group Delay
f > 0.546fs
dB
s
32/fs
0.5fs
ADC Sample Rate (Dual Rate - 96kHz typically)
Passband
+/- 0.005dB
0
0.454fs
-6dB
Passband Ripple
Stopband
+/- 0.005
dB
0.546fs
-85
Stopband Attenuation
Group Delay
f > 0.546fs
dB
s
32/fs
ADC Sample Rate (Quad Rate - 192kHz typically)
Passband
+/- 0.005dB
-3dB
0
0.25fs
0.45fs
0.5fs
-6dB
Passband Ripple
Stopband
+/- 0.005
dB
0.75
fs
Stopband Attenuation
Group Delay
f > 0.75fs
-85
dB
s
10/fs
3.7
High Pass Filter Corner
Frequency
-3dB
Hz
-0.5dB
10.4
-0.1dB
21.6
TERMINOLOGY
1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
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FILTER RESPONSES
SINGLE RATE 48k
0
-20
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (Fs)
Figure 8 Single Rate 48k Filter Response
0
-20
-40
-60
-80
-100
0.4
50.60.450.50.5
Frequency (Fs)
Figure 9 Single Rate 48k Filter Response
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 10 Single Rate 48k Filter Response
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DUAL RATE 96k
0
-20
-40
-60
-80
-100
0
0.51
1.52
2.53
3.54
Frequency (Fs)
Figure 11 Dual Rate 96k Filter Response
0
-20
-40
-60
-80
-100
0.4
50.60.450.50.5
Frequency (Fs)
Figure 12 Dual Rate 96k Filter Response
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 13 Dual Rate 96k Filter Response
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QUAD RATE 192k
0
-20
-40
-60
-80
-100
0
0.51
1.52
2.53
3.54
Frequency (Fs)
Figure 14 Quad Rate 192k Filter Response
0
-20
-40
-60
-80
-100
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (Fs)
Figure 15 Quad Rate 192k Filter Response
-2.5
-2.6
-2.7
-2.8
-2.9
-3
-3.1
-3.2
-3.3
-3.4
-3.5
0
0.1
0.2
0.3
0.4
0.5
Frequency (Fs)
Figure 16 Quad Rate 192k Filter Response
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DEVICE DESCRIPTION
INTRODUCTION
The WM8785 is a high performance stereo audio ADC designed for demanding recording
applications such as DVD recorders, studio mixers, PVRs, and AV amplifiers. The WM8785 consists
of stereo line level inputs, followed by a sigma-delta modulator and digital filtering.
The WM8785 uses a multi-bit high-order oversampling architecture delivering high SNR operating at
oversampling ratios from 128fs to 32fs according to the sample rate. Sample rates from 8kHz to
192kHz are supported. The WM8785 supports master clock rates from 128fs to 768fs.
The digital filter is a high performance linear phase FIR filter. The digital filters are optimised for each
sample rate. Also included is a selectable high pass filter to remove residual DC offsets from the
input signal.
The output from the ADC is available on a configurable digital audio interface. It supports a number
of audio data formats including I2S, Left justified and Right justified or DSP, and can operate in
master or slave modes.
The WM8785 can be controlled through a 2 wire or 3 wire MPU control interface. It is fully compatible
and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. A TDM
bus is supported for multiplexing data output.
The WM8785 can be powered down under software control to reduce system power consumption.
DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
•
•
•
DOUT: ADC data output
LRCLK: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT
and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with
left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left
or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always
an output. BCLK and LRCLK maybe inputs or outputs depending whether the device is in Master or
Slave mode, (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
•
•
•
•
Left justified
Right justified
I2S
DSP
They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for
timing information.
MASTER AND SLAVE MODE OPERATION
The WM8785 can be configured as either a master or slave mode device. As a master device the
WM8785 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT.
In slave mode, the WM8785 responds with data to clocks it receives over the digital audio interface.
The mode can be selected by setting MCR=000 (see Table below). Master and slave modes are
illustrated below.
Figure 17a Master Mode
Figure 17b Slave Mode
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AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 18 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 19 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 20 I2S Justified Audio Interface (assuming n-bit word length)
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In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)
rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 21 and Figure
22. In device slave mode, Figure 23 and Figure 24, it is possible to use any length of frame pulse
less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period
before the rising edge of the next frame pulse.
Figure 21 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
Figure 22 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
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Figure 23 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
Figure 24 DSP/PCM Mode Audio Interface (mode B, LRP=1, Slave)
AUDIO INTERFACE CONTROL
The register bits controlling the audio interface are summarised below. Note that dynamically
changing the software format may cause erroneous operation of the interfaces and is therefore not
recommended.
All ADC data is 2’s complement. The length of the digital audio data is programmable at 16/20/24 or
32 bits, as shown below. The ADC digital filters process data using 24 bits. If the WM8785 is
programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. If the device is
programmed to output 32 bits then it packs the LSBs with zeros.
In master mode LRCLK and BCLK are generated on chip. In slave mode they are received from an
external source.
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
10
DESCRIPTION
R0 (00h)
6:5
FORMAT
Audio Data Format Select
11: DSP Format
10: I2S Format
Sample Rate
and Digital Audio
Interface Format
01: Left justified
00: Right justified
Audio Data Word Length
11: 32 bits (see Note)
10: 24 bits
R1 (01h)
1:0
WL
10
0
Digital Audio
Interface Format
and TDM
01: 20 bits
00: 16 bits
right, left and I2S modes –
LRCLK polarity
2
LRP
1 = invert LRCLK polarity
0 = normal LRCLK polarity
DSP Mode – A/B select
1 = MSB is available on 1st
BCLK rising edge after LRC
rising edge (mode B)
0 = MSB is available on 2nd
BCLK rising edge after LRC
rising edge (mode A)
3
4
BCLKINV
LRSWAP
0
0
BCLK invert bit (for master and
slave modes)
0 = BCLK not inverted
1 = BCLK inverted
Left/Right channel swap
1 = swap left and right DAC
data in audio interface
0 = output left and right data as
normal
Table 1 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data. If WL=11 in Right justified mode, the actual
word length is 24 bits.
DIGITAL HIGH PASS
The high pass filter can be enabled using the HPFL and HPFR bits (see digital filter characteristics)
REGISTER
ADDRESS
BIT
LABEL
HPFR
DEFAULT
DESCRIPTION
R2(02h)
HPfilter ,
0
1
1
Digital High Pass Filter, Right Channel
0 = HPF Off
Output
disable,
Power down,
1 = HPF On
1
HPFL
Digital High Pass Filter, Left Channel
0 = HPF Off
Mono mode
1 = HPF On
Table 2 Oversampling Ratio Selection
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DATA OUT PIN DISABLE
To prevent any communication problems on the Audio Interface, the interface can be disabled
(DOUT tristated and floating) using the SDODIS bit.
REGISTER
ADDRESS
BIT
LABEL
SDODIS
DEFAULT
DESCRIPTION
R2(02h)
2
0
DOUT serial data pin disable
0 = DOUT pin enabled
HP Filter ,
Output
1 = DOUT pin off (high impedance)
disable,
Power down,
Mono mode
Table 3 Oversampling Ratio Selection
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8785 is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each
control register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The
CSB pin is sampled at power-up and selects the interface format. After power-up the pin is available
to latch in control data in 3-wire interface mode.
Figure 25 Control Interface Mode Selection
CSB PIN STATUS
INTERFACE FORMAT
Low
2 wire
3 wire
High
Table 4 Control Interface Mode Selection
SETUP/HOLD
tpusetup
TIME
250us
250us
tpuhold
Table 5 Control Interface Mode Selection
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3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
latch
CSB
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
control register address
control register data bits
Figure 26 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8785 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8785).
The WM8785 operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8785 and the R/W bit is ‘0’, indicating a write, then the WM8785 responds by
pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’,
the WM8785 returns to the idle condition and wait for a new start condition and valid address.
Once the WM8785 has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8785 register address plus the first bit of register data). The WM8785
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8785 acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8785 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
DEVICE ADDRESS RD / WR
(7 BITS) BIT
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
SDIN
SCLK
START
STOP
register address and
1st register data bit
remaining 8 bits of
register data
Figure 27 2-Wire Serial Control Interface
The WM8785 device address is 0011010.
TIME DIVISION MULTIPLEXED DATA OUT
The WM8785 can be used to time division multiplex several data channels at once. For example, the
diagram below illustrates 4 devices connected to the same TDM bus. While one DOUT pin is driving
data, the others will be tri-stated.
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Figure 28 WM8785 in Time Division Multiplexing Setup
Note:
1. TDM is only available in slave mode.
2. Right justified mode is not supported
TDM SELECTION
The figure below indicates how data is multiplexed onto the TDM bus, in left justified mode. This
assumes we have 4 devices, and each device has 2 data channels:
•
•
LCHAN = left channel
RCHAN = right channel
Each channel is allocated 32 BCLKs
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Figure 29 WM8785 in Time Division Multiplexing Left Justified Mode
Up to 4 devices (8 channels) can be supported, which would require 256 BCLKs per sample.
(whereas 128 BCLKs will allow only 2 devices, or 4 channels). The table below shows the range of
BCLK frequencies required.
BCLK RATE
DEVICES THAT CAN BE SUPPORTED
OVER-SAMPLE RATIOS
SUPPORTED (SET BY OSR)
64 fs
1
Single/dual/quad rates all supported
128 fs
192 fs
1, 2
1, 2
256 fs
1, 2, 3, 4
Single rate only supported
Table 6 Range of BCLK Frequencies Required
Note: MCLK frequency must always be greater or equal to BCLK frequency
To avoid bus contention all chips on the TDM should be programmed before DOUT is released after
power up (DOUT is held at vss for 32 samples after power-up). Alternatively SDODIS should be set
while devices are programmed (to tri-state DOUT).
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Two registers must be set to enter TDM mode:
•
•
DEVNO[2:0] sets the number of devices which are on the bus
TDM[2:0] allocates a TDM slot to the device
REGISTER
ADDRESS
BIT
7:5
LABEL
DEFAULT
DESCRIPTION
R1(h01)
DEVNO[2:0]
000
Number of TDM Devices
000 = 1 Device
Clocking, Sample
Rates,
Oversampling and
Signal Control
001 = 2 Devices
010 = 3 Devices
011 = 4 Devices
Table 7 DEVNO
REGISTER
ADDRESS
BIT
8:6
LABEL
DEFAULT
DESCRIPTION
R2(h02)
TDM[2:0]
000
Time Division Multiplexing
Device Select
Clocking, Sample
Rates,
000 = Device 0 (no delay)
Oversampling and
Signal Control
001 = Device 1 (64 BCLK delay)
010 = Device 2 (128 BCLK
delay)
011 = Device 3 (192 BCLK
delay)
Table 8 TDM
Note: When TDM is not required, the register will default to 000 (normal operation)
The figures below indicate TDM mode for I2S and DSP mode A.
Figure 30 TDM Bus I2S Mode
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OVERSAMPLING RATIOS AND SIGMA-DELTA MODULATOR FREQUENCY
For correct operation of the device and optimal performance, the user must select the appropriate
ADC modulator oversampling ratio. The oversampling ratio is selected using the OSR[1:0] bits.
REGISTER
ADDRESS
BIT
4:3
LABEL
DEFAULT
DESCRIPTION
R0(h00)
Signal Control
OSR[1:0]
00
Oversampling Ratio
Control
00: Single Rate (128fs)
01: Dual Rate (64fs)
10: Quad Rate (32fs)
11: Not Valid
Table 9 Oversampling Ratio Selection
The WM8785 can operate at sample rates from 8kHz to 192kHz. The WM8785 uses a sigma-delta
modulator that operates at frequencies between 1.024MHz and 6.144MHz
SAMPLING RATE
(LRCLK)
OVERSAMPLING RATIO
SIGMA-DELTA
MODULATOR
FREQUENCY (MHZ)
8kHz
32kHz
44.1kHz
48kHz
96kHz
192kHz
Single Rate (128fs)
Single Rate (128fs)
Single Rate (128fs)
Single Rate (128fs)
Dual Rate (64fs)
1.024
4.096
5.6448
6.144
6.144
6.144
Quad Rate (32fs)
Table 10 Sigma-delta Modulator Frequency
MASTER CLOCK AND AUDIO SAMPLE RATES
Master clock frequencies of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs are supported. In slave mode
the WM8785 automatically detects the audio sample rate. In Master mode the master clock
frequency is selected using MCR[2:0] bits. This is described in table below.
REGISTER
ADDRESS
BIT
2:0
LABEL
DEFAULT
000
DESCRIPTION
R0(h00)
MCR[2:0]
Master/Slave Selection
000: Slave Mode
Clocking, Sample
Rates,
001: Master Mode, 128fs
010: Master Mode, 192fs
011: Master Mode, 256fs
100: Master Mode, 384fs
101: Master Mode, 512fs
110: Master Mode, 768fs
Table 11 Master Clock Frequency
The master clock (MCLK) is used to operate the digital filters and the noise shaping circuits. The
WM8785 supports a wide range of master clock frequencies, and can generate many commonly
used audio sample rates directly from the master clock. Table 1 shows the recommended master
clock frequencies for different sample rates
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SAMPLING RATE
(LRCLK)
OVERSAMPLING
RATIO
MASTER CLOCK FREQUENCY (MHZ)
128fs
192fs
256fs
384fs
512fs
768fs
32kHz
44.1kHz
48kHz
Single Rate
Single Rate
Single Rate
Dual Rate
-
-
8.192
11.2896
12.288
24.576
-
12.288
16.9344
18.432
36.864
-
16.384
24.576
-
-
22.5792
33.8688
-
-
24.576
36.864
96kHz
-
-
-
-
-
-
192kHz
Quad Rate
24.576
36.864
Table 12 Slave Mode: Recommended Master Clock Frequency Selection
MLCK AND LRCLK PHASE RELATIONSHIP
The WM8785 does not require a specific phase relationship between MLCK and LRCLK. If the
relationship between MCLK and LRCLK changes by more than +/-8 BCLKs in a 64 BLCK frame, the
WM8785 will attempt to re-synchronise. During re-synchronisation, data samples may be dropped or
duplicated.
POWER DOWN CONTROL
The WM8785 can be powered down by setting the PWRDNL and PWRDNR bits. This is described in
the table below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R2(02h)
3
PWRDNR
0
0
Power Down Right Channel
0 = Power On
Signal control
1 = Power Off
4
PWRDNL
Power Down Left Channel
0 = Power On
1 = Power Off
Table 13 Power Down Control
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REGISTER MAP
REGISTER ADDRESS REMARK BIT8 BIT7 BIT6 BIT5
BIT4
OSR
BIT3
BIT2
MCR
BIT1
BIT0
DEFAULT
R0(00h)
00_0000 Sample
Rate
0
0
FORMAT
0_0000_0011
And
Audio IF
Format
R1(01h)
00_0001 Audio IF
Format
0
DEVNO
LRSWP
PWRDNL
BCLKINV
LRP
WL
0_0000_1010
And
TDM
R2(02h)
R7(07h)
00_0010 Signal
Control
TDM
0
PWRDNR SDODIS
HPFL HPFR
0_0000_0011
0_0000_0000
00_0111 Reset
Writing to reg 7 will cause software reset
Table 14 Register Map for Control Interface
Notes:
1. All unused register bits should be set to zero
2. The interface will initiate SWRB whenever R7 is addressed, regardless of the data input.
3. SWRB is released on the next register write or after 4 MCLK cycles (which ever occurs first).
4. Until the SWRB is released, DOUT is forced to zero.
5. DOUT remains zero for a count of 32 sample clocks SWRB is released, this count is driven by MCLK and is
independent of any external LRCLK.
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Notes:
1. AGND and DGND should be connected as close to the WM8785 as possible.
2. C1 to C6 should be placed as close to the WM8785 device as possible.
3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum performance, such as X7R. VMID and VREF decoupling
capacitors must be high quality electrolytic capacitors to achieve datasheet performance; ceramic capacitors are not acceptable.
4. An active input filter is required to achieve datasheet performance. The circuit shown is a tested inverting reference example.
Figure 31 External Component Diagram
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PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
DM0015.C
b
e
20
11
E1
E
GAUGE
PLANE
Θ
1
10
D
0.25
L
c
A1
A A2
L
1
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
Symbols
MIN
NOM
MAX
A
A1
A2
b
c
D
e
-----
0.05-----
1.651.751.85
0.22
0.09
-----
2.0
-----
0.30
-----
7.20
0.38
0.25
7.50
6.90
0.65 BSC
7.80
E
E1
7.40
5.00
8.20
5.60
5.30
L
50.7500..955
L1
θ
1.25 REF
4o
0o
8o
-
JEDEC.95, MO 150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical
components in life support devices or systems without the express written approval of an officer of the company. Life
support devices or systems are devices or systems that are intended for surgical implant into the body, or support or
sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be
reasonably expected to result in a significant injury to the user. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
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相关型号：
WM8786GEDS/V
Consumer Circuit, CMOS, PDSO20, 7.20 X 5.30 MM, 1.75 MM HEIGHT, MO-150AE, SSOP-20
CIRRUS
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