X55620V20I [XICOR]
Power Supply Management Circuit, Adjustable, 2 Channel, PDSO20, PLASTIC, TSSOP-20;
| 型号： | X55620V20I |
| 厂家： | 
XICOR INC. |
| 描述： | Power Supply Management Circuit, Adjustable, 2 Channel, PDSO20, PLASTIC, TSSOP-20 光电二极管 |
| 文件： | 总23页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
256K
X55620
Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FEATURES
DESCRIPTION
• Dual Voltage Monitoring
• System Battery Switch-Over Circuitry
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
• Early Warning Low V
Fail Indicator
CC
• Active High and Active Low Reset Outputs
• Selectable Watchdog Timer
—(0.15s, 0.4s, 0.8s, off)
• Low V
Reset Assertion
—Four standard reset threshold voltages
—Re-program V1
(V1MON) and V2MON Detection and
CC
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
and V2
reset threshold
TRIP
TRIP
voltage using special programming sequence
—Reset signal valid to V = 1V
A system battery switch circuit compares V
CC
CC
• Long Battery Life with Low Power Consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off
—<1.5mA max active current during read
• 256Kbits of EEPROM
(V1MON) with V
whichever is higher. This provides voltage to external
SRAM or other circuits in the event of main power fail-
input and connect V
to
BATT
OUT
ure. The X55620 can drive 50mA from V
and 250µA
CC
from V
. The device switches to V
when V
BATT
BATT CC
• Built-In Inadvertent Write Protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
programmable Block Lock™ protection
—In circuit programmable ROM mode
• 10MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
—64-byte page write mode
drops below the low V voltage threshold and V
.
CC
BATT
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V Power Supply Operation
• Available Packages
The device’s low V
user’s system from low voltage conditions, resetting the
detection circuitry protects the
CC
system when V (V1MON) falls below the minimum
CC
—20-lead TSSOP
V
V
trip point (V
). RESET/RESET is asserted until
CC
TRIP
returns to proper operating level and stabilizes. A
CC
second voltage monitor circuit tracks the unregulated
supply or monitors a second power supply voltage to
provide a power fail warning. Xicor’s unique circuits
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
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X55620 – Preliminary Information
BLOCK DIAGRAM
V2FAIL
+
V2MON
V2
TRIP
V2 Monitor
Logic
-
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET
Data
Register
SO
SI
Status
Register
Command
Decode, Test
& Control
Logic
Reset &
Watchdog
Timebase
EEPROM Array
512 X 512
SCK
CS
RESET
BATT-ON
System
V
Battery
Switch
OUT
Power On,
V
BATT
Low Voltage
Reset
Generation
V
+
CC
V1
(V1MON)
TRIP
V
Monitor
Logic
-
CC
LOWLINE
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X55620 – Preliminary Information
PIN CONFIGURATION
20 Pin TSSOP
20
V
(V1MON)
1
CS/WDI
NC
CC
NC
2
3
19
18
SO
RESET
BATT-ON
RESET
LOWLINE
V2FAIL
V2MON
WP
4
5
17
16
V
OUT
V
6
7
15
14
BATT
SCK
NC
NC
SI
8
13
12
11
NC
9
VSS
10
PIN DESCRIPTION
Pin
Name
Function
1
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any opera-
tion after power up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET
going active.
2
3
NC
SO
No internal connections
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin.The
falling edge of the serial clock (SCK) clocks the data out.
4
5
RESET
Reset Output. RESET is an active HIGH, CMOS output which is the inverse of the RESET output.
LOWLINE Early Low V Detect. This CMOS output signal goes LOW when V < V and returns
TRIP
CC
CC
HIGH when V > V
. This pin goes LOW 250ns before RESET pin.
CC
TRIP
6
7
V2FAIL
V2MON
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V2
TRIP
and goes HIGH when V2MON exceeds V2 . There is no power up reset delay circuitry on this
Trip
pin. This circuit works independently from the Low V reset and battery switch circuits.
CC
V2 Voltage Monitor Input. When the V2MON input is less than the V2
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
voltage, V2FAIL goes
TRIP
monitor a second power supply with no external components. Connect V2MON to V or V
when not used.
SS
CC
8
WP
NC
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits. This pin is also used as the test
mode enable pin where the high voltage will be applied. Thus the layout for the input is different
to allow for higher punch thru.
9
No internal connections
Ground
10
V
SS
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X55620 – Preliminary Information
PIN DESCRIPTION (CONTINUED)
Pin
Name
Function
11
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on
this pin.The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
12
13
14
NC
NC
No internal connections
No internal connections
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin.The falling edge of
SCK changes the data output on the SO pin.
15
16
V
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
BATT
mary V voltage. The V
tain the contents of SRAM and also powers the internal logic to “stay awake.”
voltage typically provides the supply voltage necessary to main-
CC
BATT
V
Open Drain Output Voltage. V
= V if V > V
. IF V < V
- 0.05.
, then V
= V
OUT
OUT
= V
CC
CC
VTRIP
CC
VTRIP
OUT CC
if V > V
+ 0.05, or V
if V < V
CC
BATT
OUT
BATT
CC
BATT
Note: There is hysteresis around V
ver voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
±0.05V point to avoid oscillation at or near the switcho-
BATT
17
BATT-ON Battery On. This CMOS output goes HIGH when the V switches to V and goes LOW
OUT
BATT
when V
switches to V . It is used to drive an external PNP pass transistor when V = V
OUT
CC CC OUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the V supply is fully functional. In the event of a V failure, the battery voltage is applied to
CC
OUT
CC
the V
pin and the external transistor is turned off. In this “backup condition,” the battery only
needs to supply enough voltage and current to keep SRAM devices from losing their data-there
is no communication at this time.
18
RESET
RESET Output. This is an active LOW, open drain output which goes active whenever V falls
CC
below the minimum V sense level. Then communication to the device is interrupted. It will remain
CC
active until V rises above the minimum V sense level for 150ms. RESET goes active if the
CC
CC
Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable
Watchdog time out period. RESET also goes active on power up and remains active for 150ms
after the power supply stabilizes.
19
20
NC
No internal connections
V
Supply Voltage
CC
(V1MON) V1 Voltage Monitor Input. When the V1MON input is less than the V1
voltage, RESET and
TRIP
RESET goes ACTIVE.
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X55620 – Preliminary Information
PRINCIPLES OF OPERATION
Power On Reset
RESET signal remains active until the voltage drops
below 1V. These also remain active until V returns
CC
and exceeds V1
for 150ms.
TRIP
Application of power to the X55620 activates a Power
On Reset Circuit. This circuit goes active at about 1V
and pulls the RESET/RESET pin active. This signal pre-
vents the system microprocessor from starting to oper-
ate with insufficient voltage or prior to stabilization of the
Low V2MON Voltage Monitoring
The X55620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V2
. The V2FAIL signal is either ORed with
TRIP
oscillator. When V
for 150ms (nominal) the circuit releases RESET/
RESET, allowing the processor to begin executing code.
exceeds the device V1
value
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
CC
TRIP
Low V
(V1MON) Voltage Monitoring
CC
During operation, the X55620 monitors the V
and asserts RESET/RESET if supply voltage falls
below a preset minimum V1 . During this time the
communication to the device is interrupted.The RESET/
RESET signal also prevents the microprocessor from
operating in a power fail or brownout condition. The
level
CC
V2
by 0.03V.
TRIP
TRIP
The V2MON voltage sensor is completely separate
from the operation of the low V
sense, and is inde-
CC
pendent of V supply.
CC
Figure 1. Two Uses of Dual Voltage Monitoring
V
OUT
V
V2MON
OUT
X55620
X55620
Unregulated
Supply
Unregulated
5V
Reg
5V
V
CC
Supply
V
System
Reset
CC
Reg
RESET
RESET
R
R
V2MON
System
Interrupt
System
Reset
V2FAIL
V2MON
V2FAIL
5V
Reg
Resistors selected so 3V appears on V2MON when
Unregulated supply reaches 6V.
Notice: No external components required to monitor
two voltages.
Watchdog Timer
then V
is applied to V
if V
is or equal to or
CC
OUT
CC
greater than V
- 0.03V. When V
drops to less
BATT
CC
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS pin. The microproces-
sor must toggle the CS pin HIGH to LOW periodically
prior to the expiration of the watchdog time out period
to prevent a RESET and RESET signal going active.
The state of two nonvolatile control bits in the Status
Register determines the watchdog timer period. The
microprocessor can change these watchdog bits by
writing to the status register.
than V
- 0.03V, then V
is connected to V
BATT
OUT BATT
through an 80 Ohm (typical) switch. V
typically
OUT
supplies the system static RAM voltage, so the
switchover circuit operates to protect the contents of
the static RAM during a power failure. Typically, when
V
has failed, the SRAMs go into a lower power state
CC
and draw much less current than in their active mode.
When V returns, V switches back to V when
CC
OUT
CC
V
exceeds V
+0.03V. There is a 60mV hystere-
CC
BATT
The Watchdog Timer oscillator stops when in battery
sis around this battery switch threshold to prevent
oscillations between supplies.
backup mode. It re-starts when V returns.
CC
While V
is connected to V
the BATT-ON pin is
CC
OUT
System Battery Switch
pulled LOW. The signal can drive an external PNP
transistor to provide additional current to the external
circuits during normal operation.
As long as V
exceeds the low voltage detect thresh-
CC
old V1
, V
is connected to V through a 5 Ohm
TRIP OUT CC
(typical) switch. When the V
has fallen below V
,
CC
TRIP
Characteristics subject to change without notice. 5 of 23
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X55620 – Preliminary Information
V
(V1MON), V2MON Threshold Reset Procedure
To set the new voltage, apply the desired V
thresh-
CC
TRIP
old voltage to the V
V2MON pin (during V2MON V2
should be same as V2MON), then tie the WP pin to the
programming voltage V . Then, send the WREN com-
pin or the V2
voltage to the
setting only V
CC
CC
TRIP
The X55620 is shipped with standard V
(V1MON)
CC
TRIP
and V2MON threshold (V1
, V2
) voltages. These
TRIP
TRIP
values will not change over normal operating and stor-
age conditions. However, in applications where the stan-
dard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X55620
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
P
mand and write to address 01h or to address 0Bh to
program V
or V2
, respectively (followed by
TRIP
TRIP
data byte 00h). The CS going high after a valid write
operation initiates the programming sequence. Bring
WP LOW to complete the operation. Note: this opera-
tion will not alter the contents of the EEPROM.
Setting the V
Voltage
TRIP
This procedure is used to set the V1
or V2
to a
TRIP
TRIP
lower or higher voltage value. It is necessary to reset
the trip point before setting the new value.
Figure 2. Example System Connection
Unregulated
Supply
5V
Reg
V
V
CC
BATT-ON
SRAM
V
OUT
BATT
V
V2MON
OUT
Address
Decode
V2MON
RESET
+
V2FAIL
Enable
Addr
V
NMI
LOWLINE
RESET
CC
RESET
µC
SPI
CS, SCK
SI, SO
V
SS
Resetting the V
Voltage
voltage V . Then send the WREN command and write
P
TRIP
to address 03h or 0Dh to reset the V1
or V2
TRIP
TRIP
This procedure is used to set the V1
to a “native” voltage level. For example, if the current
or the V
2TRIP
TRIP
respectively (followed by data byte 00h). The CS going
LOW to HIGH after a valid write operation initiates the
programming sequence. Bring WP LOW to complete
the operation.
V
is 4.4V and the new V must be 4.0V, then
TRIP
TRIP
the V
must be reset. When the threshold is reset,
TRIP
the new level is something less than 1.7V. This proce-
dure must be used to set the voltage to a lower value.
Note: this operation does not change the contents of
the EEPROM array.
To reset the new V1
or V2
voltage, apply
TRIP
TRIP
greater than 3V to V
(V1MON) or V2MON pin,
CC
respectively, and tie the WP pin to the programming
Characteristics subject to change without notice. 6 of 23
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X55620 – Preliminary Information
Figure 3. Set V
Level Sequence (V
= desired V
)
TRIP
CC
TRIP
V
= 10-15V
P
WP
CS
0
1
2
3
4
5
6
7
0
1
2
3
4 5
6
7
8
9 10
20 21 22 23
SCK
16 Bits
SI
02h
WRITE
0001h/000Bh
ADDRESS
00h
DATA
06h
WREN
Addr 01h: Set V
(V1trip)
CC
Addr 0Bh: Set V2MON trip
Figure 4. Reset V
Level Sequence (V
> 3V. WP = 10-15V)
TRIP
CC
V
= 10-15V
P
WP
CS
0
1
2
3
4
5
6
7
0
1
2
3
4 5
6
7
8
9 10
20 21 22 23
SCK
SI
16 Bits
02h
WRITE
0003h/000Dh
ADDRESS
00h
DATA
06h
WREN
Addr 03h: Update V
(V1trip)
CC
Addr 0Dh: Update V2MON trip
Figure 5. Sample V
Reset Circuit
TRIP
4.6K
X55620
V
RESET
µC
P
V
CS
SO
WP
CC
Adjust
Run
RESET
SCK
SCK
SI
V
TRIP
V
SI
Adj.
SS
SO
CS
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X55620 – Preliminary Information
Figure 6. V
Programming Sequence Flow Chart
TRIP
V
Programming
Execute
TRIP
Reset V
Sequence
TRIP
Set V
= V
Applied =
TRIP
CC
CC
Desired V
Execute
Set V
TRIP
Sequence
Apply 5V to V
CC
Decrement V
= V
CC
(V
- 10mV)
CC
CC
NO
RESET pin
goes active?
YES
Error > Emax
Error ≥ Emax
Measured V
Desired V
-
TRIP
TRIP
Error < Emax
DONE
Execute
Reset V
New V
Applied =
Applied + Error
CC
TRIP
Old V
CC
Sequence
New V
Applied =
Applied - Error
CC
Emax = Maximum Desired Error
Old V
CC
Characteristics subject to change without notice. 8 of 23
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X55620 – Preliminary Information
SPI SERIAL MEMORY
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
7
6
5
4
3
2
1
0
WPEN WD1 WD0 BL2 BL1 BL0 WEL WIP
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch
RSDR
WRSR
READ
WRITE
Read Status Register
Write Status Register (Watchdog, block lock, WPEN)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD Status Register Device Pin
Block
Block
Status Register
WPEN, BL0, BL1,
BL2, WD0, WD1
WEL
WPEN
WP#
Protected Block Unprotected Block
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Protected
Writable
Writable
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X55620 – Preliminary Information
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL=1, the latch is
set HIGH and when WEL=0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Status Register Bits
Watchdog Time Out
WD1
WD0
(Typical)
800 Milliseconds
400 Milliseconds
150 Milliseconds
Disabled
0
0
1
1
0
1
0
1
The block lock bits, BL0, BL1 and BL2, set the level of
block lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will remain
protected until the BL bits are altered to disable block
lock protection of that portion of memory.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.
Status Register Bits Array Addresses Protected
BL2
0
BL1
0
BL0
0
X55620
None
0
0
1
6000h–7FFFh
4000h–7FFFh
0000h–7FFFh
0000h–003Fh
0000h–007Fh
0000h–00FFh
0000h–01FFh
In Circuit Programmable ROM Mode
0
1
0
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
0
1
1
1
0
0
In the locked state (Programmable ROM Mode) the WP
pin is LOW and the nonvolatile bit WPEN is “1”. This
mode disables nonvolatile writes to the device’s Status
Register.
1
0
1
1
1
0
1
1
1
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
Figure 7. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
Characteristics subject to change without notice. 10 of 23
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X55620 – Preliminary Information
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to “1”
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).
– Reset Signal is active for t
.
PURST
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
Write Sequence
– A WREN instruction must be issued to set the Write
Enable Latch.
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
Characteristics subject to change without notice. 11 of 23
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X55620 – Preliminary Information
Figure 8. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Figure 9. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Characteristics subject to change without notice. 12 of 23
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X55620 – Preliminary Information
Figure 10. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Figure 11. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
10 11 12 13 14 15
SCK
Instruction
Data Byte
6
5
4
3
2
1
0
SI
High Impedance
SO
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 13 of 23
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X55620 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ...................–65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
respect to V ......................................–1.0V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Device Option
-2.7A
Supply Voltage
2.7V-5.5V
–40°C
+85°C
Blank
4.5V-5.5V
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
(1)
CC1
I
V
Supply Current (Active)
mA
SCK = V x 0.1/V
0.9 @ 10MHz, SO,
x
CC
CC
CC
(Excludes I
(Excludes I
Memory
) Read Memory array
) Write nonvolatile
1.5
3.0
OUT
OUT
V
, RESET,
OUT
LOWLINE = Open
(2)
CC2
I
V
Supply Current (Passive)
µA
CS = V , V = V or
CC
CC IN
SS
V
, V
, RESET,
(Excludes I
(Excludes I
(Excludes I
) WDT on, 5V
) WDT on, 2.7V
) WDT off, 5V
50.0
40.0
30.0
90.0
60.0
50.0
CC OUT
OUT
OUT
OUT
LOWLINE = Open
(1)
CC3
I
V
Current (Battery Backup Mode)
1
µA
V
V
= 0V, V
= 2.8V,
CC
CC
BATT
, RESET = Open
(Excludes I
)
OUT
OUT
(3)
I
V
Current (Excludes I
)
)
1
µA
µA
V
= V
= V
BATT1
BATT
BATT
OUT
OUT
CC
I
V
Current (Excludes I
0.4
1.0
V
V
,
BATT
BATT2
OUT
OUT
(Battery Backup Mode)
= 2.8V
BATT
V
, RESET = Open
OUT
V
V
Output Voltage (V > V
CC
+ 0.03V
+ 0.03V
V
V
– 0.05
V
V
-0.02
V
V
I
I
= -5mA
= -50mA
OUT1
BATT
CC
CC
OUT
OUT
or V > V
– 0.5
-0.2
CC
TRIP
CC
CC
Output Voltage (V < V
V
– 0.2
V
V
I
= -250µA
OUT2
CC
BATT
BATT
OUT
and V < V
) {Battery Backup}
CC
TRIP
V
Output (BATT-ON) LOW Voltage
0.4
V
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLB
OL
OL
V
Output (BATT-ON) HIGH Voltage
Battery Switch Hysteresis
V
–0.8
V
I
= -0.4mA (3V)
OHB
OUT
OH
V
50
-50
mV
mV
Power Up
Power Down
BSH
(V < V
)
CC
TRIP
Characteristics subject to change without notice. 14 of 23
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X55620 – Preliminary Information
D.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
RESET/RESET/LOWLINE
V
V
Reset Trip Point Voltage
4.5
4.62
4.75
60
V
mV
V
TRIP
CC
V
Low V RESET Hysteresis
CC
LVRH
V
Output (RESET, RESET, LOWLINE)
LOW Voltage
0.4
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLR
OL
OL
V
Output (RESET, LOWLINE) HIGH
Voltage
V
– 0.8
V
I
= -0.4mA (5V)
OHR
OUT
OL
Second Supply Monitor
I
V2MON Current
15
30
3.05
60
µA
V
V2
V2
V2MON Reset Trip Point Voltage
V2MON Hysteresis
2.85
2.95
TRIP
V
mV
V
V2H
V
Output (V2FAIL) LOW Voltage
0.4
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLx
OL
OL
SPI Interface
(4)
V
Input (CS, SI, SCK, WP) LOW Voltage
Input (CS, SI, SCK, WP) HIGH Voltage
-0.5
V
x 0.3
V
V
ILx
CC
(4)
IHx
V
V
x 0.7
V
+ 0.5
CC
CC
I
Input Leakage Current (CS, SI, SCK,
WP)
±10
µA
LIx
V
Output (SO) LOW Voltage
0.4
V
V
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLS
OHS
OL
OL
V
Output (SO) HIGH Voltage
V
– 0.8
I
= -1.0mA (5V)
OUT
OH
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.
WC
(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t
after a stop that
WC
initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(3) Negative number indicate charging current, Positive numbers indicate discharge current.
(4) V min. and V max. are for reference only and are not tested.
IL
IH
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Max.
Unit Conditions
(1)
C
Output Capacitance (SO, RESET, V2FAIL, RESET, LOWLINE, BATT-ON)
Input Capacitance (SCK, SI, CS, WP)
8
6
pF
pF
V
= 0V
OUT
OUT
(1)
IN
C
V
= 0V
IN
Notes: (1) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 15 of 23
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X55620 – Preliminary Information
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
V
V
OUT
V2MON
OUT
Input rise and fall times
Input and output timing level
10ns
V
x0.5
CC
1.53KΩ
1.53KΩ
2.06KΩ
RESET/RESET
BATT-ON/LOWLINE
30pF
SO
3.03KΩ
V2FAIL
30pF
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7–5.5V
Symbol
Parameter
Clock Frequency
Min.
0
Max.
Unit
MHz
ns
f
10
SCK
CYC
t
Cycle Time
100
50
t
CS Lead Time
CS Lag Time
ns
LEAD
t
200
40
ns
LAG
t
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
WH
t
40
ns
WL
t
10
ns
SU
t
10
ns
H
(3)
t
t
20
20
ns
RI
(3)
ns
FI
t
50
ns
CS
(4)
WC
t
10
ms
Characteristics subject to change without notice. 16 of 23
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X55620 – Preliminary Information
Serial Input Timing
t
CS
CS
t
t
LAG
LEAD
SCK
SI
t
t
t
t
FI
SU
H
RI
MSB IN
LSB IN
High Impedance
SO
Serial Output Timing
Symbol
2.7–5.5V
Parameter
Clock Frequency
Min.
Max.
10
Unit
MHz
ns
f
0
SCK
t
Output Disable Time
Output Valid from Clock Low
Output Hold Time
50
DIS
t
40
ns
V
t
0
ns
HO
(3)
t
t
Output Rise Time
25
25
ns
RO
(3)
Output Fall Time
ns
FO
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle.
Characteristics subject to change without notice. 17 of 23
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X55620 – Preliminary Information
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
t
t
t
t
DIS
V
HO
WL
SO
SI
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
Power-Up and Power-Down Timing
V
TRIP
V
BATT
V
CC
0V
t
RPD
t
t
PURST
PURST
RESET
V
V
CC
BAT
V
OUT
0V
V
V
OUT
OUT
RESET
t
t
VB2
VB1
BATT-ON
Characteristics subject to change without notice. 18 of 23
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X55620 – Preliminary Information
V
to LOWLINE Timings
CC
V
V
TRIP
TRIP
V
CC
t
RPD
t
F
0V
t
RPD
t
R
V
OH
LOWLINE
V
OL
V
TRIP
V
BATT
0V
V2MON to V2FAIL Timings
V
TRIP
V2MON
0V
t
RPD2
t
t
RPD2
F
t
R
V2FAIL
RESET Output Timing
Symbol
Parameter
Min.
Typ.
150
10
Max.
250
20
Unit
ms
µs
µs
ns
µs
µs
V
t
RESET/RESET Time-out Period
75
PURST
(5)
t
V
V
RESET/RESET (Power down only) V
to LOWLINE
TRIP
RPD
TRIP
(5)
t
to V2FAIL
10
20
RPD2
TRIP
t
LOWLINE to RESET/RESET delay (Power down only)
100
1000
1000
1
250
800
LR
(6)
t
V
V
/V2MON Fall Time
/V2MON Rise Time
F
CC
(6)
t
R
CC
V
Reset Valid V
CC
RVALID
t
t
V
V
+ 0.03 v to BATT-ON (logical 0)
- 0.03 v to BATT-ON (logical 1)
20
20
µs
µs
VB1
VB2
BATT
BATT
Notes: (5) This parameter is not 100% tested.
(6) This measurement is from 10% to 90% of the supply voltage.
Characteristics subject to change without notice. 19 of 23
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X55620 – Preliminary Information
CS/WDI vs. RESET/RESET Timing
CS/WDI
t
CST
RESET
RESET
t
t
RST
t
t
RST
WDO
WDO
RESET/RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WDO
75
200
500
150
400
800
250
600
1200
ms
ms
ms
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
t
CS Pulse Width to Reset the Watchdog
Reset Time Out
400
75
ns
CST
t
150
250
ms
RST
V
Set/Reset Conditions
TRIP
V
XTRIP
V
/V2MON
CC
t
TSU
t
THD
V
P
WP
t
VPH
t
VPS
t
PCS
t
VPO
CS
t
WC
SCK
SI
* 0001h Set V1
* 0003h Set V2
* 000Bh Reset V1
* all others reserved
06h
02h
TRIP
TRIP
X = 1, 2
TRIP
TRIP
* 000Dh Reset V1
Characteristics subject to change without notice. 20 of 23
REV 1.0 6/21/00
www.xicor.com
X55620 – Preliminary Information
V1
, V2
Programming Specifications V = 2.7-5.5V; Temperature = 25°C
TRIP
TRIP
CC
Parameter
Description
Min. Max. Unit
t
WP V
WP V
Program Voltage Setup time
Program Voltage Hold time
10
10
10
10
µs
µs
µs
ms
ms
ms
V
VPS
VPH
TRIP
t
TRIP
t
V
V
V
Level Setup time
TSU
TRIP
TRIP
TRIP
t
Level Hold (stable) time
Write Cycle Time
THD
t
10
WC
t
WP V
Program Voltage Off time before next cycle
1
VPO
TRIP
V
Programming Voltage
Programed Voltage Range
10
2.5
15
P
V
V
5.0
V
TRAN
TRIP
V
Initial V
at 25°C.)
Program Voltage accuracy (V applied—V ) (Programmed
TRIP
-0.2 +0.4
V
ta1
TRIP
CC
V
Subsequent V
Program Voltage accuracy [(V applied—V )—V )
TRIP
-25
-25
-25
+25
+25
+25
mV
mV
mV
ta2
TRIP
CC
ta1
(Programmed at 25°C.)
V Program Voltage repeatability (Successive program operations.)
TRIP
V
tr
(Programmed at 25°C.)
V
V
TRIP
Program variation after programming (0–75°C). (Programmed at 25°C.)
tv
V
Programming parameters are periodically sampled and are not 100% tested.
TRIP
Characteristics subject to change without notice. 21 of 23
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X55620 – Preliminary Information
PACKAGING INFORMATION
20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 22 of 23
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X55620 – Preliminary Information
Ordering Information
Operating
Temperature Range
V
Range
V1
Range
V2 Range
TRIP
Package
Part Number
X55620V20-4.5A
X55620V20I-4.5A
X55620V20
CC
TRIP
4.5–5.5V
4.5–5.5V
2.7–5.5V
2.7–5.5V
4.5–4.75V
4.5–4.75V
2.85–3.0V
2.55–2.75V
2.55–2.7V
2.85–3.0V
4.5–4.75V
4.5–4.75V
20L TSSOP
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
20L TSSOP
20L TSSOP
20L TSSOP
X55620V20I
X55620V20-2.7A
X55620V20I-2.7A
X55620V20-2.7
X55620V20I-2.7
Part Mark Information
X55620
W
V20 = 20-Lead TSSOP
X
Blank = 5V ±10%, 0 to +70°C, V1
=4.5–4.75, V2
=2.55–2.7
TRIP
TRIP
AL =5V±10%, 0 to +70°C, V1
=4.5–4.75, V2
=2.85–3.0
TRIP
TRIP
I = 5V ±10%, –40 to +85°C, V1
=4.5–4.75, V2
=2.55–2.7
TRIP
TRIP
AM = 5V ±10%, –40 to +85°C, V1
=4.5–4.75, V2
=2.85–3.0
TRIP
TRIP
F = 2.7V to 5.5V, 0 to +70°C, V1
=2.85–3.0, V2
=4.5–4.75
TRIP
TRIP
AN = 2.7V to 5.5V, 0 to +70°C, V1
=2.55–2.7, V2
=4.5–4.75
TRIP
TRIP
G = 2.7V to 5.5V, –40 to +85°C, V1
=2.85–3.0, V2
=4.5–4.75
TRIP
TRIP
AP = 2.7V to 5.5V, –40 to +85°C, V1
=2.55–2.7, V2
=4.5–4.75
TRIP
TRIP
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 23 of 23
REV 1.0 6/21/00
www.xicor.com
相关型号：
X55620V20I-2.7
Power Supply Management Circuit, Adjustable, 2 Channel, PDSO20, PLASTIC, TSSOP-20
XICOR
X55620V20I-2.7A
Power Supply Management Circuit, Adjustable, 2 Channel, PDSO20, PLASTIC, TSSOP-20
XICOR
X55620V20I-4.5
Power Supply Management Circuit, Adjustable, 2 Channel, PDSO20, PLASTIC, TSSOP-20
XICOR
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