X9241AYVI [XICOR]
Quad Digitally Controlled Potentiometer (XDCP); 四数控电位器( XDCP )型号: | X9241AYVI |
厂家: | XICOR INC. |
描述: | Quad Digitally Controlled Potentiometer (XDCP) |
文件: | 总18页 (文件大小:365K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
APPLICATION NOTE
A V A I L A B L E
AN20 • AN42–48 • AN50-53 • AN73 • AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Power/2-Wire Serial Bus
X9241A
Quad Digitally Controlled Potentiometer (XDCP™)
FEATURES
DESCRIPTION
• Four potentiometers in one package
• 2-wire serial interface
• Register oriented format
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
—Direct read/write/transfer of wiper positions
—Store as many as four positions per
potentiometer
• Terminal Voltages: +5V, -3.0V
• Cascade resistor arrays
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
• Low power CMOS
• High Reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 16-bytes of nonvolatile memory
• 3 resistor array values
—2KΩ to 50KΩ mask programmable
—Cascadable for values of 500Ω to 200KΩ
• Resolution: 64 taps each pot
• 20-lead plastic DIP, 20-lead TSSOP and 20-lead
SOIC packages
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
V
CC
SS
V
R
/
H2
R0
R2
V
/R
R0
R2
R1
R3
R1
R3
H0 H0
Wiper
Counter
Register
H2
Wiper
Counter
Register
(WCR)
Register
Array
Pot 2
(WCR)
V
/R
V
V
/R
L0 L0
L2 L2
/R
V
/R
W2 W2
W0 W0
SCL
SDA
Interface
and
Control
Circuitry
A0
A1
A2
A3
8
Data
V
/R
H1 H1
V
/R
H3 H3
R0
R2
R1
R3
R0
R2
R1
R3
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
Register
Array
Pot 3
Register
Array
Pot 1
V
V
/R
L1 L1
V
V
/R
L3 L3
/R
W1 W1
/R
W3 W3
Characteristics subject to change without notice. 1 of 18
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X9241A
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
PIN CONFIGURATION
DIP/SOIC/TSSOP
V
V
/R
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
W0 W0
/R
The SCL input is used to clock data into and out of the
X9241A.
L0 L0
V
/R
W3 W3
V
/R
H0 H0
V
/R
L3 L3
A0
V
/R
H3 H3
Serial Data (SDA)
A2
A1
X9241A
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
V
/R
W1 W1
A3
V
/R
L1 L1
SCL
V
/R
V
/R
W2 W2
H1 H1
SDA
V
V
/R
L2 L2
/R
V
H2 H2
SS
PIN NAMES
Symbol
Address
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9241A.
Description
Serial Clock
SCL
SDA
Serial Data
Address
A0–A3
V
V
/R –V /R
,
Potentiometer Pins
(terminal equivalent)
H0 H0 H3 H3
Potentiometer Pins
/R –V /R
L0 L0 L3 L3
V
/R –V /R
Potentiometer Pins
(wiper equivalent)
W0 W0 W3 W3
V /R (V /R —V /R ), V /R (V /R —V /R )
H
H
H0 H0
H3 H3
L
L
L0 L0
L3 L3
The R and R inputs are equivalent to the terminal
H
L
PRINCIPLES OF OPERATION
connections on either end of
potentiometer.
a
mechanical
The X9241A is a highly integrated microcircuit
incorporating four resistor arrays, their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
V /R (V /R —V /R )
W3 W3
W
W
W0 W0
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Characteristics subject to change without notice. 2 of 18
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X9241A
Serial Interface
Array Description
The X9241A supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9241A will be considered a
slave device in all applications.
The X9241A is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V /R and V /R inputs).
H
H
L
L
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V /
W
R ) output. Within each individual array only one
W
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
). SDA state changes during
LOW
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA
Device Addressing
while SCL is HIGH (t
). The X9241A continuously
HIGH
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9241A
this is fixed as 0101[B].
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Figure 1. Slave Address
Device Type
Identifier
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data. See Figure 7.
0
1
0
1
A3
A2
A1
A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9241A compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9241A to respond with an acknowledge.
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9241A will respond with a final acknowledge.
Characteristics subject to change without notice. 3 of 18
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X9241A
Acknowledge Polling
Instruction Structure
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9241A
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9241A is still busy with the write operation no ACK
will be returned. If the X9241A has completed the
write operation an ACK will be returned and the
master can then proceed with the next operation.
The next byte sent to the X9241A contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of four pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.
Figure 2. Instruction Byte Format
Potentiometer
Select
I3
I2
I1
I0
P1
P0
R1
R0
Flow 1. ACK Polling Sequence
Instructions
Register
Select
Nonvolatile Write
Command Completed
Enter ACK Polling
The four high order bits define the instruction. The next
two bits (P1 and P0) select which one of the four
potentiometers is to be affected by the instruction. The
last two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued.
Issue
START
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM. The response of
Issue Slave
Issue STOP
Address
No
ACK
Returned?
the wiper to this action will be delayed t
. A
Yes
STPWV
transfer from WCR current wiper position, to a Data
Register is a write to nonvolatile memory and takes a
FurTher
OperaTion?
No
minimum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all four of the
potentiometers and one of their associated registers.
Yes
Issue
Instruction
Issue STOP
Proceed
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9241A; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected Data Register. The
sequence of operations is shown in Figure 4.
Proceed
Characteristics subject to change without notice. 4 of 18
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X9241A
The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9241A has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
resistor segment towards the V /R terminal. Similarly,
H H
for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards
the V /R terminal. A detailed illustration of the
L
L
sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
capability to the host. For each SCL clock pulse (t
)
HIGH
while SDA is HIGH, the selected wiper will move one
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0
P1 P0 R1 R0
A
C
K
S
T
O
P
A
C
K
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0 P1 P0 R1 R0
DW D5 D4 D3 D2
S
T
A
C
K
A
C
K
CM
D1 D0
A
C
K
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
X
X
A
C
K
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
I3 I2
I1 I0 P1 P0 R1 R0
A
C
K
I
I
I
D
E
C
1
D
S
N
C
1
N
C
2
N
C
n
E
C
n
T
O
P
Characteristics subject to change without notice. 5 of 18
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X9241A
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
ISSUED
t
CLWV
SCL
SDA
Voltage Out
V
/R
W
W
Table 1. Instruction Set
Instruction Format
Instruction
I
I
I
I
P
1/0(10)
P
R
X(11)
R
0
Operation
Read the contents of the Wiper Counter
Register pointed to by P –P
3
2
1
0
1
0
1
Read WCR
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
1/0
1/0
1/0
1/0
1/0
X
1
0
Write WCR
1/0
X
X
Write new value to the Wiper Counter
Register pointed to by P –P
1
0
Read Data
Register
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Read the contents of the Register
pointed to by P –P and R –R
1
0
1
0
Write Data
Register
1/0
Write new value to the Register pointed
to by P –P and R –R
1
0
1
0
XFR Data
Register to
WCR
1/0
Transfer the contents of the Register
pointed to by P –P and R –R to its
1
0
1
0
associated WCR
XFR WCR to
Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0
X
1/0
X
1/0
1/0
1/0
X
1/0
1/0
1/0
X
Transfer the contents of the WCR
pointed to by P –P to the Register
1
0
pointed to by R –R
1
0
Global XFR
DataRegisterto
WCR
Transfer the contents of the Data
Registers pointed to by R –R of all four
1
0
pots to their respective WCR
Global XFR
WCR to Data
Register
X
X
Transfer the contents of all WCRs to their
respective data Registers pointed to by
R –R of all four pots
1
0
Increment/
Decrement
Wiper
1/0
1/0
Enable Increment/decrement of the
WCR pointed to by P –P
1
0
Notes: (10) 1/0 = data is one or zero
(11) X = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical)
Characteristics subject to change without notice. 6 of 18
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X9241A
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
DETAILED OPERATION
The WCR is a volatile register; that is, its contents are
lost when the X9241A is powered-down. Although the
register is automatically loaded with the value in DR0
upon power-up, it should be noted this may be different
from the value present at power-down.
All four XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
is comprised of a resistor array, a Wiper Counter
Register and four Data Registers. A detailed discussion
of the register organization and array operation follows.
Data Registers
Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of 10ms.
Wiper Counter Register
The X9241A contains four volatile Wiper Counter
Registers (WCR), one for each XDCP potentiometer.
The WCR can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select
one of sixty-four switches along its resistor array. The
contents of the WCR can be altered in four ways: it may
be written directly by the host via the Write WCR
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated Data
Registers via the XFR Data Register instruction
(parallel load); it can be modified one step at a time by
the increment/decrement instruction; finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
Characteristics subject to change without notice. 7 of 18
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X9241A
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
V /R
H
H
From Interface
Circuitry
Register 0
Register 2
Register 1
Parallel
Bus
Input
8
6
C
o
u
n
t
e
r
Wiper
Counter
Register
Register 3
D
e
c
o
d
e
2
INC/DEC
Logic
UP/DN
If WCR = 00[H] then V /R = V /R
L
W
W
L
UP/DN
If WCR = 3F[H] then V /R = V /R
V /R
W
W
H
H
Modified SCL
L
L
CLK
DW
Cascade
Control
Logic
V
/R
W
W
CM
Cascade Mode
The state of DW enables or disables the wiper. When
the DW bit of the WCR is set to “0” the wiper is enabled;
when set to “1” the wiper is disabled. If the wiper is
disabled, the wiper terminal will be electrically isolated
and float.
The X9241A provides a mechanism for cascading the
arrays. That is, the sixty-three resistor elements of one
array may be cascaded (linked) with the resistor
elements of an adjacent array. The V /R of the higher
L
L
order array must be connected to the V /R of the
lower order array (See Figure 9).
H
H
When operating in cascade mode V /R , V /R and
H
H
L
L
the wiper terminals of the cascaded arrays must be
electrically connected externally. All but one of the
wipers must be disabled. The user can alter the wiper
position by writing directly to the WCR or indirectly by
transferring the contents of the Data Registers to the
WCR or by using the Increment/Decrement command.
Cascade Control Bits
The data byte, for the three-byte commands, contains 6
bits (LSBs) for defining the wiper position plus two high
order bits, CM (Cascade Mode) and DW (Disable
Wiper, normal operation).
When using the Increment/Decrement command the
wiper position will automatically transition between
arrays. The current position of the wiper can be
determined by reading the WCR registers; if the DW bit
is “0”, the wiper in that array is active. If the current
wiper position is to be maintained on power-down a
global XFR WCR to Data Register command must be
issued to store the position in NV memory before
power-down.
The state of the CM bit (bit 7 of WCR) enables or
disables cascade mode. When the CM bit of the WCR
is set to “0” the potentiometer is in the normal operation
mode. When the CM bit of the WCR is set to “1” the
potentiometer is cascaded with its adjacent higher
order potentiometer. For example; if bit 7 of WCR2 is
set to “1”, pot 2 will be cascaded to pot 3.
Characteristics subject to change without notice. 8 of 18
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X9241A
Figure 9. Cascading Arrays
V
/R
L0 L0
Pot 0
WCR0
V
/R
H0 H0
V
V
/R
W0 W0
/R
L1 L1
Pot 1
WCR1
V
/R
H1 H1
V
V
/R
W1 W1
/R
L2 L2
Pot 2
WCR2
V
/R
H2 H2
V
V
/R
W2 W2
/R
L3 L3
Pot 3
WCR3
V
V
/R
H3 H3
External
Connection
=
/R
W3 W3
It is possible to connect three or all four potentiometers in cascade mode. It is also possible to connect POT 3 to
POT 0 as a cascade. The requirements for external connections of V /R , V /R and the wipers are the same in
L
L
H
H
these cases.
Characteristics subject to change without notice. 9 of 18
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X9241A
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ........................–65 to +135°C
Storage temperature .............................–65 to +150°C
Voltage on SCK, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
input with respect to V .........................–1V to +7V
SS
Voltage on any V /R , V /R or V /R
H
H
W
W
L
L
referenced to V ....................................... +6V/-4V
SS
∆V = |V /R –V /R |.............................................. 10V
H
H
L
L
Lead temperature (soldering, 10 seconds)........ 300°C
(10 seconds).................................................. 6mA
I
W
RECOMMENDED OPERATING CONDITIONS
Product
Temperature Range
Min.
Max.
Supply Voltage
X9241A
Commercial
Industrial
0°C
–40°C
+70°C
+85°C
5V 10ꢀ
5V 10ꢀ
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to end resistance
Min.
Typ.
Max.
+20
50
Unit
ꢀ
Test Condition
25°C, each pot
R
–20
TOTAL
Power rating
mW
mA
Ω
I
Wiper current
Wiper resistance
See Note 7, 8
W
R
40
130
+5
Wiper Current = 1mA
See Note 7
W
V
Voltage on any V /R , V /R or
–3.0
V
TERM
H
H
W
W
V /R Pin
L
L
Noise
Resolution(4)
Absolute linearity(1)
Relative linearity(2)
≤120
dBV
ꢀ
MI(3)
MI(3)
Ref: 1KHz See Note 5
See Note 5
1.6
0.4
1
R
R
–R
w(n)(actual) w(n)(expected)
0.2
–[R
]
w(n + 1)
w(n) + MI
Temperature Coefficient of R
300
ppm/°C See Note 5
ppm/C See Note 5
TOTAL
Ratiometric temperature coefficient
Potentiometer capacitances
20
1
C /C /C
15/15/25
0.1
pF
µA
See Circuit #3 and Note 5
H
L
W
l
R , R , R leakage current
V
IN
= V . Device is in
AL
H
I
W
TERM
stand-by mode.
Characteristics subject to change without notice. 10 of 18
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X9241A
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Condition
l
Supply current (active)
3
mA
f
= 100kHz, SDA = Open,
SCL
CC
Other Inputs = V
SS
I
V
current (standby)
200
500
10
µA
µA
µA
V
SCL = SDA = V , Addr. = V
CC SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
V
V
= V to V
SS CC
LI
IN
I
10
= V to V
OUT SS CC
LO
V
2
V
+ 1
CC
IH
V
–1
0.8
0.4
V
IL
V
V
I
= 3mA
OL
OL
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a poten-
tiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R –R )/63, single pot
H
L
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
Parameter
Max.
Unit
pF
Test Condition
(5)
C
Input/output capacitance (SDA)
19
12
V
= 0V
= 0V
I/O
I/O
(5)
C
Input capacitance (A0, A1, A2, A3 and SCL)
pF
V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Typ.
Max.
1
Unit
ms
(6)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
PUR
(6)
t
5
ms
PUW
t V
V
Power up ramp rate
0.2
50
V/msec
R CC
CC
POWER-UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc
reach 90ꢀ of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification
should be met, and any glitches or slope changes in the Vcc line should be held to <100mV if possible. Also, Vcc
should not reverse polarity by more than 0.5V.
Notes: (5) This parameter is guaranteed by characterization or sample testing.
(6) t
and t
are the delays required from the time V
is stable until the specified operation can be initiated. These parameters
PUR
PUW
CC
are guaranteed by design.
(7) This parameter is guaranteed by design.
(8) Maximum Wiper Current is derated over temperature. See the Wiper Current Derating Curve.
(9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitch pulse
width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure
to the device.
Characteristics subject to change without notice. 11 of 18
REV 1.1.13 12/09/02
www.xicor.com
X9241A
A.C. CONDITIONS OF TEST
Guidelines for Calculating
Typical Values of Bus Pull-Up Resistors
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing levels
10ns
120
V
I
CC MAX
R
R
=
=1.8KΩ
MIN
V
x 0.5
CC
100
80
OL MIN
t
R
=
MAX
SYMBOL TABLE
C
BUS
Max.
Resistance
60
40
20
0
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
Min.
Resistance
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
20 40 60 80
120
100
0
Bus Capacitance (pF)
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
DCP Wiper Current De-rating Curve
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
7
6
5
4
3
N/A
Center Line
is High
Impedance
Equivalent A.C. Test Circuit
2
1
0
5V
1533Ω
0
10
20
30
40 50
60 70
80 90
Ambient Temperature (°C)
SDA Output
100pF
Circuit #3 SPICE Macro Model
Macro Model
R
H
TOTAL
R
R
H
L
C
C
L
10pF
C
W
10pF
25pF
R
W
Characteristics subject to change without notice. 12 of 18
REV 1.1.13 12/09/02
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X9241A
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Reference
Figure
Symbol
Parameter
Min.
0
Max.
Unit
kHz
ns
(5)
f
SCL clock frequency
Clock LOW period
Clock HIGH period
100
10
10
SCL
(5)
t
4700
4000
LOW
(5)
t
ns
10
HIGH
(5)
t
SCL and SDA rise time
1000
300
20
ns
10
R
(5)
t
SCL and SDA fall time
ns
10
F
T (5)(9)
Noise suppression time constant (glitch filter)
Start condition setup time (for a repeated start condition)
Start condition hold time
ns
10
i
(5)
(5)
(5)
(5)
t
4700
4000
250
0
ns
10 & 12
10 & 12
10
SU:STA
HD:STA
SU:DAT
t
t
ns
Data in setup time
ns
t
Data in hold time
ns
10
HD:DAT
(5)
t
SCL LOW to SDA data out valid
Data out hold time
3500
ns
11
AA
(5)
t
50
ns
11
DH
(5)
t
Stop condition setup time
4700
4700
ns
10 & 12
10
SU:STO
(5)
t
Bus free time prior to new transmission
Write cycle time (nonvolatile write operation)
Wiper response time from stop generation
Wiper response from SCL LOW
ns
BUF
(5)
t
10
500
1000
50
ms
µs
13
WR
(5)
t
13
STPWV
(5)
t
µs
6
CLWV
t V
V power-up rate
CC
0.2
mV/µs
R
CC
Figure 10. Input Bus Timing
t
t
t
R
t
LOW
F
HIGH
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA
(Data in)
t
BUF
Figure 11. Output Bus Timing
SCL
t
t
DH
AA
SDA
(ACK)
SDA
OUT
SDA
SDA
OUT
OUT
Characteristics subject to change without notice. 13 of 18
REV 1.1.13 12/09/02
www.xicor.com
X9241A
Figure 12. Start Stop Timing
Start Condition
Stop Condition
SCL
t
t
t
HD:STA
SU:STO
SU:STA
SDA
(Data in)
Figure 13. Write Cycle and Wiper Response Timing
SCL
Clock 8
Clock 9
STOP
START
t
WR
t
STPWV
SDA
SDA
ACK
IN
Wiper
Output
Characteristics subject to change without notice. 14 of 18
REV 1.1.13 12/09/02
www.xicor.com
X9241A
PACKAGING INFORMATION
20-Lead Plastic Dual In-Line Package Type P
1.060 (26.92)
0.980 (24.89)
0.280 (7.11)
0.240 (6.096)
Pin 1 Index
Pin 1
—
0.900 (23.66)
Ref.
0.005 (0.127)
0.195 (4.95)
0.115 (2.92)
Seating
Plane
––
(3.81) 0.150
0.015 (0.38)
(2.92) 0.1150
0.10 (BSC)
(2.54)
0.022 (0.559)
0.014 (0.356)
0.070 (1.778)
0.045 (1.143)
0.300
(7.62) (BSC)
0°
15°
0.014 (0.356)
0.008 (0.2032)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 15 of 18
REV 1.1.13 12/09/02
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X9241A
PACKAGING INFORMATION
20-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.420 (10.65)
0.290 (7.37)
0.299 (7.60)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.496 (12.60)
0.508 (12.90)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0.420"
0°–8°
0.007 (0.18)
0.011 (0.28)
0.015 (0.40)
0.050 (1.27)
0.030" Typical
20 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 16 of 18
REV 1.1.13 12/09/02
www.xicor.com
X9241A
PACKAGING INFORMATION
20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.260 (6.6)
.252 (6.4)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 17 of 18
REV 1.1.13 12/09/02
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X9241A
Ordering Information
X9241A
Y
P
T
V
V
Limits
Device
CC
Blank = 5V 10ꢀ
Temperature Range
Blank = Commercial = 0 to +70°C
I = Industrial = –40 to +85°C
Package
P = 20-Lead Plastic DIP
S = 20-Lead SOIC
V = 20-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1 Pot 2 Pot 3
Y = 2K
2K
2K
2K
W = 10K 10K 10K 10K
U = 50K 50K 50K 50K
M = 2K 10K 10K 50K
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 18 of 18
REV 1.1.13 12/09/02
www.xicor.com
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