X9279TZ14I [XICOR]
Digital Potentiometer, 1 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PBGA14, BGA-14;
| 型号： | X9279TZ14I |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 1 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PBGA14, BGA-14 转换器 电阻器 |
| 文件： | 总24页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES AND DEVELOPMENT SYSTEM
A V A I L A B L E
AN99 • AN115 • AN124 •AN133 • AN134 • AN135
Single Supply / Low Power / 256-tap / 2-Wire Bus
X9279
Single Digitally-Controlled (XDCPTM) Potentiometer
FEATURES
DESCRIPTION
• 256 Resistor Taps
The X9279 integrates a single digitally controlled
• 2-Wire Serial Interface for write, read, and
transfer operations of the potentiometer
• Wiper Resistance, 100Ω typical @ 5V
• 16 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads SavedWiper Position on
Power Up.
potentiometer (XDCP) on
integrated circuit.
a
monolithic CMOS
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-Wire
bus interface. The potentiometer has associated with it
a volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers that can be directly written
to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
• Standby Current < 5µA Max
• V : 2.7V to 5.5V Operation
CC
• 50KΩ, 100KΩ versions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per
Register
• 100 yr. Data Retention
• 14-Lead TSSOP, xx-Lead XBGA
• Low Power CMOS
The XDCP can be used as
a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FUNCTIONAL DIAGRAM
V
R
H
CC
Write
Read
Address
Transfer
50KΩ and 100KΩ
Power On Recall
Data
Inc/Dec
256-taps
wiper
Status
Bus
Wiper Counter
Register (WCR)
2-Wire
Bus
Interface
POT
Interface
and Control
Data Registers
16 Bytes
Control
R
V
R
W
SS
L
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X9279
DETAILED FUNCTIONAL DIAGRAM
V
CC
Bank 0
Power On Recall
WIPER
R
H
DR0 DR1
50KΩ and 100KΩ
COUNTER
REGISTER
(WCR)
256-taps
R
R
L
SCL
DR2 DR3
INTERFACE
AND
CONTROL
SDA
A2
W
CIRCUITRY
A1
Bank 1
DR0
A0
Bank 2
Bank 3
DATA
DR1 DR0 DR1
DR0 DR1
WP
DR2 DR3 DR2 DR3
DR2 DR3
Control
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
V
SS
CIRCUIT LEVEL APPLICATIONS
SYSTEM LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable dc reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Control the gain in audio and home entertainment
systems
• Set the output voltage of a voltage regulator
• Provide the variable DC bias for tuners in RF wireless
systems
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the operating points in temperature control
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Control the operating point for sensors in industrial
systems
• Vary the frequency and duty cycle of timer ICs
• Trim offset and gain errors in artificial intelligent
systems
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
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X9279
PIN CONFIGURATION
XBGA
TSSOP
NC
X9279
14
1
2
3
4
5
6
7
V
CC
X9279
A0
R
R
R
13
12
11
10
L
NC
H
W
A2
SCL
NC
A1
WP
SDA
9
8
V
SS
PIN ASSIGNMENTS
Pin
(TSSOP)
Pin
(XBGA)
Symbol
NC
Function
1
2
No Connect
A0
Device Address for 2-Wire bus.
No Connect
3
NC
4
A2
Device Address for 2-Wire bus.
Serial Clock for 2-Wire bus.
Serial Data Input/Output for 2-Wire bus.
System Ground.
5
SCL
SDA
6
7
V
SS
8
WP
A1
Hardware Write Protect
9
Device Address for 2-Wire bus.
No Connect.
10
11
12
13
14
NC
R
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage.
W
R
H
R
L
V
CC
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X9279
PIN DESCRIPTIONS
Potentiometer Pins
R , R
Bus Interface Pins
H
L
The R and R pins are equivalent to the terminal
connections on a mechanical potentiometer.
H
L
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin
for a 2-Wire slave device and is used to transfer data
into and out of the device. It receives device address,
opcode, wiper register address and data sent from an
2-Wire master at the rising edge of the serial clock
SCL, and it shifts out data after each falling edge of the
serial clock SCL.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
) AND SUPPLY GROUND (V )
SS
It is an open drain output and may be wire-ORed with
any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor.
For selecting typical values, refer to the guidelines for
calculating typical values on the bus pull-up resistors
graph.
CC
The V pin is the system supply voltage. The V pin
CC
SS
is the system ground.
Other Pins
NO CONNECT
SERIAL CLOCK (SCL)
No connect pins should be left open. This pins are used
for Xicor manufacturing and testing purposes.
This input is used by 2-Wire master to supply 2-Wire
serial clock to the X9279.
HARDWARE WRITE PROTECT INPUT (WP)
DEVICE ADDRESS (A2 - A0)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
The Address inputs are used to set the least significant
3 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with
the X9279. A maximum of 8 devices may occupy the 2-
Wire serial bus.
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X9279
PRINCIPLES OF OPERATION
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256 switches
(see Table 1).
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter
and the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometers. This section provides detail
description of the following:
The WCR may be written directly. These Data
Registers can the WCR can be read and written by the
host system.
– Resistor Array Description.
Power Up and Down Recommendations.
– Serial Interface Description.
– Instruction and Register Description.
There are no restrictions on the power-up or power-
down conditions of V and the voltages applied to the
CC
potentiometer pins provided that V
is always more
CC
Array Description
positive than or equal to V , V , and V , i.e., V ≥ V ,
H L W CC H
V , V . The V ramp rate specification is always in
CC
effect.
The X9279 is comprised of a resistor array (see Figure
1). The array contains, in effect, 255 discrete resistive
segments that are connected in series. The physical
ends of each array are equivalent to the fixed terminals
L
W
of a mechanical potentiometer (R and R inputs).
H
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R ) output. Within each individual array only one
W
switch may be turned on at a time.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL
BUS
INPUT
SERIAL DATA PATH
R
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
(DR0)
REGISTER 1
(DR1)
8
8
PARALLEL
BUS
INPUT
E
R
BANK_0 Only
REGISTER 2
(DR2)
REGISTER 3
(DR3)
D
E
C
O
D
E
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
UP/DN
CLK
IF WCR = FF[H] THEN R = R
W
H
R
MODIFIED SCK
L
R
W
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X9279
SERIAL INTERFACE DESCRIPTION
Serial Interface
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 2.
The X9279 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9279 will be considered a
slave device in all applications.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 2.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9279 will respond with a final acknowledge.
See Figure 2.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9279 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 2.
Figure 2. Acknowledge Response from Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
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X9279
Acknowledge Polling
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte ( ID and A)
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9279
initiates the internal write cycle. ACK polling, Flow 1,
can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If
the X9279 is still busy with the write operation no ACK
will be returned. If the X9279 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
The first byte sent to the X9279 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device ID for the X9279; this is fixed as 0101[B] (refer
to Table 1).
The A[2:0] bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A2-A0 input pins. The slave address is
externally specified by the user. The X9279 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9279 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A2-A0 inputs can
FLOW 1: ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
be actively driven by CMOS input signals or tied to V
CC
or V
.
Issue
START
SS
Instruction Byte (I)
The next byte sent to the X9279 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode I [2:0]. The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9279 is single POT, the P0=0. The format is shown in
Table 2.
Issue Slave
Issue STOP
Address
ACK
No
Returned?
Yes
Register Bank Selection (RB, RA, P1, P0)
Further
No
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for Data Register to Wiper Counter
Register operations.
Operation?
Yes
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for 2-Wire write and read
operations. The Data Registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.
Issue
Issue STOP
Instruction
Proceed
Proceed
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X9279
Register Selection (R0 to R3) Table
Register
Register Bank Selection (Bank 0 to Bank 3) Table
Bank
RB RA Selection
Operations
P1 P0 Selection
Operations
0
0
1
1
0
1
0
1
0
1
2
3
Data Register Read and Write;
Wiper Counter Register
Operations
0
0
0
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write;
Wiper Counter Register
Operations
0
1
1
1
0
1
1
2
3
Data Register Read and Write
Only
Data Register Read and Write
Only
Data Register Read and Write;
Wiper Counter Register
Operations
Data Register Read and Write
Only
Data Register Read and Write;
Wiper Counter Register
Operations
Table 1. Identification Byte Format
Device Type
Identifier
Internal Slave
Address
Set to 0
for proper operation
ID3
0
ID2
1
ID1
0
ID0
1
0
A2
A1
A0
(MSB)
(LSB)
Table 2. Instruction Byte Format
P1 and P0 are used also for register Bank Selection
for 2-Wire Register Write and Read operations
Register
Selection
Instruction Opcode
Register Selection
Register Selected
RB
0
RA
0
I3
I2
I1
I0
RB
RA
P1
P0
DR0
DR1
DR2
DR3
0
1
(MSB)
(LSB)
1
0
1
1
Pot Selection (Bank Selection)
Set to P0=0 for potentiometer operations
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X9279
Table 3. Instruction Set
Instruction Set
Instruction
I3 I2 I1 I0 RB RA
P
P
Operation
1
0
Read Wiper Counter
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
0
0
0
Write new value to the Wiper Counter
Register
Read Data Register
1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed
to by P1-P0 and RB-RA
Write Data Register
1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1-P0 and RB-RA
XFR Data Register to
Wiper Counter Register
1/0 1/0
0
0
0
0
0
0
Transfer the contents of the Data Register
pointed to by RB-RA (Bank 0 only) to the Wiper
Counter Register
XFR Wiper Counter
Register to Data Register
1
0
1
0
1
1
0
0
1/0 1/0
Transfer the contents of the Wiper Counter
Register to the Register pointed to by RB-RA
(Bank 0 only)
Increment/Decrement
Wiper Counter Register
0
0
Enable Increment/decrement of the Wiper
Counter Register
Note: 1/0 = data is one or zero
DEVICE DESCRIPTION
different from the value present at power-down. Power-
up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR. The DR0
value of Bank 0 is the default value.
Wiper Counter Register (WCR)
The X9279 contains contains a Wiper Counter
Register, for the DCP potentiometer. The Wiper
Counter Register can be envisioned as a 8-bit parallel
and serial load counter with its outputs decoded to
select one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
Data Registers (DR)
The potentiometer has four 8-bit nonvolatile Data
Registers (DR3-DR0). These can be read or written
directly by the host. Data can also be transferred
between any of the four Data Registers and the
associated Wiper Counter Register. All operations
changing data in one of the Data Registers is a
nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9279 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
Bit [7:0] are used to store one of the 256 wiper
positions (0~255).
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X9279
Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
NV
Bit 6
NV
Bit 5
NV
Bit 4
NV
Bit 3
NV
Bit 2
NV
Bit 1
NV
Bit 0
NV
MSB
LSB
Instructions
Two instructions require a two-byte sequence to
complete. These instructions transfer data between the
host and the X9279; either between the host and one
of the data registers or directly between the host and
the Wiper Counter Register.These instructions are:
Four of the seven instructions are three bytes in length.
These instructions are:
– Read Wiper Counter Register – read the current
wiper position of the potentiometer,
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the Wiper Counter Register.
– Write Wiper Counter Register – change current
wiper position of the potentiometer,
– Read Data Register – read the contents of the
selected Data Register;
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the Wiper Counter
Register to the specified Data Register.
– Write Data Register – write a new value to the
selected Data Register.
The final command is Increment/Decrement (Figure 5
and 6). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the X9279 has responded with
an acknowledge, the master can clock the selected
wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by t
. A transfer
SCL clock pulse (t
) while SDA is HIGH, the
WRL
HIGH
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
selected wiper will move one resistor segment towards
the R terminal. Similarly, for each SCL clock pulse
H
minimum of t
to complete. The transfer can occur
while SDA is LOW, the selected wiper will move one
WR
between the potentiometer and one of its four
associated registers (Bank 0).
resistor segment towards the R terminal.
L
See Instruction format for more details.
Figure 3. Two-Byte Instruction Sequence
SCL
0
1
0
1
0
0
SDA
ID3 ID2 ID1 ID0
A2 A1 A0
S
T
A
R
T
0
A
C
K
RB RA P1
A
C
K
I3
I2
S
T
O
P
P0
I1 I0
Internal
Address
Device ID
Instruction
Opcode
Register
Address
Pot/Bank
Address
These commands only valid when P1=P0=0
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X9279
Figure 4. Three-Byte Instruction Sequence
SCL
0
1
0
1
0
0
SDA
ID1
S
T
A
R
T
ID3 ID2
ID0
A
C
K
I3
RB RA P1 P0
I0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
I1
I2
A2 A1 A0
Internal
Address
Pot/Bank
Register
Address
WCR[7:0] valid only when P1=P0=0;
or
Device ID
Instruction
Opcode
Address
Data Register D[7:0] for all values of P1 and P0
Figure 5. Increment/Decrement Instruction Squence
SCL
0
1
0
1
SDA
0
0
A2 A1 A0
ID3 ID2 ID1 ID0
Device ID
I3
I1
I2
I0
RB RA P1 P0
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
E
C
n
A
C
K
S
T
A
R
T
N
C
1
N
C
2
N
C
n
Internal
Address
Pot/Bank
Register
Address
Instruction
Opcode
Address
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
t
WRID
SCL
SDA
Voltage Out
V
/R
W
W
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X9279
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by X9279 on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
M S
A T
C O
K P
W W
C C
R R
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0 A 2 A 1 A 0
1 0 0 1 0 0 0 0
5
6
4 3 2 1 0
7
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by Master on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
S S
A T
C O
K P
W W
C C
R R
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0 A 2 A 1 A 0
1 0 1 0 0 0 0 0
5
6
4 3 2 1 0
7
Read Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by X9279 on SDA)
S
T
A
R
T
S
A
C
K
S
M S
A T
C O
K P
A
C
K
W W
C C
R R
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0 A 2 A 1 A 0
1
0
1
1 RB RA P1 P0
5
6
4 3 2 1 0
7
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
S (Sent by Master on SDA) S S
S
T
A
R
T
S
A
C
K
A
C
K
A T
C O
K P
W W
C C
R R
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0 A 2 A 1 A 0
1 1 0 0 RB RA P1 P0
5
6
4 3 2 1 0
7
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
S
A
C
K
S S
A T HIGH-VOLTAGE
C O WRITE CYCLE
K P
0
1
0
1
0 A 2 A 1 A 0
1 1 1 0 RB RA 0 0
Characteristics subject to change without notice. 12 of 24
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X9279
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
S
A
C
K
S S
A T
C O
K P
0
1
0
1
0 A 2 A 1 A 0
1 1 0 1 RB RA 0 0
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Increment/Decrement
(Sent by Master on SDA)
S
A
C
K
S
S
T
O
P
A
C
K
0
1
0
1
0 A 2 A 1 A 0
0
0
1
0
0
0
0
0
I/D I/D
.
.
.
.
I/D I/D
Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Characteristics subject to change without notice. 13 of 24
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X9279
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Voltage on SCL, SDA any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
with respect to V ..................................–1V to +7V
SS
∆V = | (V –V ) |.................................................... 5.5V
H
L
Lead temperature (soldering, 10 seconds)........ 300°C
I
(10 seconds)..................................................±6mA
W
RECOMMENDED OPERATING CONDITIONS
Device
X9279
Supply Voltage (V
)
(4) Limits
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
CC
5V ±10%
X9279-2.7
2.7V to 5.5V
–40°C
ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
End to End Resistance
End to End Resistance
End to End Resistance Tolerance
Power Rating
Min.
Typ.
100
50
Max.
Units
kΩ
kΩ
%
Test Conditions
T version
R
TOTAL
R
U version
TOTAL
±20
50
mW
mA
Ω
25°C, each pot
I
Wiper Current
±3
W
R
R
Wiper Resistance
300
150
I
I
= ± 3mA @ V = 3V
CC
W
W
Wiper Resistance
Ω
= ± 3mA @ V = 5V
CC
W
W
V
Voltage on any R or R Pin
V
V
V
V
= 0V
TERM
H
L
SS
CC
SS
Noise
-120
0.4
dBV/ Hz Ref: 1V
Resolution
%
(5)
Absolute Linearity (1)
±1
MI(3)
R – R
w(n)(actual) w(n)(expected)
(5)
Relative Linearity (2)
±0.2
MI(3)
R
– [R
]
w(n + 1)
w(n) + MI
Temperature Coefficient of
±300
ppm/°C
R
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitances
20
ppm/°C
pF
C /C /C
W
10/10/25
See Macro model
H
L
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (R – R ) / 255, single pot
H
L
(4) During power up V > V , V , and V .
CC
H
L
W
(5) n = 0, 1, 2, ....,255; m =0, 1, 2, ...., 254.
Characteristics subject to change without notice. 14 of 24
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X9279
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
= 400KHz; V = +6V;
SDA = Open; (for 2-Wire, Active, Read
and
I
I
I
V
supply current
(active)
3
mA
f
SCL
CC1
CC2
SB
CC
CC
V
supply current
(nonvolatile write)
5
5
mA
f
= 400KHz; V = +6V;
CC
SCL CC
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
V
current (standby)
µA
V
= +6V; V = V or V
;
CC
CC
IN
SS
CC
SDA = V ; (for 2-Wire, Standby State
CC
only)
I
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V
CC
LO
OUT
SS
V
V
V
V
V
x 0.7
V
+ 1
IH
CC
CC
–1
V
x 0.3
CC
V
IL
Output LOW voltage
Output HIGH voltage
0.4
V
I
= 3mA
OL
OL
OH
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Units
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Input / Output capacitance (SDA)
Input capacitance (SCL, WP, A2, A1 and A0)
Max.
Units
pF
Test Conditions
= 0V
(6)
IN/OUT
C
C
8
6
V
OUT
(6)
IN
pF
V
= 0V
IN
POWER-UP TIMING
Symbol
Parameter
V Power-up rate
CC
Min.
Max.
50
Units
V/ms
ms
(6)
CC
t V
0.2
r
(7)
PUR
t
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
(7)
PUW
50
ms
A.C. TEST CONDITIONS
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing level
10ns
V
x 0.5
CC
Notes: (6) This parameter is not 100% tested
(7) t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be
PUR
PUW
CC
issued.These parameters are periodically sampled and not 100% tested.
Characteristics subject to change without notice. 15 of 24
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X9279
EQUIVALENT A.C. LOAD CIRCUIT
SPICE Macromodel
5V
3V
1533Ω
R
867Ω
TOTAL
R
R
L
H
SDA pin
SDA pin
C
C
W
C
L
L
10pF
100pF
100pF
25pF
10pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
kHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
Clock Cycle Time
Clock High Time
Clock Low Time
Start Setup Time
Start Hold Time
Stop Setup Time
400
SCL
2500
600
1300
600
600
600
100
30
CYC
ns
HIGH
LOW
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT
R
ns
ns
ns
ns
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
ns
ns
300
300
0.9
ns
ns
F
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
µs
ns
AA
0
50
1200
0
DH
T
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1 Setup Time
ns
I
t
t
t
ns
BUF
ns
SU:WPA
HD:WPA
A0, A1 Hold Time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
Characteristics subject to change without notice. 16 of 24
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X9279
XDCP TIMING
Symbol
Parameter
Min.
Max.
10
Units
µs
t
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
5
5
WRPO
WRL
10
µs
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
.
Characteristics subject to change without notice. 17 of 24
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X9279
TIMING DIAGRAMS
Start and Stop Timing
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
Characteristics subject to change without notice. 18 of 24
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X9279
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
VWx
LSB
t
WRL
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(Any Instruction)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
Characteristics subject to change without notice. 19 of 24
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X9279
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
10KΩ
-12V
RL = {R /(R +R )} V (min)
L
1
1
2
O
Characteristics subject to change without notice. 20 of 24
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X9279
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R = R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
frequency R , R , C
1
2
amplitude R , R
A
B
Characteristics subject to change without notice. 21 of 24
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X9279
XX-ball BGA (X9279xxxxxxx)
a
a
l
j
m
k
b
b
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
d
= Die Orientation mark
c
e
Side View (Bump Side Down)
Millimeters
Inches
Symbol
Min
Nom.
Max
Min
Nom.
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
Ball Count X Axis
Ball Count Y Axis
Pins Pitch X Axis
j
Pins Pitch Y Axis
k
l
Edge to Ball Center (Corner)
Distance Along X
Edge to Ball Center (Corner)
Distance Along Y
m
Characteristics subject to change without notice. 22 of 24
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X9279
PACKAGING INFORMATION
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0∞– 8∞
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 23 of 24
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X9279
ORDERING INFORMATION
X9279
Y
P
T
V
V
Limits
CC
Device
Blank = 5V ±10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
V14 = 14-Lead SOIC
xxx = xxx-Lead XBGA
Potentiometer Organization
Pot
T =
100KΩ
PART MARK CONVENTION
xx Lead XBGA
X9279xxxx-2.7
X9279xxxx xx
X9279 xxxx
Top Mark
X9279xxxxx I-2.7
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 24 of 24
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