X9520Z20-B [XICOR]
Digital Potentiometer, 1 Func, PBGA20, BGA-20;
| 型号： | X9520Z20-B |
| 厂家： | 
XICOR INC. |
| 描述： | Digital Potentiometer, 1 Func, PBGA20, BGA-20 转换器 |
| 文件： | 总33页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hot Pluggable
Preliminary Information
X9520
Fiber Channel / Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Triple DCP, POR, 2 kbit EEPROM Memory, Dual Voltage Monitors
FEATURES
DESCRIPTION
• Three Digitally Controlled Potentiometers (DCPs)
—64 Tap - 10 kΩ
—100 Tap - 10 kΩ
—256 Tap - 100 kΩ
—Nonvolatile
The X9520 combines three Digitally Controlled Potentiome-
ters (DCPs), V1 / Vcc Power On Reset (POR) circuitry, two
programmable voltage monitor inputs with software and
hardware indicators, and integrated EEPROM with Block
LockTM protection. All functions of the X9520 are accessed
by an industry standard 2-Wire serial interface.
—Write Protect Function
• 2 kbit EEPROM Memory with Write Protect & Block
LockTM
• 2-Wire industry standard Serial Interface
—Complies to the Gigabit Interface Converter (GBIC)
specification
• Power On Reset (POR) Circuitry
—Programmable Threshold Voltage
—Software Selectable reset timeout
—Manual Reset
• Two Supplementary Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7 V to 5.5 V
Two of the DCPs of the X9520 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The third DCP may be used to set other vari-
ous reference quantities, or as a coarse trim for one of the
other two DCPs. The 2 kbit integrated EEPROM may be
used to store module definition data. The programmable
POR circuit may be used to ensure that V1 / Vcc is stable
before power is applied to the laser diode / module. The
programmable voltage monitors may be used for monitor-
ing various module alarm levels.
The features of the X9520 are ideally suited to simplifying
the design of fiber optic modules which comply to the Giga-
bit Interface Converter (GBIC) specification. The integration
of these functions into one package significantly reduces
board area, cost and increases reliability of laser diode
modules.
• Hot Pluggable
• 20 Pin packages
—XBGATM
—TSSOP
BLOCK DIAGRAM
R
R
R
H0
W0
L0
WIPER
COUNTER
REGISTER
8
6 - BIT
NONVOLATILE
MEMORY
WP
PROTECT LOGIC
R
R
R
H1
W1
L1
WIPER
COUNTER
REGISTER
CONSTAT
REGISTER
DATA
REGISTER
4
SDA
SCL
7 - BIT
NONVOLATILE
MEMORY
COMMAND
DECODE &
CONTROL
LOGIC
2 kbit
EEPROM
ARRAY
R
R
R
H2
W2
L2
WIPER
COUNTER
REGISTER
THRESHOLD
RESET LOGIC
MR
V3
2
8 - BIT
NONVOLATILE
MEMORY
V3RO
V2RO
V1RO
-
+
VTRIP3
VTRIP2
VTRIP1
V2
-
+
POWER ON /
LOW VOLTAGE
RESET
V1 / Vcc
+
-
GENERATION
©2000 Xicor Inc., Patents Pending
Characteristics subject to change without notice. 1 of 33
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X9520 – Preliminary Information
DETAILED DEVICE DESCRIPTION
output (V3RO, V2RO) are allowed to go HIGH. If the input
voltage becomes lower than it’s associated trip level, the
corresponding output is driven LOW. A corresponding
binary representation of the two monitor circuit outputs
(V2RO and V3RO) are also stored in latched, volatile
(CONSTAT) register bits. The status of these two monitor
outputs can be read out via the 2-wire serial port.
The X9520 combines three Xicor Digitally Controlled
Potentiometer (DCP) devices, V1 / Vcc power on reset
control, V1 / Vcc low voltage reset control, two supple-
mentary voltage monitors, and integrated EEPROM with
Block Lock™ protection, in one package. These functions
are suited to the control, support, and monitoring of vari-
ous system parameters in Fiber Channel / Gigabit Ether-
net fiber optic modules, such as in Gigabit Interface
Converter (GBIC) applications. The combination of the
X9520 fucntionality lowers system cost, increases reliabil-
ity, and reduces board space requirements using Xicor’s
unique XBGA™ packaging.
An application of the V1RO output may be to drive the
“ENABLE” input of a Laser Driver IC, with MR as a
“TX_DISABLE” input. V2RO and V3RO may be used to
monitor “TX_FAULT” and “RX_LOS” conditions respec-
tively.
Xicor’s unique circuits allow for all internal trip voltages to
be individually programmed with high accuracy. This
gives the designer great flexibility in changing system
parameters, either at the time of manufacture, or in the
field.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolu-
tion DCP may be used for setting sundry system parame-
ters such as maximum laser output power (for eye safety
requirements).
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s Block LockTM protection. This
memory may be used to store fiber optic module manu-
facturing data, serial numbers, or various other system
parameters. The EEPROM array is internally organized
as x 8, and utilizes Xicor’s proprietary Direct WriteTM cells,
providing a minimum endurance of 1,000,000 cycles and
a minimum data retention of 100 years.
Applying voltage to V
activates the Power On Reset
CC
circuit which allows the V1RO output to go HIGH, until the
supply the supply voltage stabilizes for a period of time
(selectable via software). The V1RO output then goes
LOW. The Low Voltage Reset circuitry allows the V1RO
output to go HIGH when V
falls below the minimum
CC
V
trip point. V1RO remains HIGH until V
returns to
CC
CC
The device features a 2-Wire interface and software pro-
tocol allowing operation on an I2C™ compatible serial
bus.
proper operating level. A Manual Reset (MR) input allows
the user to externally trigger the V1RO output (HIGH).
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware
PIN CONFIGURATION
XBGA
20 Pin TSSOP
1
2
3
4
V1 / Vcc
V1RO
R
20
19
18
17
H2
1
2
3
4
R
W2
V2
V1 / Vcc
V1RO
V3
R
W2
A
B
C
D
E
R
V3
V3RO
V2RO
V2
L2
R
R
H2
V3RO
W0
5
6
R
R
16
15
14
13
12
11
L0
H1
R
MR
WP
H0
MR
R
W0
R
V
R
WP
SDA
L0
SS
L2
7
8
R
R
H0
H1
SCL
R
V2RO
R
SCL
W1
L1
SDA
9
R
R
W1
L1
V
SS
10
Top View – Bumps Down
NOT TO SCALE
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X9520 – Preliminary Information
PIN ASSIGNMENT
Pin
1
XBGA
(C,2)
(B,1)
(D,1)
Name
Function
R
Connection to end of resistor array for (the 256 Tap) DCP 2.
H2
R
2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit.
w2
R
3
L2
When the V3 input is higher than the V
threshold voltage, V3RO makes a transition
4
5
(A,4)
(B,4)
V3
TRIP3
to a HIGH level. Connect V3 to V when not used.
SS
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than V
and goes LOW when V3 is less than VTRIP3. There is no delay cir-
V3RO
TRIP3
cuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) ini-
tiates a reset cycle to the V1RO pin (V1 / Vcc RESET Output pin). V1RO will remain HIGH
for time t
after MR has returned to it’s normally LOW state. The reset time can be se-
6
7
(C,3)
(C,4)
MR
purst
lected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use
of an external “pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write
Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” opera-
tions. Also, when the Write Protection is enabled, and the device Block Lock feature is ac-
tive (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile)
operations can be performed in the device (including the wiper position of any of the inte-
grated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down”
resistor, thus if left floating the write protection feature is disabled.
WP
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing
for data input and output.
8
9
(E,4)
(D,3)
SCL
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires
an external pull up resistor.
SDA
Vss
10
11
12
13
(D,2)
(D,4)
(A,3)
(B,3)
Ground.
R
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
Connection to end of resistor array for (the 100 Tap) DCP 1.
L1
R
w1
R
H1
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer
(DCP) 0.
R
14
(C,1)
H0
R
15
16
(E,2)
(E,3)
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
W0
R
L0
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit.
When the V2 input is greater than the V
threshold voltage, V2RO makes a transition
17
18
(A,1)
(E,1)
V2
TRIP2
to a HIGH level. Connect V2 to V when not used.
SS
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is
greater than V
, and goes LOW when V2 is less than V
. There is no power up
TRIP2
TRIP2
V2RO
reset delay circuitry on this pin. The V2RO pin requires the use of an external “pull-up”
resistor.
V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active
whenever V1 / Vcc falls below V
. V1RO becomes active on power up and remains
after the power supply stabilizes (t can be changed by varying
purst
TRIP1
active for a time t
purst
19
20
(B,2)
(A,2)
V1RO
the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use
of an external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the man-
ual reset (MR) input pin.
V1 / Vcc
Supply Voltage.
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X9520 – Preliminary Information
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1. Valid Data Changes on the SDA Bus
Serial Stop Condition
PRINCIPLES OF OPERATION
SERIAL INTERFACE
All communications must be terminated by a STOP con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place
the device into the Standby power mode after a read
sequence. A STOP condition can only be issued after the
transmitting device has released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides
the clock for both transmit and receive operations. There-
fore, the X9520 operates as a slave in all applications.
Serial Acknowledge
An ACKNOWLE DGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit-
ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL-
EDGE that it received the eight bits of data. Refer to Fig-
ure 3.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions. See
Figure 1.On power up of the X9520, the SDA pin is in the
input mode.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent
eight bit word.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will termi-
SCL
SDA
Start
Stop
Figure 2. Valid Start and Stop Conditions
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X9520 – Preliminary Information
SCL
from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
nate further data transmissions if an ACKNOWLEDGE is
not detected. The master must then issue a STOP condi-
tion to place the device into a known state.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111
selects the DCP structures in the X9520. The CON-
STAT Register may be selected using the Internal
Device Address 010.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
The user addressable internal components of the X9520
can be split up into three main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—Control and Status (CONSTAT) Register
SA7 SA6
SA3 SA2
SA5 SA4
SA1
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave
Address Byte being issued on the SDA pin. The Slave
address selects the part of the X9520 to be addressed,
and specifies if a Read or Write operation is to be per-
formed.
SA0
R/W
1 0 1 0
READ /
WRITE
INTERNAL
DEVICE
ADDRESS
DEVICE TYPE
IDENTIFIER
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 13.)
Internally Addressed
Device
Internal Address
(SA3 - SA1)
EEPROM Array
CONSTAT Register
DCP
000
010
111
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
Bit SA0
Operation
WRITE
0
1
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9520.
READ
Figure 4. Slave Address Format
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X9520 – Preliminary Information
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9520 ini-
tiates an internal high voltage write cycle. This cycle typi-
cally requires 5 ms. During this time, no further Read or
Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
R
N
Hx
WIPER
COUNTER
REGISTER
(WCR)
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
DECODER
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set
to either 1 or 0 in this case. If the device is still busy with
the high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation,
an ACKNOWLEDGE will be returned and the host can
then proceed with a read or write operation. (Refer to Fig-
ure 5.).
2
1
0
NON
VOLATILE
MEMORY
(NVM)
R
R
Lx
Wx
Figure 6. DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
Byte load completed
by issuing STOP.
Enter ACK Polling
The X9520 includes three independent resistor arrays.
These arrays respectively contain 63, 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
Issue START
Issue SlaveAddress
Byte (Read or Write)
terminals of a mechanical potentiometer (R and R
Hx
Lx
Issue STOP
inputs - where x = 0,1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
NO
ACK
returned?
(R ) output. Within each individual array, only one
x
w
switch may be turned on at any one time. These switches
are controlled by the Wiper Counter Register (WCR) (See
Figure 6). The WCR is a volatile register.
YES
On power up of the X9520, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The data in the WCR is
then decoded to select and enable one of the respective
FET switches. A “make before break” sequence is used
internally for the FET switches when the wiper is moved
from one tap position to another.
High Voltage Cycle
complete. Continue
command sequence?
NO
Issue STOP
YES
Continue normal
Read or Write
command sequence
Hot Pluggability
Figure 7 shows a typical waveform that the X9520 might
experience in a Hot Pluggable situation. On power up, V1
/ Vcc applied to the X9520 may exhibit some amount of
ringing, before it settles to the required value.
PROCEED
Figure 5.
Acknowledge Polling Sequence
Characteristics subject to change without notice. 6 of 33
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X9520 – Preliminary Information
V1 / Vcc
V1 / Vcc (Max.)
V
TRIP1
t
t
trans
purst
t
0
Maximum Wiper Recall time
Figure 7. DCP Power up
The device is designed such that the wiper terminal (R
)
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
Wx
is recalled to the correct position (as per the last stored in
the DCP NVM), when the voltage applied to V1 / Vcc
exceeds V
for a time exceeding t
(the Power
purst
TRIP1
On Reset time, set in the CONSTAT Register - See
“CONTROLAND STATUS REGISTER” on page 13.).
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
Therefore, if t
Vcc to settle above V
is defined as the time taken for V1 /
(Figure 7): then the desired
wiper terminal position is recalled by (a maximum) time:
is determined
trans
TRIP1
t
+ t
. It should be noted that t
trans purst trans
by system hot plug conditions.
DCP Operations
Instruction Byte
In total there are three operations that can be performed
on any internal DCP structure:
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit of
the Instruction Byte (I7), determines the Write Type (WT)
performed.
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after V1 / Vcc of
the X9520 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1 / Vcc to the
device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.
If WT is “1”, then a Nonvolatile Write to the DCP occurs.
In this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR
Characteristics subject to change without notice. 7 of 33
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X9520 – Preliminary Information
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9520 after the Slave Address, if it has
been received correctly.
I7
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
WT
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9520.
WRITE TYPE
DCP SELECT
WT†
Description
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
Following the Instruction Byte, a Data Byte is issued to
the X9520 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has been
issued on SDA (See Figure 34).
1
†
This bit has no effect when a Read operation is being performed.
Figure 8. Instruction Byte Format
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
and NVM. Therefore, the new “wiper position” setting is
recalled into the WCR after V1 / Vcc of the X9520 has
been powered down then powered back up
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when V1 / Vcc to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.
P1- P0
DCPx
x=0
# Taps
64
Max. Data Byte
0
0
1
1
0
1
0
1
3Fh
63h
FFh
x=1
100
x=2
256
Reserved
DCP Write Operation
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
A write to DCPx (x=0,1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Regis-
ter must first be set (See “BL1, BL0: Block Lock protection
bits - (Nonvolatile)” on page 13.)
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the “wiper position” of the DCP “wiper
terminal”. Therefore, the Data Byte 00001111 (15 ) cor-
10
responds to setting the “wiper terminal” to tap position 15.
Similarly, the Data Byte 00011100 (28 ) corresponds to
10
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Figure 9. DCP Write Command Sequence
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X9520 – Preliminary Information
WRITE Operation
READ Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Instruction
Byte
Slave
Slave
Address
a
r
a
r
Address
Data Byte
t
t
SDA Bus
P
0
10101110 W 00000 P1
10101111
T
A
C
K
A
C
K
A
C
K
DCPx
x = 0
Signals from
the Slave
-
-
-
x = 1
x = 2
“Dummy” write
LSB
MSB
“-” = DON’T CARE
Figure 10. DCP Read Sequence
setting the “wiper terminal” to tap position 28. The map-
ping of the Data Byte to “wiper position” data for DCP1
(100 Tap), is shown in “APPENDIX 1” . An example of a
simple C language function which “translates” between
the tap position (decimal) and the Data Byte (binary) for
DCP1, is given in “APPENDIX 2” .
DCP Read Operation
A read of DCPx (x=0,1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9520 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9520.
It should be noted that all writes to any DCP of the X9520
are random in nature. Therefore, the Data Byte of consec-
utive write operations to any DCP can differ by an arbi-
trary number of bits. Also, setting the bits P1=1, P0=1 is a
reserved sequence, and will result in no ACKNOWL-
EDGE after sending an Instruction Byte on SDA.
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” R
(x=0,1,2) at the
WX
“lowest” tap position, Therefore, the resistance between
and R is a minimum (essentially only the Wiper
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9520
issues an ACKNOWLEDGE followed by Data Byte, and
R
WX
LX
Resistance, R ).
W
S
t
a
r
t
WRITE Operation
S
t
o
p
Signals from
the Master
Address
Byte
Slave
Address
Data
Byte
SDA Bus
0 1
0 0
0
1
0 0
A
C
K
A
C
K
A
C
K
Internal
Signals from
the Slave
Device
Address
Figure 11. EEPROM Byte Write Sequence
Characteristics subject to change without notice. 9 of 33
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X9520 – Preliminary Information
S
t
S
t
o
p
(2 < n < 16)
Signals from
a
Address
Byte
the Master
Slave
Address
Data
(1)
Data
(n)
r
t
SDA Bus
0 1
0 0
0
1
0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. EEPROM Page Write Operation
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by bits
P1 and P0.
responds with an ACKNOWLEDGE. The master then ter-
minates the transfer by generating a STOP condition, at
which time the X9520 begins the internal write cycle to the
nonvolatile memory (See Figure 11). During this internal
write cycle, the X9520 inputs are disabled, so it does not
respond to any requests from the master. The SDA output
is at high impedance. A write to a region of EEPROM
memory which has been protected with the Block-Lock
feature (See “BL1, BL0: Block Lock protection bits - (Non-
volatile)” on page 13.), suppresses the ACKNOWLEDGE
bit after the Address Byte.
It should be noted that when reading out the data byte for
DCP0 (64 Tap), the upper two most significant bits are
“unknown” bits. For DCP1 (100 Tap), the upper most sig-
nificant bit is an “unknown”. For DCP2 (256 Tap) however,
all bits of the data byte are relevant (See Figure 10).
2 kbit EEPROM ARRAY
EEPROM Page Write
Operations on the 2 kbit EEPROM Array, consist of either
1, 2 or 3 byte command sequences. All operations on the
EEPROM must begin with the Device Type Identifier of
the Slave Address set to 1010000. A Read or Write to the
EEPROM is selected by setting the LSB of the Slave
Address to the appropriate value R/W (Read = “1”,
Wrtie=”0”).
In order to perform an EEPROM Page Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 13.)
The X9520 is capable of a page write operation. It is initi-
ated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
number of 8-bit bytes. After the receipt of each byte, the
X9520 responds with an ACKNOWLEDGE, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches the
end of the page, it “rolls over” and goes back to ‘0’ on the
same page.
In some cases when performing a Read or Write to the
EEPROM, an Address Byte may also need to be speci-
fied. This Address Byte can contain the values 00h to
FFh.
EEPROM Byte Write
In order to perform an EEPROM Byte Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 13.)
For example, if the master writes 12 bytes to the page
starting at location 11 (decimal), the first 5 bytes are writ-
ten to locations 11 through 15, while the last 7 bytes are
written to locations 0 through 6. Afterwards, the address
counter would point to location 7. If the master supplies
more than 16 bytes of data, then new data overwrites the
previous data, one byte at a time (See Figure 13).
For a write operation, the X9520 requires the Slave
Address Byte and an Address Byte. This gives the master
access to any one of the words in the array. After receipt
of the Address Byte, the X9520 responds with an
ACKNOWLEDGE, and awaits the next eight bits of data.
After receiving the 8 bits of the Data Byte, it again
Characteristics subject to change without notice. 10 of 33
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X9520 – Preliminary Information
S
S
t
o
p
t
Signals from
the Master
Slave
Address
a
r
t
SDA Bus
1
1
01 0 0 0 0
A
C
K
Signals from
the Slave
Data
Figure 14. Current EEPROM Address Read Sequence
The master terminates the Data Byte loading by issuing a
STOP condition, which causes the X9520 to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 12 for the address, ACKNOWLEDGE,
and data transfer sequence.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address n+1.
On power up, the address of the address counter is unde-
fined, requiring a read or write operation for initialization.
Stops and EEPROM Write Modes
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and receiving the subsequent ACKNOWLEDGE signal. If
the master issues a STOP within a Data Byte, or before
the X9520 issues a corresponding ACKNOWLEDGE, the
X9520 cancels the write operation. Therefore, the con-
tents of the EEPROM array does not change.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read opera-
tion, the master must either issue a STOP condition dur-
ing the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.
EEPROM Array Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current EEPROM Address Read, Random
EEPROM Read, and Sequential EEPROM Read.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to
5 bytes
5 bytes
7 bytes
address
1110
address
1510
address
= 610
address pointer
ends here
Addr = 710
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
Characteristics subject to change without notice. 11 of 33
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X9520 – Preliminary Information
READ Operation
WRITE Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Slave
Address
Address
Byte
Slave
Address
a
r
a
r
t
t
SDA Bus
0
1
1 0 1 0 0 0 0
10 1 0 0 0 0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
“Dummy” Write
Figure 15. Random EEPROM Address Read Sequence
a DCP or the CONSTAT Register (i.e.: an operation using
the Device Type Identifier 1010111 or 1010010). Immedi-
ately after an operation to a DCP or CONSTAT Register is
performed, only a “Random EEPROM Read” is avail-
able. Immediately following a “Random EEPROM Read” ,
a “Current EEPROM Address Read” or “Sequential
EEPROM Read” is once again available (assuming that
no access to a DCP or CONSTAT Register occur in the
interim).
After the X9520 acknowledges the receipt of the Address
Byte, the master immediately issues another START con-
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an ACKNOWLEDGE from the
X9520 and then by the eight bit word. The master termi-
nates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In this
case, the device sets the address pointer to that of the
Address Byte, and then goes into standby mode after the
STOP bit. All bus activity will be ignored until another
START is detected.
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master
issues the START condition and the Slave Address Byte,
receives an ACKNOWLEDGE, then issues an Address
Byte. This “dummy” Write operation sets the address
pointer to the address from which to begin the random
EEPROM read operation.
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data Byte
is transmitted as with the other modes; however, the mas-
S
Slave
Address
A
C
K
A
C
K
A
C
K
Signals from
the Master
t
o
p
SDA Bus
1
0 0 0
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Figure 16. Sequential EEPROM Read Sequence
Characteristics subject to change without notice. 12 of 33
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X9520 – Preliminary Information
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the entire
X9520 device. This bit must first be enabled before ANY
write operation (to DCPs, EEPROM memory array, or the
CONSTAT register). If the WEL bit is not first enabled,
then ANY proceeding (volatile or nonvolatile) write opera-
tion to DCPs, EEPROM array, as well as the CONSTAT
register, is aborted and no ACKNOWLEDGE is issued
after a Data Byte.
CS3
BL0
CS7 CS6
CS4
BL1
CS5
CS2 CS1 CS0
POR1
NV
V2OS V3OS
RWEL
WEL
POR0
NV
NV
NV
Bit(s)
Description
Write Enable Latch bit
WEL
RWEL
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by writ-
ing 00000010 to the CONSTAT register. Once enabled,
the WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CONSTAT register) or until
the X9520 powers down, and then up again.
Register Write Enable Latch bit
V2 Output Status flag
V2OS
V3OS
V3 Output Status flag
BL1 - BL0
Sets the Block Lock partition
POR1 - POR0 Sets the Power On Reset time
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed
in the CONSTAT Write command sequence (See Figure
18).
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 17. CONSTAT Register Format
ter now responds with an ACKNOWLEDGE, indicating it
requires additional data. The X9520 continues to output a
Data Byte for each ACKNOWLEDGE received. The mas-
ter terminates the read operation by not responding with
an ACKNOWLEDGE and instead issuing a STOP condi-
tion.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9520. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL),
the RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”) state.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through the entire
memory contents to be serially read during one operation.
At the end of the address space the counter “rolls over” to
address 00h and the device continues to output data for
each ACKNOWLEDGE received (Refer to Figure 16.).
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT Reg-
ister Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
CONTROL AND STATUS REGISTER
—After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure
18).
The Control and Status (CONSTAT) Register provides
the user with a mechanism for changing and reading the
status of various parameters of the X9520 (See Figure
17).
—When the X9520 is powered down.
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when V1 / Vcc is
powered down, then powered back up. The volatile bits
however, will always power up to a known logic state “0”
(irrespective of their value at power down).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used to:
—Inhibit a write operation from being performed to certain
addresses of the EEPROM memory array
A detailed description of the function of each of the CON-
STAT register bits follows:
—Inhibit a DCP write operation (changing the “wiper posi-
tion”).
Characteristics subject to change without notice. 13 of 33
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X9520 – Preliminary Information
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 18. CONSTAT Register Write Command Sequence
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1 and
BL0 bits written to the CONSTAT register. It is possible to
lock the regions of EEPROM memory shown in the table
below:
POR1, POR0: Power On Reset bits – (Nonvolatile)
Applying voltage to V activates the Power On Reset
CC
circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the V threshold for a period
TRIP1
(See Figure 30).
of time, t
PURST
Protected Addresses
(Size)
Partition of array
locked
The Power On Reset bits, POR1 and POR0 of the CON-
STAT register determine the t delay time of the
Power On Reset circuitry (See "VOLTAGE MONITORING
FUNCTIONS"). These bits of the CONSTAT register are
nonvolatile, and therefore power up to the last written
state.
BL1 BL0
PURST
0
0
1
1
0
1
0
1
None (Default)
None (Default)
Upper 1/4
Upper 1/2
All
C0h - FFh (64 bytes)
80h - FFh (128 bytes)
00h - FFh (256 bytes)
The nominal Power On Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
If the user attempts to perform a write operation on a pro-
tected region of EEPROM memory, the operation is
aborted without changing any data in the array.
Power on Reset delay (t
)
POR1 POR0
PUV1RO
When the Block Lock bits of the CONSTAT register are
set to something other than BL1=0 and BL0=0, then the
“wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
0
0
1
1
0
1
0
1
50ms
100ms (Default)
200ms
BL1 BL0
DCP Write Operation Permissible
300ms
0
0
1
1
0
1
0
1
YES (Default)
The default for these bits are POR1 = 0, POR0 = 1.
NO
NO
NO
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
The factory default setting for these bits are BL1 = 0, BL0
= 0.
At power up the VxOS (x=2,3) bits default to the value “0”.
These bits can be set to a “1” by writing the appropriate
value to the CONSTAT register. To provide consistency
between the VxRO and VxOS however, the status of the
VxOS bits can only be set to a “1” when the correspond-
ing VxRO output is HIGH.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9520 is active (HIGH), then all nonvolatile write opera-
tions to both the EEPROM memory and DCPs are inhib-
ited, irrespective of the Block Lock bit settings (See "WP:
Write Protection Pin").
Characteristics subject to change without notice. 14 of 33
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X9520 – Preliminary Information
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
typically take 5ms to complete. The RWEL bit is reset
by this cycle and the sequence must be repeated to
change the nonvolatile bits again. If bit 2 is set to ‘1’ in
this third step (qxys t11r) then the RWEL bit is set, but
the V2OS, V3OS, POR1, POR0, BL1 and BL0 bits
remain unchanged. Writing a second byte to the control
register is not allowed. Doing so aborts the write opera-
tion and the X9520 does not return an ACKNOWL-
EDGE.
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT register
requires an Address Byte which must be set to FFh. Only
one data byte is allowed to be written for each CONSTAT
register Write operation. The user must issue a STOP,
after sending this byte to the register, to initiate the non-
volatile cycle that stores the BP1, BP0, POR1 and POR0
bits. The X9520 will not ACKNOWLEDGE any data bytes
written after the first byte is entered (Refer to Figure 18.).
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all
of the nonvolatile bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin
of the X9520 is active (HIGH) (See "WP: Write Protection
Pin").
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with the
whole sequence requiring 3 steps
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 19).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each reg-
ister read operation. The X9520 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the Regis-
ter Write Enable Latch (RWEL) AND the WEL bit. This
is also a volatile cycle. The zeros in the data byte are
required. (Operation preceded by a START and ended
with a STOP).
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write opera-
tion.
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status (V2OS
and V3OS) bits, st are the Block Lock Protection (BL1
and BL0) bits, and qr are the Power On Reset delay
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9520. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires
the setting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain regions
time (t
) control bits (POR1 - POR0). This oper-
PUV1RO
ation is proceeded by a START and ended with a
STOP bit. Since this is a nonvolatile write cycle, it will
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA OUT
Figure 19. CONSTAT Register Read Command Sequence
Characteristics subject to change without notice. 15 of 33
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X9520 – Preliminary Information
of the EEPROM memory, as well as to all the DCPs. One
further level of data protection in the X9520, is incorpo-
rated in the form of the Write Protection pin.
V1 / Vcc
V
TRIP1
0 Volts
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9520.
MR
0 Volts
0 Volts
The table below (X9520 Write Permission Status) sum-
marizes the effect of the WP pin (and Block Lock), on the
write permission status of the device.
V1RO
Additional Data Protection Features
t
PURST
In addition to the preceding features, the X9520 also
incorporates the following data protection functionality:
Figure 20. Manual Reset Response
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
in software via the CONSTAT register (See “POR1,
POR0: Power On Reset bits – (Nonvolatile)” on
page 14.).
—Communication to the X9520 (via the 2-Wire interface)
is inhibited if V1 / Vcc is below the V
"V1 / Vcc Monitoring").
voltage (See
TRIP1
It should also be noted that all communication to the
device via the SDA and SCL pins is stopped and reset
while V1RO is HIGH. Also, setting the Manual Reset (MR)
pin HIGH overrides the Power On / Low Voltage circuitry
and forces the V1RO output pin HIGH (See "MR: Manual
Reset").
VOLTAGE MONITORING FUNCTIONS
V1 / Vcc Monitoring
The X9520 monitors the supply voltage and drives the
V1RO output HIGH (using an external “pull up” resistor)
MR: Manual Reset
if V1 / Vcc is lower than V
threshold. The V1RO
TRIP1
The V1RO output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connect-
ing a push-button directly from V1 / Vcc to the MR pin.
output will remain HIGH until V1 / Vcc exceeds V
TRIP1
for a minimum time of t
. After this time, the V1RO
PURST
pin is driven to a LOW state. See Figure 30.
For the Power On / Low Voltage Reset function of the
X9520, the V1RO output may be driven HIGH down to a
V1RO remains HIGH for time t
after MR has
PURST
returned to its LOW state (See Figure 20). An external
“pull down” resistor is required to hold this pin (nor-
mally) LOW.
V1 / Vcc of 1V (V
). See Figure 30. Another feature
RVALID
of the X9520, is that the value of t
may be selected
PURST
X9520 Write Permission Status
BlockLock
Bits
Write to CONSTAT Register
Permitted
DCP Volatile Write
Permitted
DCP Nonvolatile
Write Permitted
Write to EEPROM
Permitted
Nonvolatile
Bits
BL0 BL1 WP
Volatile Bits
YES
1
1
1
0
0
0
NO
NO
NO
NO
NO
NO
NO
YES
NO
NO
NO
NO
x
1
0
x
1
0
1
x
0
1
x
0
YES
YES
NO
NO
YES
NO
Not in locked region
Not in locked region
Yes (All Array)
YES
YES
YES
YES
NO
YES
YES
YES
Characteristics subject to change without notice. 16 of 33
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X9520 – Preliminary Information
V2 Monitoring
The X9520 asserts the V2RO output HIGH if the volt-
V
TRIPx
age V2 exceeds the corresponding V
threshold
Vx
TRIP2
0V
(See Figure 21). The bit V2OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
VxRO
0V
The V2RO output may remain active HIGH with V
down to 1V.
CC
V1 / Vcc
V3 Monitoring
V
TRIP1
0 Volts
(x = 2,3)
The X9520 asserts the V3RO output HIGH if the volt-
age V3 exceeds the corresponding V threshold
(See Figure 21). The bit V3OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
TRIP3
Figure 21. Voltage Monitor Response
The V3RO output may remain active HIGH with V
down to 1V.
CC
example, if the present V
is 2.9 V and the new
TRIPx
V
is 3.2 V, the new voltage can be stored directly
TRIPx
into the V
cell. If however, the new setting is to be
TRIPx
V
THRESHOLDS (X=1,2,3)
TRIPX
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
The X9520 is shipped with pre-programmed threshold
(V ) voltages. In applications where the required
TRIPx
TRIPx
thresholds are different from the default values, or if a
higher precision / tolerance is required, the X9520 trip
points may be adjusted by the user, using the steps
detailed below.
Setting a Higher V
Voltage (x=1,2,3)
TRIPx
To set a V
threshold to a new voltage which is
TRIPx
higher than the present threshold, the user must apply
the desired V threshold voltage to the corre-
TRIPx
sponding input pin (V1 / Vcc, V2 or V3). Then, a pro-
gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next,
issue on the SDA pin the Slave Address A0h, followed
Setting a V
Voltage (x=1,2,3)
TRIPx
There are two procedures used to set the threshold
voltages (V ), depending if the threshold voltage to
TRIPx
be stored is higher or lower than the present value. For
by the Byte Address 01h for V
, 09h for V
,
TRIP1
TRIP2
V
V1 / Vcc
V2, V3
TRIPx
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h
SDA
A0h †
†
Data Byte †
01h sets V
TRIP1
†
S
T
A
R
T
09h sets V
†
TRIP2
†
0Dh sets V
All others Reserved.
TRIP3
Figure 22. Setting V
to a higher level (x=1,2,3).
TRIPx
Characteristics subject to change without notice. 17 of 33
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X9520 – Preliminary Information
and 0Dh for V
, and a 00h Data Byte in order to
. The STOP bit following a valid write
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage (x=1,2,3).").
TRIP3
program V
TRIPx
operation initiates the programming sequence. Pin WP
must then be brought LOW to complete the operation
(See Figure 23). The user does not have to set the
WEL bit in the CONSTAT register before performing
this write sequence.
The desired threshold voltage is then applied to the
appropriate input pin (V1 / Vcc, V2 or V3) and the proce-
dure described in Section “Setting a Higher V
Voltage“ must be followed.
TRIPx
Setting a Lower V
Voltage (x=1,2,3).
TRIPx
Once the desired V
threshold has been set, the error
TRIPx
In order to set V
present value, then V
ing to the procedure described below. Once V
has been “reset”, then V
to a lower voltage than the
between the desired and (new) actual set threshold can
be determined. This is achieved by applying V1 / Vcc to
the device, and then applying a test voltage higher than
the desired threshold voltage, to the input pin of the volt-
TRIPx
must first be “reset” accord-
TRIPx
TRIPx
can be set to the desired
TRIPx
voltage using the procedure described in “Setting a
Higher V Voltage”.
age monitor circuit whose V
was programmed. For
TRIPx
example, if V
was set to a desired level of 3.0 V,
TRIPx
TRIP2
then a test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In the case of setting of V then
only V1 / Vcc need be applied. In all cases, care should
be taken not to exceed the maximum input voltage limits.
Resetting the V
Voltage (x=1,2,3).
TRIPx
TRIP1
To reset a V
voltage, apply the programming volt-
TRIPx
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
After applying the test voltage to the voltage monitor input
pin, the test voltage can be decreased (either in discrete
steps, or continuously) until the output of the voltage mon-
itor circuit changes state. At this point, the error between
the actual / measured, and desired threshold levels is cal-
culated.
V
, 0Bh for V
, and 0Fh for V
, followed
TRIP1
TRIP2
TRIP3
by 00h for the Data Byte in order to reset V
. The
TRIPx
STOP bit following a valid write operation initiates the
programming sequence. Pin WP must then be brought
LOW to complete the operation (See Figure 23).The
user does not have to set the WEL bit in the CONSTAT
register before performing this write sequence.
For example, the desired threshold for V
is set to
TRIP2
3.0 V, and a test voltage of 3.4 V was applied to the input
pin V2 (after applying power to V1 / Vcc). The input volt-
age is decreased, and found to trip the associated output
level of pin V2RO from a LOW to a HIGH, when V2
reaches 3.09 V. From this, it can be calculated that the
programming error is 3.09 - 3.0 = 0.09 V.
After being reset, the value of V
nal value of 1.7V.
becomes a nomi-
TRIPx
V
Accuracy (x=1,2,3).
TRIPx
The accuracy with which the V
thresholds are set,
TRIPx
can be controlled using the iterative process shown in
Figure 24.
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h †
SDA
A0h†
†
03h Resets VTRIP1
Data Byte
S
T
A
R
T
†
0Bh Resets VTRIP2
†
0Fh Resets VTRIP3
†
All others Reserved.
Figure 23. Resetting the V
Level
TRIPx
Characteristics subject to change without notice. 18 of 33
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X9520 – Preliminary Information
If the error between the desired and measured V
is
Continuing the previous example, we see that the calcu-
lated error was 0.09V. Since this is greater than zero, we
TRIPx
less than the maximum desired error, then the program-
ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
must first “reset” the V
threshold, then apply a volt-
TRIP2
age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
iteration of the V
programming sequence can be
TRIPx
performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.
must apply V
= 2.91 V to pin V2 and execute the
TRIP2
programming sequence (See "Setting a Higher VTRIPx
Voltage (x=1,2,3)").
If the calculated error is greater than zero, then the
V
must first be “reset”, and then programmed to the
Using this process, the desired accuracy for a particular
TRIPx
TRIPx
V
threshold may be attained using a successive
a value equal to the previously set V
minus the cal-
TRIPx
culated error. If it is the case that the error is less than
zero, then the V must be programmed to a value
number of iterations.
TRIPx
equal to the previously set V
of the calculated error.
plus the absolute value
TRIPx
Note: X = 1,2,3.
Let: MDE = Maximum Desired Error
V
Programming
TRIPx
NO
Desired V
<
TRIPx
present value?
YES
Execute
V
Reset
TRIPx
Sequence
Set Vx = desired V
TRIPx
Execute
TRIPx
Sequence
New Vx applied =
Old Vx applied - Error
New Vx applied =
Old Vx applied + Error
Set Higher V
Execute
Apply Vcc & Voltage
> Desired V to Vx
Reset V
TRIPx
TRIPx
Sequence
Decrease Vx
Output
switches?
NO
YES
Error + MDE
Error - MDE
Actual V
TRIPx
- Desired V
TRIPx
Error < MDE
DONE
Figure 24. V
Setting / Reset Sequence (x=1,2,3)
TRIPx
Characteristics subject to change without notice. 19 of 33
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X9520 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Parameter
Temperature under Bias
Min.
–65
–65
–1.0
–1.0
Max.
+135
+150
+15
Units
°C
°C
V
Storage Temperature
Voltage on WP pin (With respect to Vss)
Voltage on other pins (With respect to Vss)
+7
V
V1 / Vcc
5
V
| Voltage on R – Voltage on R | (x=0,1,2. Referenced to Vss)
D.C. Output Current (SDA,V1RO,V2RO,V3RO)
Hx
Lx
0
mA
°C
V
Lead Temperature (Soldering, 10 seconds)
300
Supply Voltage Limits (Applied V1 / Vcc voltage, referenced to Vss)
2.7
5.5
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Units
Industrial
–40
+85
°C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability
Figure 25. Equivalent A.C. Circuit
V1 / Vcc = 5V
2300Ω
SDA
V2RO
V3RO
100pF
V1RO
Figure 26. DCP SPICE Macromodel
R
TOTAL
R
R
Hx
Lx
C
L
C
H
10pF
R
W
C
10pF
W
25pF
(x=0,1,2)
R
Wx
Characteristics subject to change without notice. 20 of 33
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X9520 – Preliminary Information
TIMING DIAGRAMS
Figure 27. Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
A
DH
SDA OUT
Figure 28. WP Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
WP
t
t
HD:WP
SU:WP
Figure 29. Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
Characteristics subject to change without notice. 21 of 33
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X9520 – Preliminary Information
Figure 30. Power-Up and Power-Down Timing
t
t
F
R
V1 / Vcc
0 Volts
V
TRIP1
t
PURST
t
PURST
t
t
RPD
RPD
V1RO
0 Volts
MR
0 Volts
Figure 31. Manual Reset Timing Diagram
MR
t
MRPW
0 Volts
t
t
PURST
MRD
V1RO
0 Volts
V1 / Vcc
V1 / Vcc
V
TRIP1
Figure 32. V2, V3 Timing Diagram
t
t
Fx
Rx
Vx
V
TRIPx
t
t
RPDx
RPDx
t
RPDx
0 Volts
t
RPDx
VxRO
0 Volts
V1 / Vcc
V
TRIP1
V
RVALID
0 Volts
Note : x = 2,3.
Characteristics subject to change without notice. 22 of 33
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X9520 – Preliminary Information
Figure 33. V
Programming Timing Diagram (x=1,2,3).
TRIPX
V1 / Vcc, V2, V3
V
TRIPx
t
t
TSU
THD
V
P
WP
t
VPS
t
VPO
SCL
SDA
t
wc
00h
t
VPH
NOTE : V1/Vcc must be greater than V2, V3 when programming.
Figure 34. DCP “Wiper Position” Timing
Rwx (x=0,1,2)
R
wx(n+1)
R
wx(n)
R
wx(n-1)
t
wr
Time
n = tap position
SCL
SDA
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Characteristics subject to change without notice. 23 of 33
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X9520 – Preliminary Information
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min Typ
Max
Unit
Test Conditions / Notes
Current into V
Pin
CC
(X9520: Active)
Read memory array (3)
Write nonvolatile memory
f
= 400KHz
I
(1)
SCL
CC1
0.4
1.5
mA
V
= V
CC
SDA
Current into V
Pin
CC
MR = Vss
WP = Vss or Open/Floating
(X9520:Standby)
I
(2)
µA
CC2
30.0
30.0
With 2-Wire bus activity (3)
No 2-Wire bus activity
V
= V (when no bus
SCL
CC
activity else f
= 400kHz)
SCL
V
(4) = GND to V
CC.
0.1
0.1
10
1
µA
µA
Input Leakage Current (SCL, SDA, MR)
Input Leakage Current (WP)
IN
I
I
LI
V
(5) = GND to V
OUT
CC.
Output Leakage Current (SDA, V1RO,
V2RO, V3RO)
10
µA
LO
X9520 is in Standby(2)
V
V
V
Programming Range
2.75
1.8
4.70
4.70
V
V
TRIP1PR
TRIPxPR
TRIP1
TRIPx
V
V
Programming Range (x=2,3)
2.95 3.0
4.65 4.7
3.05
4.75
Factory shipped preset option A
Factory shipped preset option B
(6)
Pre - programmed V
Pre - programmed V
Pre - programmed V
threshold
threshold
threshold
V
V
V
TRIP1
TRIP1
TRIP2
TRIP3
1.75 1.8
2.95 3.0
1.85
3.05
Factory shipped preset option A
Factory shipped preset option B
V
(6)
TRIP2
1.75 1.8
2.95 3.0
1.85
3.05
Factory shipped preset option A
Factory shipped preset option B
V
(6)
TRIP3
V
=V
=V
V2 Input leakage current
V3 Input leakage current
1
1
SDA SCL CC
I
µA
Vx
Others=GND or V
CC
V
V
(7)
(7)
Input LOW Voltage (SCL, SDA, WP, MR)
Input HIGH Voltage (SCL,SDA, WP, MR)
-0.5
2.0
0.8
V
V
IL
V
CC
IH
+0.5
V1RO, V2RO, V3RO, SDA Output Low
Voltage
V
I
= 2.0mA
0.4
V
OLx
SINK
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200nS after a STOP ending a read operation; or t after a STOP ending a write operation.
WC
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
after a STOP that initiates
WC
a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4.
Notes: 5.
V
V
= Voltage applied to input pin.
IN
= Voltage applied to output pin.
OUT
Notes: 6. See “ORDERING INFORMATION” on page 33.
Notes: 7. Min. and V Max. are for reference only and are not tested
V
IL
IH
Characteristics subject to change without notice. 24 of 33
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X9520 – Preliminary Information
A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29)
400kHz
Symbol
Parameter
Min
0
Max
Units
KHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
400
SCL Clock Frequency
SCL
(5)
IN
50
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
µs
AA
µs
BUF
µs
LOW
µs
Clock HIGH Time
HIGH
µs
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
DH
µs
ns
µs
Data In Hold Time
0.6
50
µs
Stop Condition Setup Time
Data Output Hold Time
ns
(5)
R
300
300
ns
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
20 +.1Cb (2)
t (5)
F
ns
20 +.1Cb (2)
t
0.6
0
µs
SU:WP
t
µs
WP Hold Time
HD:WP
400
pF
Cb
Capacitive load for each bus line
A.C. TEST CONDITIONS
Input Pulse Levels
0.1V
to 0.9V
CC
CC
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
10ns
0.5V
CC
See Figure 25
NONVOLATILE WRITE CYCLE TIMING
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
t
(4)
5
10
ms
Nonvolatile Write Cycle Time
WC
CAPACITANCE (T = 25˚C, F = 1.0 MHZ, V
= 5V)
A
CC
Symbol
Parameter
Max
Units
Test Conditions
= 0V
V
C
C
(5)
Output Capacitance (SDA, V1RO, V2RO, V3RO)
Input Capacitance (SCL, WP, MR)
8
pF
OUT
OUT
V
= 0V
(5)
IN
6
pF
IN
Notes: 1. Typical values are for T = 25˚C and V = 5.0V
A
CC
Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4.
t
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
WC
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
Characteristics subject to change without notice. 25 of 33
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X9520 – Preliminary Information
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Min.
–20
Vss
Vss
Typ.
Max.
Units
%
Test Conditions/Notes
R
End to End Resistance Tolerance
+20
TOL
V
R
Terminal Voltage (x=0,1,2)
V
V
RHx
H
CC
V
R Terminal Voltage (x=0,1,2)
L
V
V
RLx
CC
R
= 10 KΩ (DCP0,
= 100 KΩ (DCP2)
TOTAL
10
5
mW
mW
Ω
DCP1)
P
R
Power Rating (1)
R
TOTAL
I
= 1mA, V = 5 V, V
=
W
CC
RHx
200
300
400
400
Vcc, V
= Vss (x=0,1,2).
RLx
I
= 1mA, V = 3.3 V, V
=
W
CC
RHx
R
DCP Wiper Resistance
700
Ω
W
Vcc, V
= Vss (x=0,1,2),
RLx
I
= 1mA, V = 2.7 V, V
=
W
CC
RHx
1000
1
Ω
Vcc, V
= Vss (x=0,1,2)
RLx
I
Wiper Current
Noise
mA
W
R
= 10 kΩ (DCP0,
mV /
TOTAL
sqt(Hz)
DCP1)
mV /
sqt(Hz)
R
= 100 kΩ (DCP2)
TOTAL
MI(4)
MI(4)
R
R
R
– R
-1
+1
Absolute Linearity (2)
Relative Linearity (3)
w(n)(actual)
w(n)(expected)
]
w(n)+MI
– [R
-0.2
+0.2
w(n+1)
= 10 kΩ (DCP0,
TOTAL
300
300
ppm/°C
DCP1)
R
Temperature Coefficient
TOTAL
R
= 100 kΩ (DCP2)
ppm/°C
pF
TOTAL
C /C /
Potentiometer Capacitances
Wiper Response time
10/10/
25
H
L
See Figure 26.
See Figure 34.
C
W
t
200
µs
wr
Notes: 1. Power Rating between the wiper terminal R
and the end terminals R or R - for ANY tap position n, (x=0,1,2).
HX LX
WX(n)
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R (actual) – R (expected)) = 1
wx(n) wx(n)
Ml Maximum (x=0,1,2).
Notes: 3. Relative Linearity is a measure of the error in step size between taps = R
– [R
+ Ml] = 0.2 Ml (x=0,1,2)
Wx(n+1)
wx(n)
Notes: 4. 1 Ml = Minimum Increment = R
/ (Number of taps in DCP - 1).
TOT
Notes: 5. Typical values are for T = 25°C and nominal supply voltage.
A
Notes: 6. This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 26 of 33
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X9520 – Preliminary Information
V
(X=1,2,3) PROGRAMMING PARAMETERS (See Figure 33)
TRIPX
Parameter
Description
Min
Typ
Max
Units
t
V
V
V
V
V
Program Enable Voltage Setup time
10
µs
VPS
TRIPx
TRIPx
TRIPx
TRIPx
TRIPx
t
Program Enable Voltage Hold time
Setup time
10
10
10
µs
µs
µs
VPH
t
TSU
t
Hold (stable) time
THD
Program Enable Voltage Off time
t
1
ms
VPO
(Between successive adjustments)
V Write Cycle time
TRIPx
t
5
10
15
ms
V
wc
V
P
10
Programming Voltage
Initial V Program Voltage accuracy
TRIPx
V
V
(1)
(1)
-0.1
+0.2
+25
+25
V
ta1
(Vx applied - V
) (Programmed at 25oC.)
TRIPx
TRIPx
Subsequent V
Program Voltage accuracy
-25
-25
+10
+10
mV
mV
ta2
V
[(Vx applied - V ) - V
. Programmed at 25oC.)
TRIPx
ta1
V
Program variation after programming (-40 - 85oC).
TRIP
tv
(Programmed at 25oC.)
Notes: 1. This parameter is not 100% tested.
Characteristics subject to change without notice. 27 of 33
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X9520 – Preliminary Information
V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 30, Figure 31, Figure 32)
Symbol
Description
Condition
Min.
25
Typ.
50
Max.
75
Units
ms
POR1= 0, POR0= 0
POR1= 0, POR0= 1
POR1= 1, POR0= 0
POR1= 1, POR0= 1
50
100
200
300
150
300
450
5
ms
t
Power On Reset delay time
PURST
100
150
ms
ms
t
t
(31)(2)
MR to V1RO propagation delay
MR pulse width
µs
See (1),(2),(4).
MRD
500
ns
MRDPW
V1 / Vcc, V2, V3 to V1RO,
V2RO, V3RO propagation
delay (respectively)
t
20
µs
RPDx
t
t
V1 / Vcc, V2, V3 Fall Time
V1 / Vcc, V2, V3 Rise Time
20
20
mV/µs
mV/µs
Fx
Rx
V1 / Vcc for V1RO, V2RO,
V3RO Valid (3).
V
1
V
RVALID
Notes: 1. See Figure 31 for timing diagram.
Notes: 2. See Figure 25 for equivalent load.
Notes: 3. This parameter describes the lowest possible V1 / Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with respect
to their inputs (V1 / Vcc, V2, V3).
Notes: 4. From MR rising edge crossing V , to V1RO rising edge crossing V
IH
.
OH
Characteristics subject to change without notice. 28 of 33
REV 1.0 7/20/00
www.xicor.com
X9520 – Preliminary Information
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0000 0000
0000 0001
0
1
0
1
.
.
.
.
.
.
0001 0111
0001 1000
0011 1000
0011 0111
23
24
25
26
23
24
56
55
.
.
.
.
.
.
0010 0001
0010 0000
0100 0000
0100 0001
48
49
50
51
33
32
64
65
.
.
.
.
.
.
0101 0111
0101 1000
0111 1000
0111 0111
73
74
75
76
87
88
120
119
.
.
.
.
.
.
0110 0001
0110 0000
98
99
97
96
Characteristics subject to change without notice. 29 of 33
REV 1.0 7/20/00
www.xicor.com
X9520 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example.
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned) wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned) wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned) wcr_val);
}
}
}
return((unsigned)01100000);
}
Characteristics subject to change without notice. 30 of 33
REV 1.0 7/20/00
www.xicor.com
X9520 – Preliminary Information
20 Ball BGA (X9520)
a
a
l
j
m
1
2
3
4
4
3
2
1
A
B
C
D
E
A
B
C
D
E
b
b
k
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
= Die Orientation mark
d
c
e
Side View (Bump Side Down)
Millimeters
Nom
Inches
Symbol
Min
Max
Min
Nom
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
2.566
3.836
0.510
0.395
0.110
0.250
2.591
3.861
0.570
0.430
0.140
0.28
2.616
3.886
0.630
0.465
0.170
0.310
0.10102
0.15102
0.02008
0.01555
0.00433
0.00984
0.10201
0.15201
0.02244
0.01693
0.00551
0.01102
0.10299
0.15299
0.02480
0.01831
0.00669
0.01220
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
20
4
Ball Count X Axis
Ball Count Y Axis
Pins Pitch XAxis
5
j
0.6
0.6
0.0236
0.0236
Pins Pitch Y Axis
k
Edge to Ball Center (Corner)
Distance Along X
l
0.365
0.700
0.395
0.730
0.425
0.760
0.01437
0.02756
0.01555
0.02874
0.01673
0.02992
Edge to Ball Center (Corner)
Distance Along Y
m
Characteristics subject to change without notice. 31 of 33
REV 1.0 7/20/00
www.xicor.com
X9520 – Preliminary Information
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.252 (6.4)
.300 (6.6)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
(7.72)
(4.16)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
(1.78)
(0.42)
.019 (.50)
.029 (.75)
DetailA (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 32 of 33
REV 1.0 7/20/00
www.xicor.com
X9520 – Preliminary Information
ORDERING INFORMATION
y
-
X9520
P
T
Preset (Factory Shipped) V
Threshold Levels (x=1,2,3)
TRIPx
Device
A = Optimized for 3.3 V system monitoring †
B = Optimized for 5 V system monitoring †
Temperature Range
Blank = Industrial = –40°C to +85°C
Package
V20 = 20-Lead TSSOP
Z20 = 20-Lead XBGA
XBGA PART MARK CONVENTION
20 Lead XBGA
X9520Z20A
X9520Z20B
Top Mark
TBD
TBD
†
For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc.
All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461;
4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880;
5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 33 of 33
REV 1.0 7/20/00
www.xicor.com
相关型号：
X9521B20I
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