X9522Z20-A [XICOR]
Telecom Circuit, 1-Func, PBGA20, BGA-20;
| 型号： | X9522Z20-A |
| 厂家： | 
XICOR INC. |
| 描述： | Telecom Circuit, 1-Func, PBGA20, BGA-20 电信 电信集成电路 |
| 文件： | 总29页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hot Pluggable
Preliminary Information
X9522
Laser Diode Control for Fiber Optic Modules
Triple DCP, Dual Voltage Monitors
FEATURES
DESCRIPTION
• Three Digitally Controlled Potentiometers (DCPs)
—64 Tap - 10 kΩ
—100 Tap - 10 kΩ
—256 Tap - 100 kΩ
—Nonvolatile
The X9522 combines three Digitally Controlled Potentiome-
ters (DCPs), and two programmable voltage monitor inputs
with software and hardware indicators. All functions of the
X9522 are accessed by an industry standard 2-Wire serial
interface.
—Write Protect Function
• 2-Wire industry standard Serial Interface
• Dual Voltage Monitors
—Programmable Threshold Voltages
• Single Supply Operation
—2.7 V to 5.5 V
Two of the DCPs of the X9522 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The third DCP may be used to set other vari-
ous reference quantities, or as a coarse trim for one of the
other two DCPs.The programmable voltage monitors may
be used for monitoring various module alarm levels.
• Hot Pluggable
• 20 Pin packages
The features of the X9522 are ideally suited to simplifying
the design of fiber optic modules. The integration of these
functions into one package significantly reduces board
area, cost and increases reliability of laser diode modules.
—XBGATM
—TSSOP
BLOCK DIAGRAM
R
R
R
H0
W0
L0
WIPER
COUNTER
REGISTER
8
6 - BIT
NONVOLATILE
MEMORY
WP
PROTECT LOGIC
R
R
R
H1
W1
L1
WIPER
COUNTER
REGISTER
DATA
REGISTER
SDA
7 - BIT
NONVOLATILE
MEMORY
COMMAND
DECODE &
CONSTAT
REGISTER
CONTROL
SCL
LOGIC
R
R
R
H2
W2
L2
WIPER
COUNTER
REGISTER
THRESHOLD
RESET LOGIC
2
8 - BIT
NONVOLATILE
MEMORY
V3RO
V2RO
V3
V2
-
+
VTRIP3
VTRIP2
-
+
Vcc / V1
©2000 Xicor Inc., Patents Pending
Characteristics subject to change without notice. 1 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
DETAILED DEVICE DESCRIPTION
exceeds it’s associated trip level, a hardware output
(V3RO, V2RO) are allowed to go HIGH. If the input volt-
age becomes lower than it’s associated trip level, the cor-
responding output is driven LOW. A corresponding binary
representation of the two monitor circuit outputs (V2RO
and V3RO) are also stored in latched, volatile (CON-
STAT) register bits. The status of these two monitor out-
puts can be read out via the 2-wire serial port.
The X9522 combines three Xicor Digitally Controlled
Potentiometer (DCP) devices, and two voltage monitors,
in one package. These functions are suited to the control,
support, and monitoring of various system parameters in
fiber optic modules. The combination of the X9522 fucn-
tionality lowers system cost, increases reliability, and
reduces board space requirements using Xicor’s unique
XBGA™ packaging.
Xicor’s unique circuits allow for all internal trip voltages to
be individually programmed with high accuracy. This
gives the designer great flexibility in changing system
parameters, either at the time of manufacture, or in the
field.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolu-
tion DCP may be used for setting sundry system parame-
ters such as maximum laser output power (for eye safety
requirements).
The device features a 2-Wire interface and software pro-
tocol allowing operation on an I2C™ compatible serial
bus.
The dual Voltage Monitor circuits continuously compare
their inputs to individual trip voltages. If an input voltage
PIN CONFIGURATION
XBGA
20 Pin TSSOP
1
2
3
4
Vcc / V1
NC
R
R
20
19
18
17
H2
1
2
3
4
Vcc / V1
NC
W2
V2
V3
R
W2
A
B
C
D
E
R
V3
V3RO
V2RO
V2
L2
R
R
H2
V3RO
W0
5
6
R
R
16
15
14
13
12
11
L0
H1
R
NC
WP
H0
NC
R
W0
R
V
R
WP
SDA
L0
SS
L2
7
8
R
R
H0
H1
SCL
R
V2RO
R
SCL
W1
L1
SDA
9
R
R
W1
L1
V
SS
10
Top View – Bumps Down
NOT TO SCALE
Characteristics subject to change without notice. 2 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
PIN ASSIGNMENT
Pin
1
XBGA
(C,2)
(B,1)
(D,1)
Name
Function
R
Connection to end of resistor array for (the 256 Tap) DCP 2.
H2
R
2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit.
w2
R
3
L2
When the V3 input is higher than the V
threshold voltage, V3RO makes a transition
4
(A,4)
V3
TRIP3
to a HIGH level. Connect V3 to V when not used.
SS
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than V
and goes LOW when V3 is less than
. There is no delay cir-
5
6
(B,4)
(C,3)
V3RO
NC
TRIP3
TRIP3
cuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
No Connect
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write
Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” opera-
tions. Also, when the Write Protection is enabled, and the DCP Write Lock feature is active
(i.e. the DCP Write Lock bit is set to “1”), then no “write” (volatile or nonvolatile) operations
can be performed in the device (including the wiper position of any of the integrated Digitally
Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus
if left floating the write protection feature is disabled.
7
(C,4)
WP
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing
for data input and output.
8
9
(E,4)
(D,3)
SCL
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires
an external pull up resistor.
SDA
Vss
10
11
12
13
(D,2)
(D,4)
(A,3)
(B,3)
Ground.
R
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
Connection to end of resistor array for (the 100 Tap) DCP 1.
L1
R
w1
R
H1
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer
(DCP) 0.
R
14
(C,1)
H0
R
15
16
(E,2)
(E,3)
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
W0
R
L0
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit.
When the V2 input is greater than the V
threshold voltage, V2RO makes a transition
17
18
(A,1)
(E,1)
V2
TRIP2
to a HIGH level. Connect V2 to V when not used.
SS
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is
greater than V
, and goes LOW when V2 is less than V
. There is no power up
TRIP2
TRIP2
V2RO
reset delay circuitry on this pin. The V2RO pin requires the use of an external “pull-up”
resistor.
19
20
(B,2)
(A,2)
NC
No Connect
Vcc / V1
Supply Voltage.
Characteristics subject to change without notice. 3 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1. Valid Data Changes on the SDA Bus
Serial Stop Condition
PRINCIPLES OF OPERATION
SERIAL INTERFACE
All communications must be terminated by a STOP con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place
the device into the Standby power mode after a read
sequence. A STOP condition can only be issued after the
transmitting device has released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides
the clock for both transmit and receive operations. There-
fore, the X9522 operates as a slave in all applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit-
ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL-
EDGE that it received the eight bits of data. Refer to Fig-
ure 3.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions. See
Figure 1.On power up of the X9522, the SDA pin is in the
input mode.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent
eight bit word.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data. The device will termi-
SCL
SDA
Start
Stop
Figure 2. Valid Start and Stop Conditions
Characteristics subject to change without notice. 4 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
SCL
from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
nate further data transmissions if an ACKNOWLEDGE is
not detected. The master must then issue a STOP condi-
tion to place the device into a known state.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally selects
the DCP structures in the X9522. The CONSTAT Reg-
ister may be selected using the Internal Device Address
010.All other bit combinations are RESERVED.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
The user addressable internal components of the X9522
can be split up into two main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave
Address Byte being issued on the SDA pin. The Slave
address selects the part of the X9522 to be addressed,
and specifies if a Read or Write operation is to be per-
formed.
SA7 SA6
SA3 SA2
SA5 SA4
SA1
SA0
R/W
1 0 1 0
READ /
WRITE
INTERNAL
DEVICE
ADDRESS
DEVICE TYPE
IDENTIFIER
It should be noted that in order to perform a write opera-
tion to a DCP, the Write Enable Latch (WEL) bit must first
be set.
Internally Addressed
Device
Internal Address
(SA3 - SA1)
CONSTAT Register
DCP
010
111
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
RESERVED
Others
Bit SA0
Operation
WRITE
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9522.
0
1
READ
Figure 4. Slave Address Format
Characteristics subject to change without notice. 5 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the Non Volatile Memory of a DCP (NVM), or the CON-
STAT Register) has been correctly issued (including the
final STOP condition), the X9522 initiates an internal high
voltage write cycle. This cycle typically requires 5 ms.
During this time, no further Read or Write commands can
be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
R
N
Hx
WIPER
COUNTER
REGISTER
(WCR)
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
DECODER
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set
to either 1 or 0 in this case. If the device is still busy with
the high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation,
an ACKNOWLEDGE will be returned and the host can
then proceed with a read or write operation. (Refer to Fig-
ure 5.).
2
1
0
NON
VOLATILE
MEMORY
(NVM)
R
R
Lx
Wx
Figure 6. DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
Byte load completed
by issuing STOP.
Enter ACK Polling
The X9522 includes three independent resistor arrays.
These arrays respectively contain 63, 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R and R
Issue START
Issue SlaveAddress
Byte (Read or Write)
Hx
Lx
Issue STOP
inputs - where x = 0,1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
NO
ACK
returned?
(R ) output. Within each individual array, only one
x
w
switch may be turned on at any one time. These switches
are controlled by the Wiper Counter Register (WCR) (See
Figure 6). The WCR is a volatile register.
YES
On power up of the X9522, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The data in the WCR is
then decoded to select and enable one of the respective
FET switches. A “make before break” sequence is used
internally for the FET switches when the wiper is moved
from one tap position to another.
High Voltage Cycle
complete. Continue
command sequence?
NO
Issue STOP
YES
Continue normal
Read or Write
command sequence
Hot Pluggability
Figure 7 shows a typical waveform that the X9522 might
experience in a Hot Pluggable situation. On power up,
Vcc / V1 applied to the X9522 may exhibit some amount
of ringing, before it settles to the required value.
PROCEED
Figure 5.
Acknowledge Polling Sequence
Characteristics subject to change without notice. 6 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
Vcc
Vcc (Max.)
V
TRIP
t
t
trans
pu
t
0
Maximum Wiper Recall time
Figure 7. DCP Power up
The device is designed such that the wiper terminal (R
is recalled to the correct position (as per the last stored in
the DCP NVM), when the voltage applied to Vcc / V1
)
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
Wx
exceeds V
for a time exceeding t
pu.
TRIP
Therefore, if t
is defined as the time taken for Vcc /
(Figure 7): then the desired
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
trans
V1 to settle above V
TRIP
wiper terminal position is recalled by (a maximum) time:
is determined by
t
+ t . It should be noted that t
trans
trans pu
system hot plug conditions.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
Instruction Byte
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit of
the Instruction Byte (I7), determines the Write Type (WT)
performed.
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after Vcc / V1 of
the X9522 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when Vcc / V1 to the
device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.
If WT is “1”, then a Nonvolatile Write to the DCP occurs.
In this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR
and NVM. Therefore, the new “wiper position” setting is
recalled into the WCR after Vcc / V1 of the X9522 has
been powered down then powered back up
Characteristics subject to change without notice. 7 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9522.
I7
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
WT
WRITE TYPE
DCP SELECT
Following the Instruction Byte, a Data Byte is issued to
the X9522 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has been
issued on SDA (See Figure 25).
WT†
Description
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
1
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
†
This bit has no effect when a Read operation is being performed.
Figure 8. Instruction Byte Format
P1- P0
DCPx
x=0
# Taps
64
Max. Data Byte
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when Vcc / V1 to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.
0
0
1
1
0
1
0
1
3Fh
63h
FFh
x=1
100
x=2
256
Reserved
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
DCP Write Operation
A write to DCPx (x=0,1,2) can be performed using the
three byte command sequence shown in Figure 9.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the “wiper position” of the DCP “wiper
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Regis-
ter must first be set (See “WEL: Write Enable Latch (Vola-
tile)” on page 10.)
terminal”. Therefore, the Data Byte 00001111 (15 ) cor-
10
responds to setting the “wiper terminal” to tap position 15.
Similarly, the Data Byte 00011100 (28 ) corresponds to
10
setting the “wiper terminal” to tap position 28. The map-
ping of the Data Byte to “wiper position” data for DCP1
(100 Tap), is shown in “APPENDIX 1”. An example of a
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9522 after the Slave Address, if it has
been received correctly.
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Figure 9. DCP Write Command Sequence
Characteristics subject to change without notice. 8 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
WRITE Operation
READ Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Instruction
Byte
Slave
Slave
Address
a
r
a
r
Address
Data Byte
t
t
SDA Bus
P
0
10101110 W 00000 P1
10101111
T
A
C
K
A
C
K
A
C
K
DCPx
x = 0
Signals from
the Slave
-
-
-
x = 1
x = 2
“Dummy” write
LSB
MSB
“-” = DON’T CARE
Figure 10. DCP Read Sequence
simple C language function which “translates” between
the tap position (decimal) and the Data Byte (binary) for
DCP1, is given in “APPENDIX 2”.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9522
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by bits
P1 and P0.
It should be noted that all writes to any DCP of the X9522
are random in nature. Therefore, the Data Byte of consec-
utive write operations to any DCP can differ by an arbi-
trary number of bits. Also, setting the bits P1=1, P0=1 is a
reserved sequence, and will result in no ACKNOWL-
EDGE after sending an Instruction Byte on SDA.
It should be noted that when reading out the data byte for
DCP0 (64 Tap), the upper two most significant bits are
“unknown” bits. For DCP1 (100 Tap), the upper most sig-
nificant bit is an “unknown”. For DCP2 (256 Tap) however,
all bits of the data byte are relevant (See Figure 10).
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” R
(x=0,1,2) at the
WX
“lowest” tap position, Therefore, the resistance between
and R is a minimum (essentially only the Wiper
R
WX
LX
CONTROL AND STATUS REGISTER
Resistance, R ).
W
The Control and Status (CONSTAT) Register provides
the user with a mechanism for changing and reading the
status of various parameters of the X9522 (See Figure
11).
DCP Read Operation
A read of DCPx (x=0,1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when Vcc / V1 is
powered down, then powered back up. The volatile bits
however, will always power up to a known logic state “0”
(irrespective of their value at power down).
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9522 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9522.
A detailed description of the function of each of the
CONSTAT register bits follows:
Characteristics subject to change without notice. 9 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT Reg-
ister Write Operation").
CS3
CS7 CS6
CS4
0
CS5
CS2 CS1 CS0
0
V2OS V3OS
DWLK RWEL
NV
WEL
0
The RWEL bit will reset itself to the default “0” state, in
one of two cases:
—After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure
12).
Bit(s)
Description
CS7
V2OS
V3OS
CS4
Always set to “0” (RESERVED)
V2 Output Status flag
—When the X9522 is powered down.
V3 Output Status flag
DWLK: DCP Write Lock bit - (Nonvolatile)
Always set to “0” (RESERVED)
Sets the DCP Write Lock
Register Write Enable Latch bit
Write Enable Latch bit
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
DWLK
RWEL
WEL
When the DCP Write Lock bit of the CONSTAT register is
set to “1”, then the “wiper position” of the DCPs cannot be
changed - i.e. DCP write operations cannot be con-
ducted:
CS0
Always set to “0” (RESERVED)
NOTE: Bits belled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
DWLK
DCP Write Operation Permissible
Figure 11. CONSTAT Register Format
0
1
YES (Default)
NO
WEL: Write Enable Latch (Volatile)
The factory default setting for this bit is DWLK= 0.
The WEL bit controls the Write Enable status of the entire
X9522 device. This bit must first be enabled before ANY
write operation (to DCPs, or the CONSTAT register). If the
WEL bit is not first enabled, then ANY proceeding (volatile
or nonvolatile) write operation to DCPs, or the CONSTAT
register, is aborted and no ACKNOWLEDGE is issued
after a Data Byte.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9522 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by writ-
ing 00000010 to the CONSTAT register. Once enabled,
the WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CONSTAT register) or until
the X9522 powers down, and then up again.
At power up the VxOS (x=2,3) bits default to the value “0”.
These bits can be set to a “1” by writing the appropriate
value to the CONSTAT register. To provide consistency
between the VxRO and VxOS however, the status of the
VxOS bits can only be set to a “1” when the correspond-
ing VxRO output is HIGH.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed
in the CONSTAT Write command sequence (See Figure
12).
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
RWEL: Register Write Enable Latch (Volatile)
—The corresponding VxRO output becomes LOW.
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9522. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL),
the RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”) state.
Characteristics subject to change without notice. 10 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 12. CONSTAT Register Write Command Sequence
CONSTAT Register Write Operation
—Write a 06H to the CONSTAT Register to set the Regis-
ter Write Enable Latch (RWEL) AND the WEL bit. This
is also a volatile cycle. The zeros in the data byte are
required. (Operation preceded by a START and ended
with a STOP).
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT register
requires an Address Byte which must be set to FFh. Only
one data byte is allowed to be written for each CONSTAT
register Write operation. The user must issue a STOP,
after sending this byte to the register, to initiate the non-
volatile cycle that stores the DWLK bit. The X9522 will not
ACKNOWLEDGE any data bytes written after the first
byte is entered (Refer to Figure 12.).
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as 0xy0t010 in binary,
where xy are the Voltage Monitor Output Status (V2OS
and V3OS) bits, and t is the DCP Write Lock (DWLK)
bit. This operation is proceeded by a START and ended
with a STOP bit. Since this is a nonvolatile write cycle, it
will typically take 5ms to complete. The RWEL bit is
reset by this cycle and the sequence must be repeated
to change the nonvolatile bits again. If bit 2 is set to ‘1’
in this third step (0xy0 t110) then the RWEL bit is set,
but the DWLK bit will remain unchanged. Writing a sec-
ond byte to the control register is not allowed. Doing so
aborts the write operation and the X9522 does not
return an ACKNOWLEDGE.
When writing to the CONSTAT register, the bits CS7, CS4
and CS0 must all be set to “0”. Writing any other bit
sequence to bits CS7, CS4 and CS0 of the CONSTAT
register is reserved.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with the
whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset the
nonvolatile (DWLK) bit in the CONSTAT Register to “0”.
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA OUT
Figure 13. CONSTAT Register Read Command Sequence
Characteristics subject to change without notice. 11 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
It should be noted that a write to nonvolatile bit (DWLK) of
CONSTAT register will be ignored if the Write Protect pin
of the X9522 is active (HIGH) (See "WP: Write Protection
Pin").
V
TRIPx
Vx
0V
CONSTAT Register Read Operation
VxRO
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 13).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each regis-
ter read operation. The X9522 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
0V
Vcc / V1
V
TRIP
0 Volts
(x = 2,3)
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write opera-
tion.
Figure 14. Voltage Monitor Response
Additional Data Protection Features
When reading the contents of the CONSTAT register, the
bits CS7, CS4 and CS0 will always return “0”.
In addition to the preceding features, the X9522 also
incorporates the following data protection functionality:
DATA PROTECTION
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
There are a number of levels of data protection features
designed into the X9522. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires the
setting of the RWEL bit. The DCP Write Lock of the
device enables the user to inhibit writes to all DCPs. One
further level of data protection in the X9522, is incorpo-
rated in the form of the Write Protection pin.
—Communication to the X9522 (via the 2-Wire interface)
is inhibited if Vcc / V1 is below the V
.
TRIP
VOLTAGE MONITORING FUNCTIONS
V2 monitoring
The X9522 asserts the V2RO output HIGH if the volt-
WP: Write Protection Pin
age V2 exceeds the corresponding V
threshold
TRIP2
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9522.
(See Figure 14). The bit V2OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The table below (X9522 Write Permission Status) sum-
marizes the effect of the WP pin (and DCP Write Lock),
on the write permission status of the device.
The V2RO output may remain active HIGH with Vcc
down to 1V.
X9522 Write Permission Status
Write to CONSTAT Register
DWLK
WP
Permitted
(DCP Write Lock (Write Protect pin DCP Volatile Write
DCP Nonvolatile
bit status)
status)
Permitted
Write Permitted
Volatile Bits
YES
Nonvolatile Bits
1
1
0
0
NO
NO
NO
NO
NO
1
0
1
0
YES
YES
NO
NO
YES
YES
YES
YES
YES
YES
Characteristics subject to change without notice. 12 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
V
TRIPx
V2, V3
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h
SDA
A0h †
Data Byte †
†
09h sets V
TRIP1
S
T
A
R
T
†
0Dh sets V
†
TRIP2
All others Reserved.
Figure 15. Setting V
to a higher level (x=1,2).
TRIPx
V3 monitoring
higher precision / tolerance is required, the X9522 trip
points may be adjusted by the user, using the steps
detailed below.
The X9522 asserts the V3RO output HIGH if the volt-
age V3 exceeds the corresponding V threshold
TRIP3
(See Figure 14). The bit V3OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
Setting a V
Voltage (x=2,3)
TRIPx
There are two procedures used to set the threshold
voltages (V ), depending if the threshold voltage to
TRIPx
The V3RO output may remain active HIGH with Vcc
down to 1V.
be stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIPx
V
is 3.2 V, the new voltage can be stored directly
TRIPx
V
THRESHOLDS (X=2,3)
into the V
cell. If however, the new setting is to be
TRIPX
TRIPx
lower than the present setting, then it is necessary to
“reset” the V voltage before setting the new value.
The X9522 is shipped with pre-programmed threshold
(V ) voltages. In applications where the required
TRIPx
TRIPx
thresholds are different from the default values, or if a
V
P
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
00h †
SDA
A0h†
Data Byte
†
S
T
A
R
T
0Bh Resets VTRIP2
†
0Fh Resets VTRIP3
†
All others Reserved.
Figure 16. Resetting the V
Level (x=2,3)
TRIPx
Characteristics subject to change without notice. 13 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
Setting a Higher V
Voltage (x=2,3)
Resetting the V
Voltage
TRIPx
TRIPx
To set a V
threshold to a new voltage which is
To reset a V
voltage, apply the programming volt-
TRIPx
TRIPx
higher than the present threshold, the user must apply
the desired V threshold voltage to the corre-
sponding input pin (V2 or V3). Then, a programming
voltage (Vp) must be applied to the WP pin before a
START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
age (Vp) to the WP pin before a START condition is set
up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 0Bh for
TRIPx
V
, and 0Fh for V
, followed by 00h for the
TRIP2
TRIP3
Data Byte in order to reset V
. The STOP bit fol-
TRIPx
lowing a valid write operation initiates the programming
sequence. Pin WP must then be brought LOW to com-
plete the operation (See Figure 16).The user does not
have to set the WEL bit in the CONSTAT register
before performing this write sequence.
Address 09h for V
, and 0Dh for V
, and a 00h
TRIP3
TRIP3
Data Byte in order to program V
. The STOP bit
TRIPx
following a valid write operation initiates the program-
ming sequence. Pin WP must then be brought LOW to
complete the operation (See Figure 16). The user does
not have to set the WEL bit in the CONSTAT register
before performing this write sequence.
After being reset, the value of V
nal value of 1.7V.
becomes a nomi-
TRIPx
Setting a Lower V
Voltage (x=2,3)
V
Accuracy (x=2,3)
TRIPx
TRIPx
The accuracy with which the V
can be controlled using the iterative process shown in
Figure 17.
thresholds are set,
TRIPx
In order to set V
present value, then V
ing to the procedure described below. Once V
to a lower voltage than the
TRIPx
must first be “reset” accord-
TRIPx
TRIPx
has been “reset”, then V
can be set to the desired
TRIPx
If the desired threshold is less that the present threshold
voltage, then it must first be “reset” (See "Resetting the
VTRIPx Voltage").
voltage using the procedure described in “Setting a
Higher V Voltage”.
TRIPx
Note: X = 2,3.
V
Programming
TRIPx
Let: MDE = Maximum Desired Error
NO
Desired V
<
TRIPx
present value?
YES
Execute
V
Reset
TRIPx
Sequence
Set Vx = desired V
TRIPx
Execute
TRIPx
Sequence
New Vx applied =
Old Vx applied - Error
New Vx applied =
Old Vx applied + Error
Set Higher V
Execute
Apply Vcc / V1 & Voltage
> Desired V to Vx
Reset V
TRIPx
TRIPx
Sequence
Decrease Vx
Output
switches?
NO
YES
Error + MDE
Error - MDE
Actual V
TRIPx
TRIPx
- Desired V
Error < MDE
DONE
Figure 17. V
Setting / Reset Sequence (x=2,3)
TRIPx
Characteristics subject to change without notice. 14 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
The desired threshold voltage is then applied to the
appropriate input pin (V2 or V3) and the procedure
If the error between the desired and measured V
is
TRIPx
less than the maximum desired error, then the program-
ming process may be terminated. If however, the error is
greater than the maximum desired error, then another
described in Section “Setting a Higher V
must be followed.
Voltage“
TRIPx
iteration of the V
performed (using the calculated error) in order to further
increase the accuracy of the threshold voltage.
programming sequence can be
TRIPx
Once the desired V
threshold has been set, the
TRIPx
error between the desired and (new) actual set threshold
can be determined. This is achieved by applying Vcc / V1
to the device, and then applying a test voltage higher than
the desired threshold voltage, to the input pin of the volt-
If the calculated error is greater than zero, then the
V
must first be “reset”, and then programmed to the
TRIPx
age monitor circuit whose V
was programmed. For
a value equal to the previously set V
minus the cal-
TRIPx
TRIPx
example, if V
was set to a desired level of 3.0 V,
culated error. If it is the case that the error is less than
zero, then the V must be programmed to a value
TRIP2
then a test voltage of 3.4 V may be applied to the voltage
monitor input pin V2. In all cases, care should be taken
not to exceed the maximum input voltage limits.
TRIPx
equal to the previously set V
of the calculated error.
plus the absolute value
TRIPx
After applying the test voltage to the voltage monitor input
pin, the test voltage can be decreased (either in discrete
steps, or continuously) until the output of the voltage
monitor circuit changes state. At this point, the error
between the actual / measured, and desired threshold
levels is calculated.
Continuing the previous example, we see that the calcu-
lated error was 0.09V. Since this is greater than zero, we
must first “reset” the V
threshold, then apply a volt-
TRIP2
age equal to the last previously programmed voltage,
minus the last previously calculated error. Therefore, we
must apply V
= 2.91 V to pin V2 and execute the
TRIP1
programming sequence (See "Setting a Higher VTRIPx
Voltage (x=2,3)").
For example, the desired threshold for V
is set to
TRIP2
3.0 V, and a test voltage of 3.4 V was applied to the input
pin V2 (after applying power to Vcc / V1). The input volt-
age is decreased, and found to trip the associated output
level of pin V2RO from a LOW to a HIGH, when V2
reaches 3.09 V. From this, it can be calculated that the
programming error is 3.09 - 3.0 = 0.09 V.
Using this process, the desired accuracy for a particular
V
threshold may be attained using a successive
TRIPx
number of iterations.
Characteristics subject to change without notice. 15 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Parameter
Temperature under Bias
Min.
–65
–65
–1.0
–1.0
Max.
+135
+150
+15
Units
°C
°C
V
Storage Temperature
Voltage on WP pin (With respect to Vss)
Voltage on other pins (With respect to Vss)
+7
V
Vcc / V1
5
V
| Voltage on R – Voltage on R | (x=0,1,2. Referenced to Vss)
D.C. Output Current (SDA,V2RO,V3RO)
Hx
Lx
0
mA
°C
V
Lead Temperature (Soldering, 10 seconds)
300
Supply Voltage Limits (Applied Vcc / V1 voltage, referenced to Vss)
2.7
5.5
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
0
Max.
70
Units
°C
Commercial
Industrial
–40
+85
°C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability
Figure 18. Equivalent A.C. Circuit
Vcc / V1 = 5V
2300Ω
SDA
V2RO
V3RO
100pF
Figure 19. DCP SPICE Macromodel
R
TOTAL
R
R
Hx
Lx
C
L
C
H
10pF
R
W
C
10pF
W
25pF
(x=0,1,2)
R
Wx
Characteristics subject to change without notice. 16 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
TIMING DIAGRAMS
Figure 20. Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
A
DH
SDA OUT
Figure 21. WP Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
WP
t
t
HD:WP
SU:WP
Figure 22. Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
Characteristics subject to change without notice. 17 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
Figure 23. V2, V3 Timing Diagram
t
t
Fx
Rx
Vx
V
TRIPx
t
t
RPDx
RPDx
t
RPDx
0 Volts
0 Volts
t
RPDx
VxRO
Vcc / V1
V
TRIP
V
RVALID
0 Volts
Note : x = 2,3.
Figure 24. V
Programming Timing Diagram (x=2,3)
TRIPX
V2, V3
V
TRIPx
t
t
TSU
THD
V
P
WP
t
VPS
t
VPO
SCL
SDA
t
wc
00h
t
VPH
NOTE : Vcc / V1 must be greater than V2, V3 when programming.
Characteristics subject to change without notice. 18 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
Figure 25. DCP “Wiper Position” Timing
Rwx (x=0,1,2)
R
wx(n+1)
R
wx(n)
R
wx(n-1)
t
wr
Time
n = tap position
SCL
SDA
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Characteristics subject to change without notice. 19 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min Typ
Max
Unit
Test Conditions / Notes
Current into Vcc / V1 Pin
(X9522: Active)
f
= 400KHz
I
(1)
SCL
CC1
Read memory array (3)
Write nonvolatile memory
0.4
1.5
mA
V
= Vcc / V1
SDA
Current into Vcc / V1 Pin
WP = Vss or Open/Floating
= Vcc / V1 (when no bus ac-
(X9522:Standby)
With 2-Wire bus activity (3)
No 2-Wire bus activity
I
(2)
µA
CC2
V
30.0
30.0
SCL
tivity else f
= 400kHz)
SCL
V
(4) = GND to Vcc / V1
.
0.1
10
1
µA
µA
Input Leakage Current (SCL, SDA)
Input Leakage Current (WP)
IN
I
I
LI
V
(5) = GND to Vcc / V1
OUT
.
Output Leakage Current (SDA, V2RO,
V3RO)
0.1
10
µA
LO
X9522 is in Standby(2)
V
V
Programming Range (x=1,2)
1.8
4.70
V
V
TRIPxPR
TRIPx
1.75 1.8
2.95 3.0
1.85
3.05
Factory shipped preset option A
Factory shipped preset option B
V
V
I
(6)
Pre - programmed V
Pre - programmed V
threshold
threshold
TRIP1
TRIP2
TRIP1
TRIP2
1.75 1.8
2.95 3.0
1.85
3.05
Factory shipped preset option A
Factory shipped preset option B
(6)
V
V
=V
=Vcc / V1
V2 Input leakage current
V3 Input leakage current
1
1
SDA SCL
µA
V
Vx
Others=GND or Vcc / V1
V
V
V
(7)
Input LOW Voltage (SCL, SDA, WP)
Input HIGH Voltage (SCL,SDA, WP)
V2RO, V3RO, SDA Output Low Voltage
-0.5
2.0
0.8
IL
Vcc /
V1 +0.5
(7)
IH
V
I
= 2.0mA
0.4
V
OLx
SINK
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200nS after a STOP ending a read operation; or t after a STOP ending a write operation.
WC
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
after a STOP that initiates
WC
a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4.
Notes: 5.
V
V
= Voltage applied to input pin.
IN
= Voltage applied to output pin.
OUT
Notes: 6. See “ORDERING INFORMATION” on page 29.
Notes: 7. Min. and V Max. are for reference only and are not tested
V
IL
IH
Characteristics subject to change without notice. 20 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
A.C. CHARACTERISTICS (See Figure 20, Figure 21, Figure 22)
400kHz
Symbol
Parameter
Min
0
Max
Units
KHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
400
SCL Clock Frequency
SCL
(5)
IN
50
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
µs
AA
µs
BUF
µs
LOW
µs
Clock HIGH Time
HIGH
µs
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
DH
µs
ns
µs
Data In Hold Time
0.6
50
µs
Stop Condition Setup Time
Data Output Hold Time
ns
t (5)
R
300
300
ns
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
20 +.1Cb (2)
t (5)
F
ns
20 +.1Cb (2)
t
0.6
0
µs
SU:WP
t
µs
WP Hold Time
HD:WP
400
pF
Cb
Capacitive load for each bus line
A.C. TEST CONDITIONS
Input Pulse Levels
0.1Vcc to 0.9Vcc
10ns
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
0.5Vcc
See Figure 18
NONVOLATILE WRITE CYCLE TIMING
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
t
(4)
5
10
ms
Nonvolatile Write Cycle Time
WC
CAPACITANCE (T = 25˚C, F = 1.0 MHZ, VCC / V1 = 5V)
A
Symbol
Parameter
Max
Units
Test Conditions
= 0V
V
C
C
(5)
Output Capacitance (SDA, V2RO, V3RO)
8
pF
pF
OUT
OUT
V
= 0V
(5)
IN
Input Capacitance (SCL, WP)
6
IN
Notes: 1. Typical values are for T = 25˚C and Vcc / V1 = 5.0V
A
Notes: 2. Cb = total capacitance of one bus line in pF.
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4.
t
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
WC
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
Characteristics subject to change without notice. 21 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions/Notes
R
End to End Resistance Tolerance
–20
+20
%
TOL
Vcc /
V1
V
R Terminal Voltage (x=0,1,2)
H
Vss
Vss
V
V
RHx
Vcc /
V1
V
R Terminal Voltage (x=0,1,2)
L
RLx
R
= 10 KΩ (DCP0,
= 100 KΩ (DCP2)
TOTAL
10
5
mW
mW
DCP1)
P
R
Power Rating (1)
R
TOTAL
I
= 1mA, Vcc / V1 = 5 V, V
RHx
W
200
300
400
400
700
Ω
Ω
= Vcc / V1, V
(x=0,1,2).
= Vss
RLx
I
= 1mA, Vcc / V1 = 3.3 V,
W
R
DCP Wiper Resistance
V
= Vcc / V1, V
= Vss
W
RHx
RLx
(x=0,1,2),
I
= 1mA, Vcc / V1 = 2.7 V,
W
1000
1
Ω
V
= Vcc / V1, V
= Vss
RHx
RLx
(x=0,1,2)
I
Wiper Current
Noise
mA
W
R
= 10 kΩ (DCP0,
mV /
sqt(Hz)
TOTAL
DCP1)
mV /
sqt(Hz)
R
= 100 kΩ (DCP2)
TOTAL
MI(4)
MI(4)
R
R
R
– R
-1
+1
Absolute Linearity (2)
Relative Linearity (3)
w(n)(actual)
w(n)(expected)
]
w(n)+MI
– [R
-0.2
+0.2
w(n+1)
= 10 kΩ (DCP0,
TOTAL
300
300
ppm/°C
DCP1)
R
Temperature Coefficient
TOTAL
R
= 100 kΩ (DCP2)
ppm/°C
pF
TOTAL
C /C /
Potentiometer Capacitances
Wiper Response time
10/10/
25
H
L
See Figure 19.
See Figure 25.
C
W
t
200
75
µs
wr
Vcc / V1 power up DCP recall thresh-
old
V
t
V
TRIP
Vcc / V1 power up DCP recall delay
time
25
50
ms
PU
Notes: 1. Power Rating between the wiper terminal R
and the end terminals R or R - for ANY tap position n, (x=0,1,2).
HX LX
WX(n)
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R (actual) – R (expected)) = 1
wx(n) wx(n)
Ml Maximum (x=0,1,2).
Notes: 3. Relative Linearity is a measure of the error in step size between taps = R
– [R
+ Ml] = 0.2 Ml (x=0,1,2)
Wx(n+1)
wx(n)
Notes: 4. 1 Ml = Minimum Increment = R
/ (Number of taps in DCP - 1).
TOT
Notes: 5. Typical values are for T = 25°C and nominal supply voltage.
A
Notes: 6. This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 22 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
V
(X=1,2) PROGRAMMING PARAMETERS (See Figure 24)
TRIPX
Parameter
Description
Min
Typ
Max
Units
t
V
V
V
V
V
Program Enable Voltage Setup time
10
µs
VPS
TRIPx
TRIPx
TRIPx
TRIPx
TRIPx
t
Program Enable Voltage Hold time
Setup time
10
10
10
µs
µs
µs
VPH
t
TSU
t
Hold (stable) time
THD
Program Enable Voltage Off time
t
1
ms
VPO
(Between successive adjustments)
V Write Cycle time
TRIPx
t
5
10
15
ms
V
wc
V
P
10
Programming Voltage
Initial V Program Voltage accuracy
TRIPx
V
V
(1)
(1)
-0.1
+0.2
+25
+25
V
ta1
(Vx applied - V
) (Programmed at 25oC.)
TRIPx
TRIPx
Subsequent V
Program Voltage accuracy
-25
-25
+10
+10
mV
mV
ta2
[(Vx applied - V ) - V
. Programmed at 25oC.)
TRIPx
ta1
V
Program variation after programming (-40 - 85oC).
TRIP
V
tv
(Programmed at 25oC.)
Notes: 1. This parameter is not 100% tested.
Characteristics subject to change without notice. 23 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
V2RO, V3RO OUTPUT TIMING. (See Figure 23)
Symbol
Description
Condition
Min.
Typ.
Max.
Units
V2, V3 to V2RO, V3RO propa-
gation delay (respectively)
t
20
µs
RPDx
t
t
V2, V3 Fall Time
V2, V3 Rise Time
20
20
mV/µs
mV/µs
Fx
Rx
Vcc / V1 for V2RO, V3RO Valid
(3).
V
1
V
RVALID
Notes: 1. See Figure 23 for timing diagram.
Notes: 2. See Figure 18 for equivalent load.
Notes: 3. This parameter describes the lowest possible Vcc / V1 level for which the outputs V2RO, and V3RO will be correct with respect to their
inputs ( V2, V3).
Characteristics subject to change without notice. 24 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0000 0000
0000 0001
0
1
0
1
.
.
.
.
.
.
0001 0111
0001 1000
0011 1000
0011 0111
23
24
25
26
23
24
56
55
.
.
.
.
.
.
0010 0001
0010 0000
0100 0000
0100 0001
48
49
50
51
33
32
64
65
.
.
.
.
.
.
0101 0111
0101 1000
0111 1000
0111 0111
73
74
75
76
87
88
120
119
.
.
.
.
.
.
0110 0001
0110 0000
98
99
97
96
Characteristics subject to change without notice. 25 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example.
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned) wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned) wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned) wcr_val);
}
}
}
return((unsigned)01100000);
}
Characteristics subject to change without notice. 26 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
20 Ball BGA (X9522)
a
a
l
j
m
1
2
3
4
4
3
2
1
A
B
C
D
E
A
B
C
D
E
b
b
k
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
= Die Orientation mark
d
c
e
Side View (Bump Side Down)
Millimeters
Nom
Inches
Symbol
Min
Max
Min
Nom
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
2.566
3.836
0.510
0.395
0.110
0.250
2.591
3.861
0.570
0.430
0.140
0.28
2.616
3.886
0.630
0.465
0.170
0.310
0.10102
0.15102
0.02008
0.01555
0.00433
0.00984
0.10201
0.15201
0.02244
0.01693
0.00551
0.01102
0.10299
0.15299
0.02480
0.01831
0.00669
0.01220
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
20
4
Ball Count X Axis
Ball Count Y Axis
Pins Pitch XAxis
5
j
0.6
0.6
0.0236
0.0236
Pins Pitch Y Axis
k
Edge to Ball Center (Corner)
Distance Along X
l
0.365
0.700
0.395
0.730
0.425
0.760
0.01437
0.02756
0.01555
0.02874
0.01673
0.02992
Edge to Ball Center (Corner)
Distance Along Y
m
Characteristics subject to change without notice. 27 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.252 (6.4)
.300 (6.6)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
(7.72)
(4.16)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
(1.78)
(0.42)
.019 (.50)
.029 (.75)
DetailA (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 28 of 29
REV 1.0 7/21/00
www.xicor.com
X9522 – Preliminary Information
ORDERING INFORMATION
y
-
X9522
P
T
Preset (Factory Shipped) V
Threshold Levels (x=2,3)
TRIPx
Device
A = Optimized for 3.3 V system monitoring †
B = Optimized for 5 V system monitoring †
Temperature Range
Blank = Industrial = –40°C to +85°C
Package
V20 = 20-Lead TSSOP
Z20 = 20-Lead XBGA
XBGA PART MARK CONVENTION
20 Lead XBGA
X9522Z20A
X9522Z20B
Top Mark
TBD
TBD
†
For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS"
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc.
All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461;
4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880;
5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 29 of 29
REV 1.0 7/21/00
www.xicor.com
相关型号：
©2020 ICPDF网 联系我们和版权申明