XA9572XL-15TQG100Q [XILINX]
Flash PLD, 15.5ns, CMOS, PQFP100, TQFP-100;
| 型号： | XA9572XL-15TQG100Q |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 15.5ns, CMOS, PQFP100, TQFP-100 输入元件 可编程逻辑 |
| 文件： | 总10页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XA9572XL Automotive CPLD
0
0
DS599 (v1.1) April 3, 2007
Product Specification
Features
Description
The XA9572XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage automotive applications. It is comprised
of four 54V18 Function Blocks, providing 1,600 usable
gates with propagation delays of 15.5 ns. See Figure 2 for
overview.
•
AEC-Q100 device qualification and full PPAP support
available in both extended temperature Q-grade and
I-grade.
•
Guaranteed to meet full electrical specifications over
TA = -40° C to +105° C with TJ Maximum = +125° C
Power Estimation
(Q-grade)
•
•
•
•
15.5 ns pin-to-pin logic delays
System frequency up to 64.5 MHz
72 macrocells with 1,600 usable gates
Available in small footprint packages
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. Each macrocell in an XA9500XL automotive device
must be configured for low-power mode (default mode for
XA9500XL devices). In addition, unused product-terms and
macrocells are automatically deactivated by the software to
further conserve power.
-
-
-
-
44-pin VQFP (34 user I/O pins)
64-pin VQFP (52 user I/O pins)
100-pin TQFP (72 user I/O pins)
Pb-free package only
For a general estimate of ICC, the following equation may be
used:
•
•
Optimized for high-performance 3.3V systems
-
-
Low power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
I
CC(mA) = MC(0.052*PT + 0.272) + 0.04 * MCTOG * MC * f
where:
MC = # macrocells
-
-
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
PT = average number product terms per macrocell
f = maximum clock frequency
Advanced system features
-
-
In-system programmable
MCTOG = average % of flip-flops toggling per clock
(~12%)
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
This calculation was derived from laboratory measurements
of an XA9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
-
-
-
-
-
-
-
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
75
•
•
•
•
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
50
64.5 MHz
25
0
-
Endurance exceeding 10,000 program/erase
cycles
-
-
20 year data retention
ESD protection exceeding 2,000V
100
DS599_01_121106
50
Clock Frequency (MHz)
WARNING: Programming temperature range of
TA = 0° C to +70° C
Figure 1: Typical ICC vs. Frequency for XA9572XL
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS599 (v1.1) April 3, 2007
www.xilinx.com
1
Product Specification
R
XA9572XL Automotive CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
54
54
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
1
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
2
Macrocells
1 to 18
DS057_02_082800
Figure 2: XA9572XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
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DS599 (v1.1) April 3, 2007
Product Specification
R
XA9572XL Automotive CPLD
(1,3)
Absolute Maximum Ratings
Symbol
Description
Value
Units
V
VCC
VIN
Supply voltage relative to GND
Input voltage relative to GND(2)
Voltage applied to 3-state output(2)
Storage temperature (ambient)(4)
Junction temperature
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
–65 to +150
+125
V
VTS
TSTG
TJ
V
oC
oC
Notes:
1. All automotive customers are required to set the Macrocell Power Setting to low, and set Logic Optimization to density.
2. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V.
3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
4. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Recommended Operation Conditions
Symbol
Parameter
I-Grade
Q-Grade
Min
–40
–40
3.0
3.0
2.3
0
Max
+85
+105
3.6
Units
oC
oC
V
Ambient temperature
TA
VCCINT
VCCIO
Supply voltage for internal logic and input buffers
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
3.6
V
2.7
V
VIL
VIH
VO
0.80
5.5
V
High-level input voltage
2.0
0
V
Output voltage
VCCIO
V
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
TDR
Data Retention
-
-
-
Years
Cycles
Volts
NPE
Program/Erase Cycles (Endurance) @ TA = 70°
Electrostatic Discharge (ESD)
10,000
2,000
VESD
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
IOH = –4.0 mA
OH = –500 μA
IOL = 8.0 mA
OL = 500 μA
Min
Max
Units
V
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
2.4
-
VOH
I
90% VCCIO
-
V
-
-
-
-
0.4
0.4
±10
±10
V
VOL
I
V
IIL
VCC = Max; VIN = GND or VCC
VCC = Max; VIN = GND or VCC
μA
μA
IIH
I/O high-Z leakage current
DS599 (v1.1) April 3, 2007
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3
Product Specification
R
XA9572XL Automotive CPLD
Symbol
Parameter
Test Conditions
Min
Max
Units
I/O high-Z leakage current
VCC = Max; VCCIO = Max;
-
±10
μA
VIN = GND or 3.6V
IIH
V
CC Min < VIN < 5.5V
-
-
±50
10
μA
pF
CIN
ICC
I/O capacitance
VIN = GND; f = 1.0 MHz
Operating supply current
(low power mode, active)
VIN = GND, No load; f = 1.0 MHz
20 (Typical)
mA
AC Characteristics
XA9572XL-15
Symbol
Parameter
Min
Max
Units
TPD
TSU
I/O to output valid
I/O setup time before GCK
-
15.5
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12.0
-
TH
I/O hold time after GCK
GCK to output valid
0
-
-
5.8
64.5
-
TCO
fSYSTEM
TPSU
TPH
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
-
7.6
0.0
-
-
TPCO
TOE
10.2
7.0
7.0
11.0
11.0
14.5
15.3
-
GTS to output valid
-
TOD
GTS to output disable
-
TPOE
TPOD
TAO
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
-
-
-
TPAO
TWLH
TAPRPW
TPLH
TSUEC
THEC
P-term S/R to output valid
-
GCK pulse width (High or Low)
Asynchronous preset/reset pulse width (High or Low)
P-term clock pulse width (High or Low)
Clock enable setup
4.5
7.0
7.0
6.5
0
-
-
-
Clock enable hold
-
V
TEST
R
1
2
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
3.3V
2.5V
3.3V
2.5V
320 Ω
250 Ω
360 Ω
660 Ω
35 pF
35 pF
C
L
R
DS058_03_081500
Figure 3: AC Load Circuit
4
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DS599 (v1.1) April 3, 2007
Product Specification
R
XA9572XL Automotive CPLD
Internal Timing Parameters
XA9572XL-15
Symbol
Parameter
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
TGCK
TGSR
TGTS
TOUT
TEN
Output buffer enable/disable delay
Product Term Control Delays
TPTCK
TPTSR
TPTTS
Product term clock delay
-
-
-
2.7
1.8
7.5
ns
ns
ns
Product term set/reset delay
Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI
TSUI
Combinatorial logic propagation delay
Register setup time
-
3.0
3.5
3.0
3.5
-
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
THI
Register hold time
TECSU
TECHO
TCOI
TAOI
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
1.0
7.0
-
-
TRAI
10.0
-
TLOGI
7.3
Feedback Delays
TF
Time Adders
TPTA
Fast CONNECT II feedback delay
-
4.2
ns
Incremental product term allocator delay
Slew-rate limited delay
-
-
1.0
4.5
ns
ns
TSLEW
DS599 (v1.1) April 3, 2007
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5
Product Specification
R
XA9572XL Automotive CPLD
XA9572XL I/O Pins
Function
BScan
Order
Function
Block
BScan
Order
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Macrocell
1
VQG44
VQG64 TQG100
Macrocell
1
VQG44
VQG64 TQG100
-
-
8
16
13
18
20
14
15
25
17
22(1)
28
23(1)
33
36
27(1)
29
39
30
40
87
94
91
93
95
96
3(2)
97
99(1)
1
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
5
-
41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
64
58
59
65
67
71
72
68
76
77
70
66
81
74
82
85
78
89
86
90
79
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
2
39
2
22
31
32
24
34
-
3
-
12
13
9
3
-
4
-
4
-
5
40
5
6
6
41
10
-
6
-
7
-
7
-
8
42
43(1)
11
15(1)
18
16(1)
23
-
17(1)
19
-
8
7
25
27
39
33
40
-
9
9
8
10
11
12
13
14
15
16
17
18
1
-
10
11
12
13
14
15
16
17
18
1
-
44(1)
12
-
-
-
-
1(1)
13
14
18
16
-
35
36
42
38
-
2
-
3
20
-
-
-
-
-
-
2
29
60
58
59
61
62
-
2
19
-
43
46
47
44
49
-
3
-
3
4
-
4
-
5
30
5
20
-
6
31
6
7
-
7
-
8
32
33(1)
63
64(1)
1
8
21
-
45
-
9
9
10
11
12
13
14
15
16
17
18
-
10
11
12
13
14
15
16
17
18
-
51
48
52
-
34(1)
2(1)
4(1)
22
-
-
4
6
-
36(2)
37
-
-
8
-
5(2)
9
23
27
-
50
56
-
6
11
-
10
12
92
6
38
-
7
28
-
57
-
3
-
0
Notes:
1. Global control pin.
2. GTS1
6
www.xilinx.com
DS599 (v1.1) April 3, 2007
Product Specification
R
XA9572XL Automotive CPLD
XA9572XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
VQG44
VQG64
TQG100
43
44
15
22
16
23
1
17
27
36
5
3
34
2
4
33
64
99
11
30
48
TDI
9
28
53
45
83
TDO
24
TMS
10
29
47
V
CCINT 3.3V
VCCIO 2.5V/3.3V
GND
15, 35
26
3, 37
5, 57, 98
26, 38, 51, 88
26, 55
14, 21, 41, 54
4, 17, 25
21, 31, 44, 62,
69, 75, 84, 100
No Connects
-
-
2, 7, 19, 24, 34,
43, 46, 73, 80
DS599 (v1.1) April 3, 2007
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7
Product Specification
R
XA9572XL Automotive CPLD
Device Part Marking and Ordering Combination Information
R
Device Type
Package
XA9572XL
TQG100
This line not
related to device
part number
15I
Speed
Operating Range
1
·
Sample package with part marking.
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
No. of
Pins
Operating
Range(1)
Symbol
VQG44
VQG64
Package Type
XA9572XL-15VQG44I
XA9572XL-15VQG64I
XA9572XL-15TQG100I
XA9572XL-15VQG44Q
XA9572XL-15VQG64Q
XA9572XL-15TQG100Q
Notes:
15.5 ns
15.5 ns
15.5 ns
15.5 ns
15.5 ns
15.5 ns
44-pin
64-pin
Quad Flat Pack (VQFP)
Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
Quad Flat Pack (VQFP)
Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
I
I
TQG100 100-pin
I
VQG44
VQG64
44-pin
64-pin
Q
Q
Q
TQG100 100-pin
I-Grade: TA = –40° to +85°C; Q-Grade: TA = –40° to +105°C.
XA9572XL -15 TQ
G
100
I
Example:
Device
Speed Grade
Package Type
-Free
Pb
Number of Pins
Temperature Range
XA9500XL Automotive Requirements and Recommendations
3. Do not float I/O pins during device operation. Floating
I/O pins can increase ICC as input buffers will draw
Requirements
The following requirements are for all automotive applica-
tions:
1-2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
I/O pins should be appropriately terminated with
keeper/bus-hold. Unused I/Os can also be configured
as CGND (programmable GND).
1. All automotive customers are required to keep the
Macrocell Power selection set to low, and the Logic
Optimization set to density when designing with ISE
software. These are the default settings when
XA9500XL devices are selected for design. These
settings are found on the Process Properties page for
Implement Design. See the ISE Online Help for details
on these properties.
4. Do not drive I/O pins without VCC/VCCIO powered.
5. Sink current when driving LEDs. Because all Xilinx
CPLDs have N-channel pull-down transistors on
outputs, it is required that an LED anode is sourced
through a resistor externally to VCC. Consequently, this
will give the brightest solution.
2. Use a monotonic, fast ramp power supply to power up
XA9500XL . A VCC ramp time of less than 1 ms is
required.
6. Avoid external pull-down resistors. Always use external
pull-up resistors if external termination is required. This
is because the XC9500XL Automotive CPLD, which
8
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DS599 (v1.1) April 3, 2007
Product Specification
R
XA9572XL Automotive CPLD
includes some I/O driving circuits beyond the input and
output buffers, may have contention with external
pull-down resistors, and, consequently, the I/O will not
switch as expected.
2. Include JTAG stakes on the PCB. JTAG stakes can be
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
7. Do not drive I/Os pins above the VCCIO assigned to its
I/O bank.
3. XA9500XL Automotive CPLDs work with any power
sequence, but it is preferable to power the VCCI
(internal VCC) before the VCCIO for the applications in
which any glitches from device I/Os are unwanted.
a. The current flow can go into VCCIO and affect a user
voltage regulator.
b. It can also increase undesired leakage current
associated with the device.
4. Do not disregard report file warnings. Software
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
c. If done for too long, it can reduce the life of the
device.
8. Do not rely on the I/O states before the CPLD
configures.
5. Understand the Timing Report. This report file provides
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
9. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
6. Review Fitter Report equations. Equations can be
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
10. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO comply with IEEE 1149.1. All Xilinx CPLDs have
internal weak pull-ups of ~50 kΩ on TDI, TMS, and
TCK.
7. Let design software define pinouts if possible. Xilinx
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
11. Attach all CPLD VCC and GND pins in order to have
necessary power and ground supplies around the
CPLD.
12. Decouple all VCC and VCCIO pins with capacitors of
0.01 μF and 0.1 μF closest to the pins for each
8. Perform a post-fit simulation for all speeds to identify
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
V
CC/VCCIO-GND pair.
Recommendations
The following recommendations are for all automotive appli-
cations.
9. Distribute SSOs (Simultaneously Switching Outputs)
evenly around the CPLD to reduce switching noise.
1. Use strict synchronous design (only one clocking event)
if possible. A synchronous system is more robust than
an asynchronous one.
10. Terminate high speed outputs to eliminate noise caused
by very fast rising/falling edges.
Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS
NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE
NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED
FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR
REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE.
USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE
LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
DS599 (v1.1) April 3, 2007
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9
Product Specification
R
XA9572XL Automotive CPLD
Packaging
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
01/12/07
04/03/07
Initial Xilinx release.
1.1
Add programming temperature range warning on page 1.
10
www.xilinx.com
DS599 (v1.1) April 3, 2007
Product Specification
相关型号：
XA9572XL-15VQG44I
Flash PLD, 15.5ns, CMOS, PQFP44, VQFP-44Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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XILINX
XA9572XL-15VQG44Q
Flash PLD, 15.5ns, CMOS, PQFP44, VQFP-44Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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XILINX
XA9572XL-15VQG64I
Flash PLD, 15.5ns, CMOS, PQFP64, VQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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XILINX
XA9572XL-15VQG64Q
Flash PLD, 15.5ns, CMOS, PQFP64, VQFP-64Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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XILINX
XAA117
Transistor Output SSR, 2-Channel, 3750V Isolation, ROHS COMPLIANT, DIP-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IXYS
XAA117
Dual Single Pole OptoMOS® RelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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CLARE
XAA117P
Transistor Output SSR, 2-Channel, 3750V Isolation, ROHS COMPLIANT, FLAT PACK-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IXYS
XAA117P
Dual Single Pole OptoMOS® RelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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CLARE
XAA117PTR
Transistor Output SSR, 2-Channel, 3750V Isolation, ROHS COMPLIANT, FLAT PACK-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IXYS
XAA117PTR
Dual Single Pole OptoMOS® RelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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CLARE
XAA117S
Transistor Output SSR, 2-Channel, 3750V Isolation, ROHS COMPLIANT, SURFACE MOUNT PACKAGE-8Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IXYS
XAA117S
Dual Single Pole OptoMOS® RelayWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
CLARE
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