XC3S400A-4FTG256C [XILINX]
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 250MHz, 8064-Cell, CMOS, PBGA256, LEAD FREE, FPTBGA-256;
| 型号： | XC3S400A-4FTG256C |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, 896 CLBs, 400000 Gates, 250MHz, 8064-Cell, CMOS, PBGA256, LEAD FREE, FPTBGA-256 时钟 栅 可编程逻辑 |
| 文件： | 总132页 (文件大小：3936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
Spartan-3A FPGA Family:
Data Sheet
0
0
DS529 August 19, 2010
Product Specification
Module 1:
Introduction and Ordering Information
Module 3:
DC and Switching Characteristics
DS529-1 (v2.0) August 19, 2010
DS529-3 (v2.0) August 19, 2010
•
•
•
•
•
•
•
Introduction
Features
•
DC Electrical Characteristics
•
•
•
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
Architectural and Configuration Overview
General I/O Capabilities
Production Status
Supported Packages and Package Marking
Ordering Information
•
Switching Characteristics
•
•
•
•
•
•
•
•
I/O Timing
Configurable Logic Block (CLB) Timing
Multiplier Timing
Block RAM Timing
Module 2:
Digital Clock Manager (DCM) Timing
Suspend Mode Timing
Device DNA Timing
Spartan-3A FPGA Family: Functional
Description
Configuration and JTAG Timing
DS529-2 (v2.0) August 19, 2010
The functionality of the Spartan®-3A FPGA family is
described in the following documents.
Module 4:
Pinout Descriptions
•
UG331: Spartan-3 Generation FPGA User Guide
DS529-4 (v2.0) August 19, 2010
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
•
•
•
•
Pin Descriptions
Package Overview
Pinout Tables
Configurable Logic Blocks (CLBs)
-
-
-
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
Footprint Diagrams
For more information on the Spartan-3A FPGA family, go to
www.xilinx.com/spartan3a
•
•
•
•
•
•
•
•
•
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools and IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Spartan-3A FPGA
XC3S50A
Status
Production
Production
Production
Production
Production
Powering FPGAs
Power Management
XC3S200A
•
UG332: Spartan-3 Generation Configuration User Guide
XC3S400A
•
•
•
•
Configuration Overview
Configuration Pins and Behavior
Bitstream Sizes
XC3S700A
XC3S1400A
Detailed Descriptions by Mode
-
-
-
-
-
-
Master Serial Mode using Platform Flash PROM
Master SPI Mode using Commodity Serial Flash
Master BPI Mode using Commodity Parallel Flash
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
•
•
•
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
•
UG334: Spartan-3A/3AN FPGA Starter Kit User Guide
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529 August 19, 2010
www.xilinx.com
1
Product Specification
Spartan-3A FPGA Family: Data Sheet
2
www.xilinx.com
DS529 August 19, 2010
Product Specification
8
Spartan-3A FPGA Family:
Introduction and Ordering Information
DS529-1 (v2.0) August 19, 2010
Product Specification
Introduction
•
•
640+ Mb/s data transfer rate per differential I/O
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 400 Mb/s
Fully compliant 32-/64-bit, 33/66 MHz PCI® technology
support
The Spartan®-3A family of Field-Programmable Gate
Arrays (FPGAs) solves the design challenges in most
high-volume, cost-sensitive, I/O-intensive electronic
applications. The five-member family offers densities ranging
from 50,000 to 1.4 million system gates, as shown in Table 1.
•
•
•
The Spartan-3A FPGAs are part of the Extended
Spartan-3A family, which also include the non-volatile
Spartan-3AN and the higher density Spartan-3A DSP
FPGAs. The Spartan-3A family builds on the success of the
earlier Spartan-3E and Spartan-3 FPGA families. New
features improve system performance and reduce the cost
of configuration. These Spartan-3A family enhancements,
combined with proven 90 nm process technology, deliver
more functionality and bandwidth per dollar than ever before,
setting the new standard in the programmable logic industry.
•
Abundant, flexible logic resources
•
Densities up to 25,344 logic cells, including optional shift
register or distributed RAM support
•
•
•
•
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
•
•
Hierarchical SelectRAM™ memory architecture
•
Up to 576 Kbits of fast block RAM with byte write enables
for processor applications
•
Up to 176 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
Because of their exceptionally low cost, Spartan-3A FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home networking,
display/projection, and digital television equipment.
•
•
•
•
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
•
•
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
The Spartan-3A family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial cost,
lengthy development cycles, and the inherent inflexibility of
conventional ASICs, and permit field design upgrades.
•
•
•
•
•
•
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 BPI parallel NOR Flash PROM
Low-cost Xilinx® Platform Flash with JTAG
Unique Device DNA identifier for design authentication
Load multiple bitstreams under FPGA control
Post-configuration CRC checking
Features
•
Very low cost, high-performance logic solution for
high-volume, cost-conscious applications
•
Complete Xilinx ISE® and WebPACK™ development
system software support plus Spartan-3A Starter Kit
MicroBlaze™ and PicoBlaze™ embedded processors
Low-cost QFP and BGA packaging, Pb-free options
•
•
•
Dual-range VCCAUX supply simplifies 3.3V-only design
Suspend, Hibernate modes reduce system power
Multi-voltage, multi-standard SelectIO™ interface pins
•
•
•
•
•
•
•
•
Up to 502 I/O pins or 227 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot swap compliance
•
•
•
Common footprints support easy density migration
Compatible with select Spartan-3AN nonvolatile FPGAs
Compatible with higher density Spartan-3A DSP FPGAs
•
XA Automotive version available
Table 1: Summary of Spartan-3A FPGA Attributes
CLB Array
Block
RAM
Maximum
Distributed
(One CLB = Four Slices)
(1)
System Equivalent
Dedicated
Maximum Differential
RAM bits
(1)
Device
XC3S50A
XC3S200A
XC3S400A
XC3S700A
Gates Logic Cells Rows Columns CLBs
Slices
704
1,792
3,584
bits
Multipliers DCMs User I/O
I/O Pairs
50K
200K
400K
700K
1,584
4,032
8,064
13,248
25,344
16
32
40
48
72
12
16
24
32
40
176
448
896
11K
28K
56K
92K
176K
54K
3
2
4
4
8
8
144
248
311
372
502
64
112
142
165
288K
360K
360K
576K
16
20
20
32
1,472 5,888
2,816 11,264
XC3S1400A 1400K
227
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529-1 (v2.0) August 19, 2010
www.xilinx.com
3
Introduction and Ordering Information
Architectural Overview
The Spartan-3A family architecture consists of five
fundamental programmable functional elements:
•
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
These elements are organized as shown in Figure 1. A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50A, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50A has DCMs only at the
top, while the XC3S700A and XC3S1400A add two DCMs in
the middle of the two columns of block RAM and multipliers.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus 3-state
operation. Supports a variety of signal standards,
including several high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
•
•
Block RAM provides data storage in the form of 18-Kbit
dual-port blocks.
The Spartan-3A family features a rich network of routing that
interconnect all five functional elements, transmitting signals
among them. Each functional element has an associated
switch matrix that permits multiple connections to the
routing.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
IOBs
CLB
DCM
IOBs
DCM
CLBs
DCM
IOBs
DS312-1_01_032606
Notes:
1. The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1: Spartan-3A FPGA Architecture
4
www.xilinx.com
DS529-1 (v2.0) August 19, 2010
Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3A FPGAs are programmed by loading
The Spartan-3A FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional
input-only pins as indicated in Table 2.
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
Spartan-3A FPGAs support the following single-ended
standards:
•
•
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
•
•
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
•
•
•
•
•
•
•
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
Spartan-3A FPGAs support the following differential
standards:
Furthermore, Spartan-3A FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
•
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
•
•
•
•
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
Additionally, each Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
VQ100
VQG100
TQ144
TQG144
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
FG676
FGG676
Package
Body Size
(mm)
(2)
(2)
14 x 14
20 x 20
17 x 17
19 x 19
21 x 21
23 x 23
27 x 27
Device
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
User
Diff
68
60
108
50
144
64
XC3S50A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(13)
(24)
(7)
(24)
(32)
(32)
68
(13)
60
(24)
195
(35)
90
(50)
248
(56)
112
(64)
XC3S200A
XC3S400A
XC3S700A
-
-
-
-
-
-
-
-
195
(35)
90
(50)
251
(59)
112
(64)
311
(63)
142
(78)
-
-
-
-
-
-
161
(13)
74
(36)
311
(63)
142
(78)
372
(84)
165
(93)
-
-
-
-
161
(13)
74
(36)
375
(87)
165
(93)
502
(94)
227
(131)
XC3S1400A
-
-
Notes:
1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
2. The footprints for the VQ/TQ packages are larger than the package body. See the Package Drawings for details.
DS529-1 (v2.0) August 19, 2010
www.xilinx.com
5
Introduction and Ordering Information
Production Status
Table 3 indicates the production status of each Spartan-3A
FPGA by temperature range and speed grade. The table
also lists the earliest speed file version required for creating
a production configuration bitstream. Later versions are also
supported.
Table 3: Spartan-3A FPGA Production Status (Production Speed File)
Temperature Range
Speed Grade
Commercial (C)
High-Performance (–5)
Industrial
Standard (–4)
Standard (–4)
Production
Production
Production
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
(v1.35)
(v1.35)
(v1.35)
Production
(v1.35)
Production
(v1.35)
Production
(v1.35)
Production
(v1.36)
Production
(v1.36)
Production
(v1.36)
Production
(v1.34)
Production
(v1.35)
Production
(v1.34)
Production
(v1.34)
Production
(v1.35)
Production
(v1.34)
Package Marking
Figure 2 provides a top marking example for Spartan-3A
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3A FPGAs in BGA packages. The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator.
The “5C” and “4I” Speed Grade/Temperature Range part
combinations may be dual marked as “5C/4I”. Devices with
a single mark are only guaranteed for the marked speed
grade and temperature range.
Mask Revision Code
Fabrication Code
R
R
Process Technology
SPARTAN
XC3S50ATM
Device Type
Date Code
Lot Code
Package
TQ144AGQ0625
D1234567A
Speed Grade
4C
Temperature Range
Pin P1
DS529-1_03_080406
Figure 2: Spartan-3A QFP Package Marking Example
Mask Revision Code
R
BGA Ball A1
Fabrication Code
Process Code
R
SPARTAN
Device Type
XC3S50ATM
Date Code
Package
FT256 AGQ0625
D1234567A
4C
Lot Code
Speed Grade
Temperature Range
DS529-1_02_021206
Figure 3: Spartan-3A BGA Package Marking Example
6
www.xilinx.com
DS529-1 (v2.0) August 19, 2010
Introduction and Ordering Information
Ordering Information
Spartan-3A FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a ‘G’ character in the ordering code.
Example:
XC3S50A -4 FT 256 C
Device Type
Temperature Range
Speed Grade
Package Type/Number of Pins
DS529-1_05_011309
Device
Speed Grade
Package Type / Number of Pins(1)
Temperature Range (TJ)
XC3S50A
–4 Standard Performance VQ100/
VQG100
100-pin Very Thin Quad Flat Pack (VQFP)
C Commercial (0°C to 85°C)
XC3S200A –5 High Performance
(Commercial only)
TQ144/
TQG144
144-pin Thin Quad Flat Pack (TQFP)
I Industrial (–40°C to 100°C)
XC3S400A
XC3S700A
XC3S1400A
FT256/
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
320-ball Fine-Pitch Ball Grid Array (FBGA)
400-ball Fine-Pitch Ball Grid Array (FBGA)
484-ball Fine-Pitch Ball Grid Array (FBGA)
676-ball Fine-Pitch Ball Grid Array (FBGA)
FTG256
FG320/
FGG320
FG400/
FGG400
FG484/
FGG484
FG676
FGG676
Notes:
1. See Table 2 for specific device/package combinations.
2. See DS681 for the XA Automotive Spartan-3A FPGAs.
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/05/06
02/02/07
Initial release.
1.1
Promoted to Preliminary status. Updated maximum differential I/O count for XC3S50A in Table 1.
Updated differential input-only pin counts in Table 2.
03/16/07
04/23/07
05/08/07
07/10/07
04/15/08
1.2
1.3
Minor formatting updates.
Added "Production Status" section.
Updated XC3S400A to Production.
Minor updates.
1.4
1.4.1
1.6
Added VQ100 for XC3S50A and XC3S200A and extended FT256 to XC3S700A and XC3S1400A
Added reference to SCD 4103 for 750 Mbps performance.
05/28/08
03/06/09
1.7
1.8
Added reference to XA Automotive version.
Simplified Ordering Information. Added references to Extended Spartan-3A Family.
Removed reference to SCD 4103.
08/19/10
2.0
Updated Table 2 to clarify TQ/VQ size.
DS529-1 (v2.0) August 19, 2010
www.xilinx.com
7
Introduction and Ordering Information
8
www.xilinx.com
DS529-1 (v2.0) August 19, 2010
10
Spartan-3A FPGA Family:
Functional Description
0
DS529-2 (v2.0) August 19, 2010
Product Specification
Spartan-3A FPGA Design Documentation
The functionality of the Spartan®-3A FPGA Family is
described in the following documents. The topics covered in
each guide is listed below.
•
Detailed Descriptions by Mode
-
-
-
Master Serial Mode using Xilinx® Platform
Flash PROM
•
DS706: Extended Spartan-3A Family Overview
www.xilinx.com/support/documentation/
data_sheets/ds706.pdf
Master SPI Mode using Commodity SPI Serial
Flash PROM
Master BPI Mode using Commodity Parallel
NOR Flash PROM
•
UG331: Spartan-3 Generation FPGA User Guide
www.xilinx.com/support/documentation/
user_guides/ug331.pdf
-
-
-
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
•
•
•
•
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
•
•
•
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Configurable Logic Blocks (CLBs)
Design Authentication using Device DNA
-
-
-
Distributed RAM
For application examples, see the Spartan-3A FPGA
application notes.
SRL16 Shift Registers
Carry and Arithmetic Logic
•
Spartan-3A FPGA Application Notes
www.xilinx.com/support/documentation/
spartan-3a_application_notes.htm
•
•
•
•
•
•
•
•
•
•
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Software Design Tools
IP Cores
For specific hardware examples, please see the Spartan-3A
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
•
Spartan-3A/3AN FPGA Starter Kit Board Page
www.xilinx.com/s3astarter
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
•
UG334: Spartan-3A/3AN FPGA Starter Kit User
Guide
www.xilinx.com/support/documentation/
Powering FPGAs
boards_and_kits/ug334.pdf
Power Management
•
UG332: Spartan-3 Generation Configuration User
Guide
For information on the XA Automotive version of the
Spartan-3A family, see the following data sheet.
www.xilinx.com/support/documentation/
user_guides/ug332.pdf
•
XA Spartan-3A Automotive FPGA Family Data Sheet
www.xilinx.com/support/documentation/data_sheets/
ds681.pdf
•
Configuration Overview
-
-
Configuration Pins and Behavior
Bitstream Sizes
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
•
Sign Up for Alerts
www.xilinx.com/support/answers/18683.htm
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529-2 (v2.0) August 19, 2010
www.xilinx.com
9
Spartan-3A FPGA Family: Functional Description
Related Product Families
The Spartan-3AN nonvolatile FPGA family is architecturally
identical to the Spartan-3A FPGA family, except that it has
in-system flash memory and is offered in select
pin-compatible package options.
The compatible Spartan-3A DSP FPGA family replaces the
18-bit multiplier with the DSP48A block, while also
increasing the block RAM capability and quantity. The two
members of the Spartan-3A DSP FPGA family extend the
Spartan-3A density range up to 37,440 and 53,712 logic
cells.
•
DS557: Spartan-3AN Family Data Sheet
www.xilinx.com/support/documentation/
data_sheets/ds557.pdf
•
DS610: Spartan-3A DSP FPGA Family Data Sheet
www.xilinx.com/support/documentation/
data_sheets/ds610.pdf
•
UG431: XtremeDSP DSP48A for Spartan-3A DSP
FPGAs
www.xilinx.com/support/documentation/
user_guides/ug431.pdf
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/05/06
02/02/07
03/16/07
04/23/07
07/10/07
04/15/08
05/28/08
03/06/09
08/19/10
Initial release.
1.1
Promoted to Preliminary status.
1.2
Added cross-reference to nonvolatile Spartan-3AN FPGA family.
Added cross-reference to compatible Spartan-3A DSP family.
Updated Starter Kit reference to new UG334.
Updated trademarks.
1.3
1.4
1.6
1.7
Added reference to XA Automotive version.
Added link to DS706 on Extended Spartan-3A family.
Updated link to sign up for Alerts.
1.8
2.0
10
www.xilinx.com
DS529-2 (v2.0) August 19, 2010
64
Spartan-3A FPGA Family:
DC and Switching Characteristics
0
DS529-3 (v2.0) August 19, 2010
Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Absolute Maximum Ratings
Preliminary: Based on characterization. Further changes
Stresses beyond those listed under Table 4: Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
Table 4: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
–0.5
–0.5
–0.5
–0.5
Max
1.32
Units
VCCINT Internal supply voltage
VCCAUX Auxiliary supply voltage
V
V
V
V
3.75
VCCO
VREF
Output driver supply voltage
Input reference voltage
3.75
VCCO + 0.5
Voltage applied to all User I/O pins and
dual-purpose pins
Driver in a high-impedance state
–0.95
4.6
V
VIN
IIK
Voltage applied to all Dedicated pins
Input clamp current per I/O pin
–0.5
–
4.6
V
mA
V
–0.5V < VIN < (VCCO + 0.5V)(1)
Human body model
100
2000
500
200
125
150
–
VESD
Electrostatic Discharge Voltage
Charged device model
Machine model
–
V
–
V
TJ
Junction temperature
Storage temperature
–
°C
°C
TSTG
–65
Notes:
1. Upper clamp applies only when using PCI IOSTANDARDs.
2. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
11
DC and Switching Characteristics
Power Supply Specifications
Table 5: Supply Voltage Thresholds for Power-On Reset
Symbol
VCCINTT
VCCAUXT
VCCO2T
Description
Threshold for the VCCINT supply
Min
0.4
1.0
1.0
Max
1.0
Units
V
V
V
Threshold for the VCCAUX supply
2.0
Threshold for the VCCO Bank 2 supply
2.0
Notes:
1.
V
, V
, and V
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
CCO
CCINT CCAUX
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply V
information).
last for lowest overall power consumption (see UG331 chapter “Powering Spartan-3 Generation FPGAs” for more
CCINT
2. To ensure successful power-on, V
no dips at any point.
, V
Bank 2, and V
supplies must rise through their respective threshold-voltage ranges with
CCAUX
CCINT CCO
Table 6: Supply Voltage Ramp Rate
Symbol
Description
Min
0.2
0.2
0.2
Max
100
100
100
Units
ms
VCCINTR
VCCAUXR
VCCO2R
Ramp rate from GND to valid VCCINT supply level
Ramp rate from GND to valid VCCAUX supply level
Ramp rate from GND to valid VCCO Bank 2 supply level
ms
ms
Notes:
1.
V
, V
, and V
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
CCO
CCINT CCAUX
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. Apply V
information).
last for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more
CCINT
2. To ensure successful power-on, V
no dips at any point.
, V
Bank 2, and V
supplies must rise through their respective threshold-voltage ranges with
CCAUX
CCINT CCO
Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM
Data
Symbol
VDRINT
VDRAUX
Description
Min
1.0
2.0
Units
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
V
V
12
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
General Recommended Operating Conditions
Table 8: General Recommended Operating Conditions
Symbol
Description
Commercial
Min
0
Nominal
Max
85
Units
°C
°C
V
–
–
TJ
Junction temperature
Industrial
–40
1.14
1.10
2.25
3.00
–0.5
–0.5
–0.5
–
100
VCCINT
Internal supply voltage
1.20
–
1.26
(1)
VCCO
Output driver supply voltage
3.60
V
VCCAUX = 2.5
2.50
3.30
–
2.75
V
VCCAUX
Auxiliary supply voltage(2)
VCCAUX = 3.3
3.60
V
PCI IOSTANDARD
VCCO+0.5
4.10
V
VIN
TIN
Input voltage(3)
IP or IO_#
IO_Lxxy_#(4)
–
V
All other
IOSTANDARDs
–
4.10
V
Input signal transition time(5)
–
500
ns
Notes:
1. This V
range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended V
CCO
CCO
range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.
2. Define VCCAUX selection using CONFIG VCCAUX constraint.
3. See XAPP459, “Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.”
4. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage
IN
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
5. Measured between 10% and 90% V
. Follow Signal Integrity recommendations.
CCO
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
13
DC and Switching Characteristics
General DC Characteristics for I/O Pins
Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins(1)
Symbol
Description
Test Conditions
Min
Typ
Max
Units
(2)
IL
Leakage current at User I/O,
input-only, dual-purpose, and
dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
–
+10
µA
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10
–
+10
µA
µA
µA
µA
Leakage current on pins during
hot socketing, FPGA unpowered
IHS
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
Add IHS + IRPU
(3)
IRPU
Current through pull-up resistor
at User I/O, dual-purpose,
VIN = GND
VCCO or VCCAUX
3.0V to 3.6V
=
–151
–315
–182
–710
input-only, and dedicated pins.
Dedicated pins are powered by
V
CCO or VCCAUX
=
–82
–437
2.3V to 2.7V
VCCAUX
.
VCCO = 1.7V to 1.9V
CCO = 1.4V to 1.6V
CCO = 1.14V to 1.26V
–36
–22
–11
5.1
–88
–56
–226
–148
–83
µA
µA
µA
kΩ
kΩ
kΩ
kΩ
kΩ
µA
V
V
–31
(3)
RPU
Equivalent pull-up resistor value
at User I/O, dual-purpose,
input-only, and dedicated pins
(based on IRPU per Note 3)
VIN = GND
VCCO = 3.0V to 3.6V
VCCO = 2.3V to 2.7V
VCCO = 1.7V to 1.9V
VCCO = 1.4V to 1.6V
11.4
14.8
21.6
28.4
41.1
346
23.9
33.1
52.6
74.0
119.4
659
6.2
8.4
10.8
15.3
167
VCCO = 1.14V to 1.26V
(3)
IRPD
Current through pull-down
resistor at User I/O,
VCCAUX = 3.0V to 3.6V
VIN = VCCO
VCCAUX = 2.25V to 2.75V
dual-purpose, input-only, and
dedicated pins. Dedicated pins
100
225
457
µA
are powered by VCCAUX
.
(3)
RPD
Equivalent pull-down resistor
value at User I/O, dual-purpose,
input-only, and dedicated pins
(based on IRPD per Note 3)
VCCAUX = 3.0V to 3.6V
VIN = 3.0V to 3.6V
VIN = 2.3V to 2.7V
VIN = 1.7V to 1.9V
VIN = 1.4V to 1.6V
5.5
4.1
3.0
2.7
2.4
7.9
5.9
4.2
3.6
3.0
–10
–
10.4
7.8
5.7
5.1
4.5
16.0
12.0
8.5
7.2
6.0
–
20.8
15.7
11.1
9.6
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
µA
pF
Ω
VIN = 1.14V to 1.26V
8.1
VCCAUX = 2.25V to 2.75V
VIN = 3.0V to 3.6V
VIN = 2.3V to 2.7V
VIN = 1.7V to 1.9V
35.0
26.3
18.6
15.7
12.5
+10
10
V
IN = 1.4V to 1.6V
VIN = 1.14V to 1.26V
All VCCO levels
IREF
CIN
VREF current per pin
Input capacitance
–
–
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
VCCO = 3.3V 10%
90
100
115
LVDS_33,
MINI_LVDS_33,
RSDS_33
VCCO = 2.5V 10%
90
110
–
Ω
LVDS_25,
MINI_LVDS_25,
RSDS_25
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8.
2. For single-ended signals that are placed on a differential-capable I/O, V of –0.2V to –0.5V is supported but can cause increased leakage
IN
between the two pins. See "Parasitic Leakage" in UG331, Spartan-3 Generation FPGA User Guide.
3. This parameter is based on characterization. The pull-up resistance R = V
/ I
. The pull-down resistance R = V / I
.
PU
CCO RPU
PD
IN RPD
14
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Quiescent Current Requirements
Table 10: Quiescent Supply Current Characteristics
Commercial
Industrial
Symbol
Description
Device
XC3S50A
Typical(2)
Maximum(2)
Maximum(2)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ICCINTQ
Quiescent VCCINT supply current
2
7
20
50
85
120
220
2
30
70
125
185
310
3
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
10
13
24
0.2
0.2
0.3
0.3
0.3
3
ICCOQ
Quiescent VCCO supply current
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
2
3
3
4
3
4
3
4
ICCAUXQ Quiescent VCCAUX supply current
8
10
15
24
34
58
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
5
12
18
28
50
5
6
10
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8.
2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at room temperature (T of 25°C at V = 1.2V, V = 3.3V, and V
CCAUX
J
CCINT
CCO
= 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage
limits with V = 1.26V, V = 3.6V, and V = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design
CCINT
CCO
CCAUX
with no functional elements instantiated). For conditions other than those described above (for example, a design including functional
elements), measured quiescent current levels will be different than the values in the table.
3. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power
consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A FPGA XPower Estimator provides quick, approximate,
typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as
well as more accurate typical estimates.
4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
5. For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
15
DC and Switching Characteristics
Single-Ended I/O Standards
Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
VCCO for Drivers(2)
VREF
VIL
Max (V)
0.8
VIH
Min (V)
IOSTANDARD
Attribute
Min (V) Max (V)
Nom (V)
3.3
3.3
2.5
1.8
1.5
1.2
3.3
3.3
1.5
1.5
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
Min (V)
Nom (V)
Max (V)
LVTTL
3.0
3.0
2.3
1.65
1.4
1.1
3.0
3.0
1.4
1.4
1.7
1.7
1.7
1.7
1.7
2.3
2.3
3.0
3.0
3.6
3.6
2.7
1.95
1.6
1.3
3.6
3.6
1.6
1.6
1.9
1.9
1.9
1.9
1.9
2.7
2.7
3.6
3.6
2.0
LVCMOS33(4)
LVCMOS25(4,5)
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3(6)
PCI66_3(6)
HSTL_I
0.8
2.0
0.7
1.7
0.4
0.8
VREF is not used for
these I/O standards
0.4
0.8
0.4
0.7
0.3 • VCCO
0.3 • VCCO
VREF – 0.1
0.5 • VCCO
0.5 • VCCO
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.125
VREF + 0.125
VREF + 0.150
VREF + 0.150
VREF + 0.2
VREF + 0.2
0.68
–
0.75
0.9
0.9
-
HSTL_III
VREF – 0.1
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
0.8
0.9
1.1
–
VREF – 0.1
–
0.9
V
REF – 0.1
REF – 0.1
–
1.1
–
V
0.833
0.833
1.13
1.13
1.3
0.900
0.900
1.25
1.25
1.5
0.969
0.969
1.38
1.38
1.7
1.7
VREF – 0.125
V
REF – 0.125
REF – 0.150
V
SSTL2_II
VREF – 0.150
SSTL3_I
V
V
REF – 0.2
REF – 0.2
SSTL3_II
1.3
1.5
Notes:
1. Descriptions of the symbols used in this table are as follows:
V
V
V
V
– the supply voltage for output drivers
– the reference voltage for setting the input switching threshold
– the input voltage that indicates a Low logic level
– the input voltage that indicates a High logic level
CCO
REF
IL
IH
2. In general, the V
rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when V
= 3.3V range
CCAUX
CCO
and for PCI I/O standards.
3. For device operation, the maximum signal voltage (V max) can be as high as V max. See Table 8.
IH
IN
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the V
rail and use the LVCMOS25 or
CCAUX
LVCMOS33 standard depending on V
. The dual-purpose configuration pins use the LVCMOS standard before the User mode. When
CCAUX
using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V
throughout configuration.
lines of Banks 0, 1, and 2 at power-on as well as
CCO
6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins. The PCIX
IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.
16
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards(Continued)
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
Test
Conditions
Logic Level
Characteristics
Test
Conditions
Logic Level
Characteristics
IOL
(mA) (mA)
IOH
VOL
Max (V)
VOH
Min (V)
IOL
(mA) (mA)
IOH
VOL
Max (V)
VOH
Min (V)
IOSTANDARD
Attribute
IOSTANDARD
Attribute
PCI33_3(5)
1.5
1.5
8
–0.5 10% VCCO 90% VCCO
–0.5 10% VCCO 90% VCCO
LVTTL(3)
2
4
6
8
2
4
–2
–4
0.4
0.4
0.4
0.4
2.4
PCI66_3(5)
HSTL_I(4)
–8
–8
0.4
0.4
0.4
0.4
0.4
VCCO - 0.4
VCCO - 0.4
VCCO - 0.4
VCCO - 0.4
VCCO - 0.4
6
–6
HSTL_III(4)
HSTL_I_18
HSTL_II_18(4)
HSTL_III_18
SSTL18_I
SSTL18_II(4)
SSTL2_I
24
8
8
–8
–8
12
16
24
2
12
16
24
2
–12
–16
–24
–2
16
24
6.7
–16
–8
VTT – 0.475 VTT + 0.475
TT – 0.603 VTT + 0.603
–8.1 VTT – 0.61 VTT + 0.61
16.2 –16.2 VTT – 0.81 VTT + 0.81
–6.7
LVCMOS33(3)
LVCMOS25(3)
LVCMOS18(3)
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
V
13.4 –13.4
8.1
4
4
–4
6
6
–6
SSTL2_II(4)
SSTL3_I
8
8
–8
8
–8
VTT – 0.6
VTT – 0.8
VTT + 0.6
VTT + 0.8
12
16
24(4)
2
12
16
24
2
–12
–16
–24
–2
SSTL3_II
16
–16
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 8 and Table 11.
2. Descriptions of the symbols used in this table are as follows:
4
4
–4
I – the output current condition under which V is tested
OL
OOHL – the output current condition under which V is tested
6
6
–6
I
OH
V – the output voltage that indicates a Low logic level
OOHL – the output voltage that indicates a High logic level
CCO – the supply voltage for output drivers
8
8
–8
V
V
12
16(4)
24(4)
2
12
16
24
2
–12
–16
–24
–2
V – the voltage applied to a resistor termination
TT
3. For the LVCMOS and LVTTL standards: the same V and V
OL
OH
limits apply for the Fast, Slow, and QUIETIO slew attributes.
4. These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
4
4
–4
5. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The
PCIX IOSTANDARD is available and has equivalent
characteristics but no PCI-X IP is supported.
6
6
–6
8
8
–8
12(4)
16(4)
2
12
16
2
–12
–16
–2
LVCMOS15(3)
0.4
0.4
VCCO – 0.4
4
4
–4
6
6
–6
8(4)
12(4)
2
8
–8
12
2
–12
–2
LVCMOS12(3)
VCCO – 0.4
4(4)
6(4)
4
–4
6
–6
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
17
DC and Switching Characteristics
Differential I/O Standards
Differential Input Pairs
VINP
VINN
Differential
I/O Pair Pins
P
N
Internal
Logic
VINN
V
50%
ID
VINP
V
ICM
GND level
V
INP + VINN
V
ICM = Input common mode voltage =
2
VINP - VINN
V
ID = Differential input voltage =
DS529-3_10_012907
Figure 4: Differential Input Voltages
Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
VCCO for Drivers(1)
VID VICM
Max (V) Min (mV) Nom (mV) Max (mV) Min (V)
(2)
IOSTANDARD Attribute
Min (V)
2.25
3.0
Nom (V)
2.5
Nom (V)
Max (V)
2.35
(3)
LVDS_25
2.75
3.6
100
100
100
200
200
100
100
100
100
150
100
100
100
100
100
100
100
100
100
100
100
100
100
350
350
300
–
600
600
–
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
2.7
0.2
0.2
0.8
0.8
0.8
0.68
–
1.25
1.25
1.3
1.2
1.2
1.2
1.2
1.2
1.2
–
(3)
LVDS_33
3.3
2.35
(4)
BLVDS_25
2.25
2.25
3.0
2.5
2.75
2.75
3.6
2.35
(3)
MINI_LVDS_25
2.5
600
600
1000
1000
–
1.95
(3)
MINI_LVDS_33
3.3
–
1.95
(5)
LVPECL_25
Inputs Only
Inputs Only
2.5
800
800
200
200
–
1.95
(5)
(6)
LVPECL_33
2.8
(3)
RSDS_25
2.25
3.0
3.14
2.25
3.0
1.7
1.7
1.7
1.4
1.4
1.7
1.7
2.3
2.3
3.0
3.0
2.75
3.6
3.47
2.75
3.6
1.9
1.9
1.9
1.6
1.6
1.9
1.9
2.7
2.7
3.6
3.6
1.5
1.5
3.23
2.3
2.3
1.1
1.1
1.1
0.9
–
(3)
RSDS_33
3.3
–
(3, 4, 7)
TMDS_33
3.3
1200
400
400
–
(3)
PPDS_25
2.5
–
–
(3)
PPDS_33
3.3
–
–
DIFF_HSTL_I_18
1.8
–
–
(8)
DIFF_HSTL_II_18
1.8
–
–
–
DIFF_HSTL_III_18
DIFF_HSTL_I
1.8
–
–
–
1.5
–
–
DIFF_HSTL_III
DIFF_SSTL18_I
1.5
–
–
0.9
–
1.8
–
–
0.7
0.7
1.0
1.0
1.1
1.1
1.1
1.1
1.5
1.5
1.9
1.9
(8)
DIFF_SSTL18_II
1.8
–
–
–
DIFF_SSTL2_I
2.5
–
–
–
(8)
DIFF_SSTL2_II
2.5
–
–
–
DIFF_SSTL3_I
DIFF_SSTL3_II
3.3
–
–
–
3.3
–
–
–
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The VCCO rails supply only differential output drivers, not input circuits.
VICM must be less than VCCAUX
.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
See "External Termination Requirements for Differential I/O," page 20.
LVPECL is supported on inputs only, not outputs. LVPECL_33 requires VCCAUX=3.3V 10%.
LVPECL_33 maximum VICM = the lower of 2.8V or VCCAUX – (VID / 2)
Requires VCCAUX = 3.3V 10% for inputs. (VCCAUX – 300 mV) ≤ VICM ≤ (VCCAUX – 37 mV)
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.
18
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Differential Output Pairs
VOUTP
VOUTN
Differential
I/O Pair Pins
P
N
Internal
Logic
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
V
OUTP + VOUTN
V
OCM = Output common mode voltage =
2
VOUTP - VOUTN
= Output voltage indicating a High logic level
= Output voltage indicating a Low logic level
V
OD = Output differential voltage =
VOH
VOL
DS529-3_11_012907
Figure 5: Differential Output Voltages
Table 14: DC Characteristics of User I/Os Using Differential Signal Standards
VOD
VOCM
VOH
VOL
Typ
(mV)
IOSTANDARD Attribute Min (mV)
Max (mV)
Min (V)
Typ (V)
Max (V)
Min (V)
Max (V)
LVDS_25
247
247
240
300
300
100
100
400
100
100
–
350
350
350
–
454
454
460
600
600
400
400
800
400
400
–
1.125
–
–
1.375
–
–
–
LVDS_33
1.125
1.375
–
BLVDS_25
–
1.30
–
–
–
–
MINI_LVDS_25
MINI_LVDS_33
RSDS_25
1.0
1.4
–
–
–
1.0
–
1.4
–
–
–
1.0
–
1.4
–
–
RSDS_33
–
1.0
–
1.4
–
–
TMDS_33
–
VCCO – 0.405
–
VCCO – 0.190
–
–
PPDS_25
–
0.5
0.5
–
0.8
0.8
–
1.4
1.4
–
–
–
PPDS_33
–
–
–
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
–
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VTT + 0.475 VTT – 0.475
VTT + 0.603 VTT – 0.603
–
–
–
–
–
–
–
–
–
–
–
–
VTT + 0.61
VTT + 0.81
VTT + 0.6
VTT + 0.8
VTT – 0.61
VTT – 0.81
VTT – 0.6
VTT – 0.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8 and Table 13.
2. See "External Termination Requirements for Differential I/O," page 20.
3. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ω across the N and P pins of the
T
differential signal pair.
4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25,
MINI_LVDS_25, PPDS_25 when V
=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when V
www.xilinx.com
= 3.3V
CCO
CCO
DS529-3 (v2.0) August 19, 2010
19
DC and Switching Characteristics
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
Bank 0 and 2
Any Bank
Bank 0
Bank 0
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
1
/ th of Bourns
4
Part Number
Bank 2
Bank 2
CAT16-PT4F4
Z
0
0
= 50Ω
= 50Ω
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
VCCO = 3.3V VCCO = 2.5V
LVDS_33,
LVDS_25,
100Ω
MINI_LVDS_33,
RSDS_33,
PPDS_33
MINI_LVDS_25,
RSDS_25,
PPDS_25
Z
DIFF_TERM=No
a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint
VCCO = 3.3V VCCO = 2.5V
Z
0
= 50Ω
= 50Ω
LVDS_33,
LVDS_25,
MINI_LVDS_33,
RSDS_33,
PPDS_33
MINI_LVDS_25,
RSDS_25,
PPDS_25
VCCO = 3.3V VCCO = 2.5V
LVDS_33,
LVDS_25,
RDT
MINI_LVDS_33,
RSDS_33,
PPDS_33
MINI_LVDS_25,
RSDS_25,
PPDS_25
Z
0
DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint
DS529-3_09_020107
Figure 6: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
Any Bank
Bank 0
Any Bank
Bank 0
1
1
/ th of Bourns
4
/ th of Bourns
4
Part Number
Part Number
CAT16-LV4F12
CAT16-PT4F4
Bank 2
Bank 2
V
CCO = 2.5V
Z
0
0
= 50Ω
= 50Ω
No VCCO Requirement
165Ω
140Ω
165Ω
100Ω BLVDS_25
BLVDS_25
Z
DS529-3_07_020107
Figure 7: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
Any Bank
Bank 0
Bank 0 and 2
Bank 0
3.3V
Bank 2
Bank 2
50Ω
50Ω
V
CCAUX = 3.3V
V
CCO = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS529-3_08_020107
Figure 8: External Input Resistors Required for TMDS_33 I/O Standard
Device DNA Read Endurance
Table 15: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
Read
cycles
DNA_CYCLES
30,000,000
20
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Switching Characteristics
All Spartan-3A FPGAs ship in two speed grades: –4 and the
higher performance –5. Switching characteristics in this
document are designated as Advance, Preliminary, or
Production, as shown in Table 16. Each category is defined
as follows:
To create a Xilinx user account and sign up for automatic
E-mail notification whenever this data sheet is updated:
•
Sign Up for Alerts
www.xilinx.com/support/answers/18683.htm
Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The
Spartan-3A FPGA speed files (v1.41), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for these
files are shown in Table 16. For more complete, more
precise, and worst-case data, use the values reported by the
Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Advance: These specifications are based on simulations
only and are typically available soon after establishing
FPGA specifications. Although speed grades with this
designation are considered relatively stable and
conservative, some under-reporting might still occur.
Preliminary: These specifications are based on complete
early silicon characterization. Devices and speed grades
with this designation are intended to give a better indication
of the expected performance of production silicon. The
probability of under-reporting preliminary delays is greatly
reduced compared to Advance data.
Production: These specifications are approved once
enough production silicon of a particular device has been
characterized to provide full correlation between speed files
and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal
notification of any subsequent changes. Typically, the
slowest speed grades transition to Production before faster
speed grades.
Table 16: Spartan-3A v1.41 Speed Grade Designation
Device
XC3S50A
Advance
Preliminary
Production
-4, -5
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
-4, -5
-4, -5
-4, -5
-4, -5
Software Version Requirements
Table 17 provides the recent history of the Spartan-3A
FPGA speed files.
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Advance or Preliminary should not be
used in a production-quality system.
Table 17: Spartan-3A Speed File Version History
ISE
Version
1.41
Release
Description
ISE 10.1.03 Updated Automotive output delays
ISE 10.1.02 Updated Automotive input delays.
ISE 10.1.01 Added Automotive parts.
1.40
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx®
ISE® software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and
software updates.
1.39
1.38
ISE 9.2.03i Added Absolute Minimum values.
Updated pin-to-pin setup and hold
times (Table 19), TMDS output
ISE 9.2.01i adjustment (Table 26) multiplier
setup/hold times (Table 34), and block
RAM clock width (Table 35).
1.37
1.36
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
ISE 9.2i;
XC3S400A, all speed grades and all
previously temperature grades, upgraded to
available via Production
Answer
Record
AR24992
XC3S50A, XC3S200A, XC3S700A,
Answer
XC3S1400A, all speed grades and all
Record
1.35
1.34
temperature grades, upgraded to
Production.
AR24992
XC3S700A and XC3S1400A -4 speed
ISE 9.1.03i grade upgraded to Production. Updated
pin-to-pin timing numbers.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
21
DC and Switching Characteristics
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Max
Max
Units
Clock-to-Output Times
TICKOFDCM
When reading from the Output
LVCMOS25(2), 12mA
XC3S50A
3.18
3.21
2.97
3.39
3.51
4.59
4.88
4.68
4.97
5.06
3.42
3.27
3.33
3.50
3.99
5.02
5.24
5.12
5.34
5.69
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Flip-Flop (OFF), the time from the output drive, Fast slew
rate, with DCM(3)
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
active transition on the Global
Clock pin to data appearing at the
Output pin. The DCM is in use.
TICKOF
When reading from OFF, the time LVCMOS25(2), 12mA
from the active transition on the output drive, Fast slew
Global Clock pin to data appearing rate, without DCM
at the Output pin. The DCM is not
in use.
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 23. If the latter is true, add the appropriate Output adjustment from Table 26.
3. DCM output jitter is included in all measurements.
22
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
-5
-4
Symbol
Setup Times
TPSDCM
Description
Conditions
Device
Min
Min
Units
When writing to the Input
Flip-Flop (IFF), the time from the IFD_DELAY_VALUE = 0,
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2)
,
XC3S50A
2.45
2.59
2.38
2.38
1.91
2.55
2.32
2.21
2.28
2.33
2.68
2.84
2.68
2.57
2.17
2.76
2.76
2.60
2.63
2.41
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
with DCM(4)
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
TPSFD
When writing to IFF, the time from LVCMOS25(2)
the setup of data at the Input pin IFD_DELAY_VALUE = 5,
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
,
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
without DCM
Hold Times
TPHDCM
When writing to IFF, the time from LVCMOS25(3)
,
XC3S50A
-0.36
-0.52
-0.33
-0.17
-0.07
-0.63
-0.56
-0.42
-0.80
-0.69
-0.36
-0.52
-0.29
-0.12
0.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
the active transition at the Global IFD_DELAY_VALUE = 0,
Clock pin to the point when data with DCM(4)
must be held at the Input pin. The
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
DCM is in use. No Input Delay is
programmed.
TPHFD
When writing to IFF, the time from LVCMOS25(3)
,
-0.58
-0.56
-0.42
-0.75
-0.69
the active transition at the Global IFD_DELAY_VALUE = 5,
Clock pin to the point when data without DCM
must be held at the Input pin. The
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
DCM is not in use. The Input
Delay is programmed.
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 23. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 23. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
23
DC and Switching Characteristics
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Speed Grade
IFD_
DELAY_
VALUE
-5
-4
Symbol
Setup Times
TIOPICK
Description
Conditions
Device
Min
Min
Units
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
No Input Delay is programmed.
LVCMOS25(2)
0
XC3S50A
1.56
1.71
1.30
1.34
1.36
2.16
3.10
3.51
4.04
3.88
4.72
5.47
5.97
2.05
2.72
3.38
3.88
3.69
4.56
5.34
5.85
1.79
2.43
3.02
3.49
3.41
4.20
4.96
5.44
1.58
1.81
1.51
1.51
1.74
2.18
3.12
3.76
4.32
4.24
5.09
5.94
6.52
2.20
2.93
3.78
4.37
4.20
5.23
6.11
6.71
2.02
2.67
3.43
3.96
3.95
4.81
5.66
6.19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
TIOPICKD
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S200A
XC3S400A
24
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Speed Grade
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
IFD_
DELAY_
VALUE
-5
-4
Symbol
TIOPICKD
Description
Conditions
Device
Min
Min
1.95
2.83
3.72
4.31
4.14
5.19
6.10
6.73
2.17
2.92
3.76
4.32
4.19
5.09
5.98
6.57
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop (IFF).
The Input Delay is programmed.
LVCMOS25(2)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S700A
1.82
2.62
3.32
3.83
3.69
4.60
5.39
5.92
1.79
2.55
3.38
3.75
3.81
4.39
5.16
5.69
XC3S1400A
Hold Times
TIOICKP
Time from the active transition at the LVCMOS25(3)
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. No Input Delay is
programmed.
0
XC3S50A
–0.66
–0.85
–0.42
–0.81
–0.71
–0.88
–1.33
–2.05
–2.43
–2.34
–2.81
–3.03
–3.83
–1.51
–2.09
–2.40
–2.68
–2.56
–2.99
–3.29
–3.61
–0.64
–0.65
–0.42
–0.67
–0.71
–0.88
–1.33
–2.05
–2.43
–2.34
–2.81
–3.03
–3.57
–1.51
–2.09
–2.40
–2.68
–2.56
–2.99
–3.29
–3.61
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S50A
TIOICKPD
Time from the active transition at the LVCMOS25(3)
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S200A
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
25
DC and Switching Characteristics
Table 20: Setup and Hold Times for the IOB Input Path(Continued)
Speed Grade
IFD_
DELAY_
VALUE
-5
-4
Symbol
TIOICKPD
Description
Conditions
Device
Min
Min
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Time from the active transition at the LVCMOS25(3)
ICLK input of the Input Flip-Flop (IFF)
to the point where data must be held
at the Input pin. The Input Delay is
programmed.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S400A
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
–1.12
–1.70
–2.08
–2.38
–2.23
–2.69
–3.08
–3.35
–1.67
–2.27
–2.59
–2.92
–2.89
–3.22
–3.52
–3.81
–1.60
–2.06
–2.46
–2.86
–2.88
–3.24
–3.55
–3.89
XC3S700A
XC3S1400A
Set/Reset Pulse Width
Minimum pulse width to SR control
input on IOB
-
-
1.61
All
1.33
ns
TRPW_IOB
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 21: Sample Window (Source Synchronous)
Max
Symbol
Description
Units
TSAMP
Setup and hold
capture window of
an IOB flip-flop.
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
ps
• Answer Record 30879
26
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Input Propagation Times
Table 22: Propagation Times for the IOB Input Path
Speed Grade
-5
-4
Symbol
Description
Conditions
DELAY_VALUE
Device
Max
Max Units
Propagation Times
TIOPI
The time it takes for data to travel
from the Input pin to the I output with
no input delay programmed
LVCMOS25(2)
IBUF_DELAY_VALUE=0 XC3S50A
XC3S200A
1.04
0.87
0.65
0.92
1.12
0.87
0.72
0.92
1.21
2.07
2.46
2.71
3.21
3.46
3.84
4.19
4.47
4.11
4.50
4.67
5.20
5.44
5.95
6.28
6.57
1.65
1.97
2.33
2.96
3.19
3.60
4.02
4.26
3.86
4.25
4.55
5.24
5.53
5.94
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S400A
XC3S700A
XC3S1400A 0.96
TIOPID
The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2)
1
2
XC3S50A
1.79
2.13
2.36
2.88
3.11
3.45
3.75
4.00
3.61
3.95
4.18
4.75
4.98
5.31
5.62
5.86
1.57
1.87
2.16
2.68
2.87
3.20
3.57
3.79
3.42
3.79
4.02
4.62
4.86
5.18
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
XC3S200A
2
3
4
5
6
7
8
9
10
11
12
13
14
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
27
DC and Switching Characteristics
Table 22: Propagation Times for the IOB Input Path(Continued)
Speed Grade
-5
-4
Symbol
TIOPID
Description
Conditions
DELAY_VALUE
Device
Max
5.43
5.75
1.32
1.67
1.90
2.33
2.60
2.94
3.23
3.50
3.18
3.53
3.76
4.26
4.51
4.85
5.14
5.40
1.84
2.20
2.46
2.93
3.21
3.54
3.86
4.13
3.82
4.17
4.43
4.95
5.22
5.57
5.89
6.16
Max Units
The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2)
15
16
1
XC3S200A
6.24
6.59
1.43
1.83
2.07
2.52
2.91
3.20
3.51
3.85
3.55
3.95
4.20
4.67
4.97
5.32
5.64
5.95
1.87
2.27
2.60
3.15
3.45
3.80
4.16
4.48
4.19
4.58
4.89
5.49
5.83
6.21
6.55
6.89
2.18
2.59
2.84
3.30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S400A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
XC3S700A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
XC3S1400A 1.95
2
2.29
2.54
2.96
3
4
28
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Speed Grade
Table 22: Propagation Times for the IOB Input Path(Continued)
-5
-4
Symbol
TIOPID
Description
Conditions
DELAY_VALUE
Device
Max
Max Units
The time it takes for data to travel
from the Input pin to the I output with
the input delay programmed
LVCMOS25(2)
5
6
XC3S1400A 3.17
3.52
3.92
4.18
4.57
4.31
4.79
5.06
5.51
5.73
6.08
6.33
6.77
1.81
2.04
1.74
1.74
1.97
2.41
3.35
3.98
4.55
4.47
5.32
6.17
6.75
2.43
3.16
4.01
4.60
4.43
5.46
6.33
6.94
2.25
2.90
3.66
4.19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.52
3.82
4.10
3.84
4.20
4.46
4.87
5.07
5.43
5.73
6.01
7
8
9
10
11
12
13
14
15
16
TIOPLI
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
LVCMOS25(2)
IFD_DELAY_VALUE=0 XC3S50A
XC3S200A
1.70
1.85
1.44
1.48
XC3S400A
XC3S700A
XC3S1400A 1.50
TIOPLID
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2)
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
XC3S50A
XC3S200A
XC3S400A
2.30
3.24
3.65
4.18
4.02
4.86
5.61
6.11
2.19
2.86
3.52
4.02
3.83
4.70
5.48
5.99
1.93
2.57
3.16
3.63
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
29
DC and Switching Characteristics
Table 22: Propagation Times for the IOB Input Path(Continued)
Speed Grade
-5
-4
Symbol
Description
Conditions
DELAY_VALUE
Device
Max
3.55
4.34
5.09
5.58
1.96
2.76
3.45
3.97
3.83
4.74
5.53
6.06
Max Units
TIOPLID
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
LVCMOS25(2)
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
XC3S400A
4.18
5.03
5.88
6.42
2.18
3.06
3.95
4.54
4.37
5.42
6.33
6.96
2.40
3.15
3.99
4.55
4.42
5.32
6.21
6.80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC3S700A
XC3S1400A 1.93
2.69
3.52
3.89
3.95
4.53
5.30
5.83
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 23.
30
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Input Timing Adjustments
Table 23: Input Timing Adjustments by IOSTANDARD(Continued)
Table 23: Input Timing Adjustments by IOSTANDARD
Add the
Add the
Adjustment Below
Adjustment Below
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
Speed Grade
Speed Grade
(IOSTANDARD)
-5
-4
Units
(IOSTANDARD)
-5
-4
Units
Differential Standards
LVDS_25
Single-Ended Standards
LVTTL
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.62
0.54
0
0.62
0.54
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDS_33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.69
0.69
0.79
0.71
0.71
0.68
0.68
0.78
0.78
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.69
0.69
0.79
0.71
0.71
0.68
0.68
0.78
0.78
LVPECL_33
RSDS_25
PCI66_3
RSDS_33
HSTL_I
TMDS_33
HSTL_III
PPDS_25
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
SSTL2_II
SSTL3_I
SSTL3_II
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
31
DC and Switching Characteristics
Output Propagation Times
Table 24: Timing for the IOB Output Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Max
Max
Units
Clock-to-Output Times
TIOCKP
When reading from the Output Flip-Flop (OFF), LVCMOS25(2), 12 mA output
the time from the active transition at the OCLK drive, Fast slew rate
input to data appearing at the Output pin
All
2.87
2.78
3.13
2.91
ns
Propagation Times
TIOOP
The time it takes for data to travel from the IOB’s LVCMOS25(2), 12 mA output
All
All
ns
O input to the Output pin
drive, Fast slew rate
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
LVCMOS25(2), 12 mA output
drive, Fast slew rate
3.63
8.62
3.89
9.65
ns
ns
TIOGSRQ
Time from asserting the Global Set Reset (GSR)
input on the STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
Three-State Output Propagation Times
Table 25: Timing for the IOB Three-State Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Max
Max
Units
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK input of LVCMOS25, 12 mA
the Three-state Flip-Flop (TFF) to when the Output output drive, Fast slew
All
0.63
2.80
0.76
3.06
ns
pin enters the high-impedance state
rate
(2)
TIOCKON
Time from the active transition at TFF’s OTCLK input
to when the Output pin drives valid data
All
All
ns
ns
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State (GTS) LVCMOS25, 12 mA
9.47
10.36
input on the STARTUP_SPARTAN3A primitive to
when the Output pin enters the high-impedance
state
output drive, Fast slew
rate
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
All
1.61
3.57
1.86
3.82
ns
ns
Output pin enters a high-impedance state
(2)
TIOSRON
Time from asserting TFF’s SR input at TFF to when
the Output pin drives valid data
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 26.
32
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Output Timing Adjustments
Table 26: Output Timing Adjustments for IOB(Continued)
Table 26: Output Timing Adjustments for IOB
Add the
Add the
Adjustment
Adjustment
Below
Below
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Speed Grade
Speed Grade
-5
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-5
-4
Units
LVCMOS33
Slow
2 mA
4 mA
5.58
3.17
3.17
2.09
1.24
1.15
5.58
3.17
3.17
2.09
1.24
1.15
Single-Ended Standards
LVTTL
Slow
2 mA
4 mA
5.58
3.16
3.17
2.09
1.62
1.24
5.58
3.16
3.17
2.09
1.62
1.24
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 mA
8 mA
6 mA
12 mA
16 mA
24 mA
2 mA
8 mA
12 mA
16 mA
24 mA
2 mA
2.55(3) 2.55(3)
2.74(3) 2.74(3)
Fast
3.02
1.71
3.02
1.71
4 mA
Fast
3.03
1.71
3.03
1.71
6 mA
1.72
1.72
4 mA
8 mA
0.53
0.53
6 mA
1.71
1.71
12 mA
16 mA
24 mA
2 mA
0.59
0.59
8 mA
0.53
0.53
0.59
0.59
12 mA
16 mA
24 mA
2 mA
0.53
0.53
0.51
0.51
0.59
0.59
QuietIO
27.67
27.67
27.67
16.71
16.29
16.18
12.11
27.67
27.67
27.67
16.71
16.29
16.18
12.11
0.60
0.60
4 mA
QuietIO
27.67
27.67
27.67
16.71
16.67
16.22
12.11
27.67
27.67
27.67
16.71
16.67
16.22
12.11
6 mA
4 mA
8 mA
6 mA
12 mA
16 mA
24 mA
8 mA
12 mA
16 mA
24 mA
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
33
DC and Switching Characteristics
Table 26: Output Timing Adjustments for IOB(Continued)
Table 26: Output Timing Adjustments for IOB(Continued)
Add the
Add the
Adjustment
Adjustment
Below
Below
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Speed Grade
Speed Grade
-5
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-5
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS25
Slow
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
5.33
2.81
2.82
1.14
1.10
0.83
5.33
2.81
2.82
1.14
1.10
0.83
LVCMOS15
Slow
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
5.82
3.97
3.21
2.53
2.06
5.23
3.05
1.95
1.60
1.30
34.11
25.66
24.64
22.06
20.64
7.14
4.87
5.67
6.77
5.02
4.09
50.76
43.17
37.31
0.34
0.34
0.78
1.16
0.35
0.30
0.47
0.40
0.30
0
5.82
3.97
3.21
2.53
2.06
5.23
3.05
1.95
1.60
1.30
34.11
25.66
24.64
22.06
20.64
7.14
4.87
5.67
6.77
5.02
4.09
50.76
43.17
37.31
0.34
0.34
0.78
1.16
0.35
0.30
0.47
0.40
0.30
0
Fast
2.26(3) 2.26(3)
Fast
4.36
1.76
1.25
0.38
0
4.36
1.76
1.25
0.38
0
QuietIO
0.01
0.01
25.92
25.92
25.92
15.57
15.59
14.27
11.37
4.48
3.69
2.91
1.99
1.57
1.19
3.96
2.57
1.90
1.06
0.83
0.63
24.97
24.97
24.08
16.43
14.52
13.41
0.01
0.01
25.92
25.92
25.92
15.57
15.59
14.27
11.37
4.48
3.69
2.91
1.99
1.57
1.19
3.96
2.57
1.90
1.06
0.83
0.63
24.97
24.97
24.08
16.43
14.52
13.41
QuietIO
LVCMOS12
Slow
Fast
LVCMOS18
Slow
Fast
QuietIO
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
QuietIO
SSTL2_II
SSTL3_I
–0.05
0
–0.05
0
SSTL3_II
0.17
0.17
34
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Table 26: Output Timing Adjustments for IOB(Continued)
Add the
Adjustment
Below
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Speed Grade
-5
-4
Units
Differential Standards
LVDS_25
1.16
0.46
0.11
0.75
0.40
1.16
0.46
0.11
0.75
0.40
ns
ns
ns
ns
ns
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
Input Only
LVPECL_33
RSDS_25
1.42
0.58
0.46
1.07
0.63
0.43
0.41
0.36
1.01
0.54
0.49
0.41
0.82
0.09
1.16
0.28
1.42
0.58
0.46
1.07
0.63
0.43
0.41
0.36
1.01
0.54
0.49
0.41
0.82
0.09
1.16
0.28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
3. Note that 16 mA drive is faster than 24 mA drive for the Slow
slew rate.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
35
DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 27 lists the conditions to use for each
standard.
LVCMOS, LVTTL), then RT is set to 1MΩ to indicate an open
connection, and VT is set to zero. The same measurement
point (VM) that was used at the Input is also used at the
Output.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
V (V
)
T
REF
FPGA Output
R (R
T
)
REF
V
(V
)
M
MEAS
)
C (C
L
REF
The Output test setup is shown in Figure 9. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
DS312-3_04_102406
Notes:
1. The names shown in parentheses are
used in the IBIS file.
Figure 9: Output Test Setup
Table 27: Test Methods for Timing Measurement at I/Os
Inputs and
Outputs
Inputs
Outputs
Signal Standard
(IOSTANDARD)
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
Single-Ended
LVTTL
-
-
-
-
-
-
-
0
3.3
3.3
1M
1M
1M
1M
1M
1M
25
25
25
25
50
50
50
25
50
50
25
50
25
50
25
0
0
1.4
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
0
1.65
1.25
0.9
0
2.5
0
0
1.8
0
0
0
1.5
0
0.75
0.6
1.2
0
Rising
Falling
Rising
Falling
Note 3
Note 3
0
0.94
2.03
0.94
2.03
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
3.3
0
PCI66_3
-
Note 3
Note 3
3.3
0.75
1.5
0.9
0.9
1.8
0.9
0.9
1.25
1.25
1.5
1.5
HSTL_I
0.75
0.9
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.75
VREF – 0.75
VREF – 0.75
VREF – 0.75
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.75
VREF + 0.75
VREF + 0.75
VREF + 0.75
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
0.9
0.9
1.1
0.9
0.9
1.25
1.25
1.5
SSTL2_II
SSTL3_I
SSTL3_II
1.5
36
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Inputs and
Table 27: Test Methods for Timing Measurement at I/Os(Continued)
Inputs
Outputs
Outputs
Signal Standard
(IOSTANDARD)
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
Differential
LVDS_25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.3
VICM – 0.3
VICM – 0.1
VICM – 0.1
VICM – 0.1
VICM – 0.1
VICM – 0.1
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM – 0.5
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.3
VICM + 0.3
VICM + 0.1
VICM + 0.1
VICM + 0.1
VICM + 0.1
VICM + 0.1
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
VICM + 0.5
50
50
1M
50
50
N/A
N/A
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
1.2
1.2
0
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
1.2
1.2
N/A
N/A
1.2
1.2
3.3
0.8
0.8
0.75
1.5
0.9
0.9
1.8
0.9
0.9
1.25
1.25
1.5
1.5
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Notes:
1. Descriptions of the relevant symbols are as follows:
V
V
V
– The reference voltage for setting the input switching threshold
– The common mode input voltage
– Voltage of measurement point on signal transition
REF
ICM
M
V – Low-level test voltage at Input pin
L
V
– High-level test voltage at Input pin
H
R – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
T
V – Termination voltage
T
2. The load capacitance (C ) at the Output pin is 0 pF for all signal standards.
L
3. According to the PCI specification.
The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the
speed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used for
all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those
measurements to produce the final timing numbers as published in the speed files and data sheet.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
37
DC and Switching Characteristics
Using IBIS Models to Simulate Load Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
with the parameters used in Table 27 (VT, RT, and VM). Do
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 9.
Use parameter values VT, RT, and VM from Table 27.
C
REF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output driver
connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF
,
and VMEAS values) or capacitive value to represent the
load.
www.xilinx.com/support/download/index.htm
4. Record the time to VMEAS
.
Delays for a given application are simulated according to its
specific load conditions as follows:
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 26) to
yield the worst-case delay of the PCB trace.
Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Table 28 and Table 29 provide the essential SSO guidelines.
For each device/package combination, Table 28 provides
the number of equivalent VCCO/GND pairs. The equivalent
number of pairs is based on characterization and may not
match the physical number of pairs. For each output signal
standard and drive strength, Table 29 recommends the
maximum number of SSOs, switching in the same direction,
allowed per VCCO/GND pair within an I/O bank. The
guidelines in Table 29 are categorized by package style,
slew rate, and output drive current. Furthermore, the
number of SSOs is specified by I/O bank. Generally, the left
and right I/O banks (Banks 1 and 3) support higher output
drive current.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Multiply the appropriate numbers from Table 28 and
Table 29 to calculate the maximum number of SSOs allowed
within an I/O bank. Exceeding these SSO guidelines might
result in increased power or ground bounce, degraded
signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table 28 x Table 29
The recommended maximum SSO values assume that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
The SSO values assume that the VCCAUX is powered at
3.3V. Setting VCCAUX to 2.5V provides better SSO
characteristics.
The number of SSOs allowed for quad-flat packages
(VQ/TQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. Ball
grid array packages are recommended for applications with
a large number of simultaneously switching outputs.
38
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Table 28: Equivalent VCCO/GND Pairs per Bank
Package Style (including Pb-free)
Device
XC3S50A
VQ100
TQ144
FT256
FG320
FG400
FG484
FG676
1
1
–
–
–
2
–
–
–
–
3
4
4
4
4
–
4
4
–
–
–
–
5
5
–
–
–
–
5
6
–
–
–
–
9
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Table 29: Recommended Number of Simultaneously Switching
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (V
=3.3V)(Continued)
Outputs per VCCO-GND Pair (V
=3.3V)
CCAUX
CCAUX
Package Type
Package Type
FT256, FG320,
FG400, FG484,
FG676
FT256, FG320,
FG400, FG484,
FG676
VQ100, TQ144
VQ100, TQ144
Top, Left,
Top,
Left,
Top,
Left,
Top,
Left,
Bottom Right Bottom Right
Bottom Right Bottom Right
Signal Standard
(IOSTANDARD)
(Banks (Banks (Banks (Banks
Signal Standard
(IOSTANDARD)
(Banks (Banks (Banks (Banks
0,2)
24
14
11
10
9
1,3)
24
14
11
10
9
0,2)
76
46
27
20
13
10
–
1,3)
76
46
27
20
13
10
9
0,2)
1,3)
0,2)
1,3)
LVCMOS33
Slow
2
4
Single-Ended Standards
LVTTL
Slow
2
4
20
10
10
6
20
10
10
6
60
41
29
22
13
11
9
60
41
29
22
13
11
9
6
8
6
12
16
24
2
8
8
8
12
16
24
2
6
6
–
8
5
5
Fast
10
8
10
8
10
8
10
8
4
4
4
Fast
10
6
10
6
10
6
10
6
6
5
5
5
5
4
8
4
4
4
4
6
5
5
5
5
12
16
24
2
4
4
4
4
8
3
3
3
3
2
2
2
2
12
16
24
2
3
3
3
3
–
2
–
2
3
3
3
3
QuietIO
36
32
24
16
16
12
–
36
32
24
16
16
12
10
76
46
32
26
18
14
–
76
46
32
26
18
14
10
2
2
2
2
4
QuietIO
40
24
20
16
12
9
40
24
20
16
12
9
80
48
36
27
16
13
12
80
48
36
27
16
13
12
6
4
8
6
12
16
24
8
12
16
24
9
9
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
39
DC and Switching Characteristics
Table 29: Recommended Number of Simultaneously Switching
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (V
=3.3V)(Continued)
Outputs per VCCO-GND Pair (V
=3.3V)(Continued)
CCAUX
CCAUX
Package Type
Package Type
FT256, FG320,
FG400, FG484,
FG676
FT256, FG320,
FG400, FG484,
FG676
VQ100, TQ144
VQ100, TQ144
Top,
Left,
Top,
Left,
Top,
Left,
Top,
Left,
Bottom Right Bottom Right
Bottom Right Bottom Right
Signal Standard
(IOSTANDARD)
(Banks (Banks (Banks (Banks
Signal Standard
(IOSTANDARD)
(Banks (Banks (Banks (Banks
0,2)
16
10
8
1,3)
16
10
8
0,2)
76
46
33
24
18
–
1,3)
76
46
33
24
18
11
7
0,2)
12
7
1,3)
12
7
0,2)
55
31
18
–
1,3)
55
31
18
15
10
25
10
6
LVCMOS25
Slow
2
4
LVCMOS15
Slow
2
4
6
6
7
7
8
7
7
8
–
6
12
16
24
2
6
6
12
2
–
5
–
–
6
Fast
10
7
10
7
25
10
6
–
5
–
4
Fast
12
10
8
12
10
8
18
14
6
18
14
6
6
6
6
4
8
–
4
–
4
6
12
2
–
3
–
3
8
6
6
6
6
QuietIO
30
21
18
–
30
21
18
12
12
17
13
10
9
70
40
31
–
70
40
31
31
20
40
25
18
31
13
9
12
16
24
2
3
3
3
3
4
–
3
–
3
6
–
2
–
2
8
QuietIO
36
30
24
20
12
–
36
30
24
20
12
12
8
76
60
48
36
36
–
76
60
48
36
36
36
8
12
2
–
–
4
LVCMOS12
Slow
Fast
17
–
40
–
6
4
8
6
–
–
12
16
24
2
2
12
–
31
–
4
9
–
–
6
–
9
–
LVCMOS18
Slow
Fast
13
8
13
8
64
34
22
18
–
64
34
22
18
13
10
18
9
QuietIO
2
36
–
36
33
27
9
55
–
55
36
36
16
13
20
8
4
4
6
8
8
6
–
–
8
7
7
PCI33_3
9
16
–
12
16
2
–
5
PCI66_3
–
9
–
5
–
HSTL_I
–
11
7
–
13
8
13
8
18
9
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
–
–
4
13
–
13
5
17
–
17
5
6
7
7
7
7
8
4
4
4
4
8
8
10
7
8
12
16
2
–
4
–
4
7
13
9
15
9
–
3
–
3
–
–
QuietIO
30
24
20
16
–
30
24
20
16
12
12
64
64
48
36
–
64
64
48
36
36
24
10
–
10
6
18
–
18
9
4
SSTL2_II
SSTL3_I
6
7
8
8
10
7
8
SSTL3_II
5
6
6
12
16
–
–
40
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Table 29: Recommended Number of Simultaneously Switching
Outputs per VCCO-GND Pair (V
=3.3V)(Continued)
CCAUX
Package Type
FT256, FG320,
FG400, FG484,
FG676
VQ100, TQ144
Top,
Left,
Top,
Left,
Bottom Right Bottom Right
Signal Standard
(IOSTANDARD)
(Banks (Banks (Banks (Banks
0,2)
1,3)
0,2)
1,3)
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
8
8
1
8
8
–
–
1
–
–
22
27
4
–
–
4
–
–
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
22
27
Input Only
Input Only
LVPECL_33
RSDS_25
8
8
8
8
8
–
–
6
–
4
3
–
5
–
3
2
–
–
–
–
–
5
3
6
2
4
6
4
5
3
4
3
22
27
27
22
27
–
–
–
–
–
–
10
4
8
2
4
7
4
9
4
5
3
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
–
8
–
5
3
–
9
–
4
3
Notes:
1. Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2. The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the V /V voltage
IL IH
limits for the respective I/O standard.
3. If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
41
DC and Switching Characteristics
Configurable Logic Block (CLB) Timing
Table 30: CLB (SLICEM) Timing
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time
from the active transition at the CLK input to data
appearing at the XQ (YQ) output
–
0.60
–
0.68
ns
Setup Times
TAS
Time from the setup of data at the F or G input to the
active transition at the CLK input of the CLB
0.18
1.58
–
–
0.36
1.88
–
–
ns
ns
TDICK
Time from the setup of data at the BX or BY input to
the active transition at the CLK input of the CLB
Hold Times
TAH
Time from the active transition at the CLK input to the
point where data is last held at the F or G input
0
0
–
–
0
0
–
–
ns
ns
TCKDI
Time from the active transition at the CLK input to the
point where data is last held at the BX or BY input
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
0.63
0.63
0
–
–
0.75
0.75
0
–
–
ns
ns
TCL
FTOG
770
667
MHz
Propagation Times
TILO
The time it takes for data to travel from the CLB’s F
(G) input to the X (Y) output
–
0.62
–
–
0.71
–
ns
ns
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to
the CLB’s SR input
1.33
1.61
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
42
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Table 31: CLB Distributed RAM Switching Characteristics
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
–
1.69
–
2.01
ns
Setup Times
TDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
–0.07
0.18
0.30
–
–
–
–0.02
0.36
0.59
–
–
–
ns
ns
ns
TAS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
TWS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
Hold Times
TDH
Hold time of the BX and BY data inputs after the active transition
at the CLK input of the distributed RAM
0.13
0.01
–
–
0.13
0.01
–
–
ns
ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after
the active transition at the CLK input of the distributed RAM
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
0.88
–
1.01
–
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Table 32: CLB Shift Register Switching Characteristics
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on
the shift register output
–
4.11
–
4.82
ns
Setup Times
TSRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.13
–
0.18
–
ns
Hold Times
TSRLDH
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0.16
0.90
–
–
0.16
1.01
–
–
ns
ns
Clock Pulse Width
TWPH, TWPL
Minimum High or Low pulse width at CLK input
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
43
DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 33: Clock Distribution Switching Characteristics
Maximum
Speed Grade
Description
Symbol
Minimum
-5
-4
Units
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to
O-output delay
TGIO
–
0.22
0.23
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and
I1 inputs. Same as BUFGCE enable CE-input
TGSI
–
0
0.56
350
0.63
334
ns
Frequency of signals distributed on global buffers (all sides)
FBUFG
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
44
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 34: 18 x 18 Embedded Multiplier Timing
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
–
4.36
–
4.88
ns
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
–
–
0.84
4.44
–
–
1.30
4.97
ns
ns
register(2,3)
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register(2,4)
Setup Times
TMSDCK_P
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
3.56
–
3.98
–
ns
TMSDCK_A
TMSDCK_B
Data setup time at the A input before the active transition at the CLK
when using the AREG input register(4)
0.00
0.00
–
–
0.00
0.00
–
–
ns
ns
Data setup time at the B input before the active transition at the CLK
when using the BREG input register(4)
Hold Times
TMSCKD_P
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
0.00
–
0.00
–
ns
TMSCKD_A
TMSCKD_B
Clock Frequency
Data hold time at the A input after the active transition at the CLK
0.35
0.35
–
–
0.45
0.45
–
–
ns
ns
when using the AREG input register(4)
Data hold time at the B input after the active transition at the CLK
when using the BREG input register(4)
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
0
280
0
250
MHz
register(1)
Notes:
1. Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. The PREG register is typically used when inferring a single-stage multiplier.
4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5. The numbers in this table are based on the operating conditions set forth in Table 8.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
45
DC and Switching Characteristics
Block RAM Timing
Table 35: Block RAM Timing
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Clock-to-Output Times
TRCKO
When reading from block RAM, the delay from the active
transition at the CLK input to data appearing at the DOUT
output
–
2.06
–
2.49
ns
Setup Times
TRCCK_ADDR Setup time for the ADDR inputs before the active transition at
the CLK input of the block RAM
0.32
0.28
0.69
1.12
–
–
–
–
0.36
0.31
0.77
1.26
–
–
–
–
ns
ns
ns
ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active
transition at the CLK input of the block RAM
TRCCK_ENB Setup time for the EN input before the active transition at the
CLK input of the block RAM
TRCCK_WEB Setup time for the WE input before the active transition at the
CLK input of the block RAM
Hold Times
TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the
CLK input
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
ns
ns
ns
ns
TRCKD_DIB
Hold time on the DIN inputs after the active transition at the
CLK input
TRCKC_ENB Hold time on the EN input after the active transition at the CLK
input
TRCKC_WEB Hold time on the WE input after the active transition at the CLK
input
Clock Timing
TBPWH
TBPWL
Clock Frequency
High pulse width of the CLK signal
1.56
1.56
–
–
1.79
1.79
–
–
ns
ns
Low pulse width of the CLK signal
FBRAM
Block RAM clock frequency
0
320
0
280
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
46
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Digital Clock Manager (DCM) Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Aspects of DLL operation play a role in all DCM applications.
All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
tables (Table 36 and Table 37) apply to any application that
only employs the DLL component. When the DFS and/or the
PS components are used together with the DLL, then the
specifications listed in the DFS and PS tables (Table 38
through Table 41) supersede any corresponding ones in the
DLL tables. DLL specifications that do not change with the
addition of DFS or PS functions are presented in Table 36
and Table 37.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the
frequency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays for
details.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Delay-Locked Loop (DLL)
Table 36: Recommended Operating Conditions for the DLL
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
5(2)
280(3)
5(2)
250(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN
period
F
F
CLKIN < 150 MHz
CLKIN > 150 MHz
40%
45%
60%
55%
40%
45%
60%
55%
–
–
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
Cycle-to-cycle jitter at the
CLKIN input
FCLKIN < 150 MHz
FCLKIN > 150 MHz
–
–
–
300
150
1
–
–
–
300
150
1
ps
ps
ns
ns
Period jitter at the CLKIN input
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay
from the DCM output to the CLKFB input
1
1
–
–
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 38.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5. The DCM specifications are guaranteed when both adjacent DCMs are locked.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
47
DC and Switching Characteristics
Table 37: Switching Characteristics for the DLL
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max
Units
Output Frequency Ranges
CLKOUT_FREQ_CLK0
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
Frequency for the CLK0 and CLK180 outputs
Frequency for the CLK90 and CLK270 outputs
Frequency for the CLK2X and CLK2X180 outputs
Frequency for the CLKDV output
All
5
5
280
200
334
186
5
5
250
200
334
166
MHz
MHz
MHz
MHz
10
10
CLKOUT_FREQ_DV
0.3125
0.3125
(2,3,4)
Output Clock Jitter
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
Period jitter at the CLK0 output
All
100
150
100
150
ps
ps
ps
ps
ps
–
–
–
–
–
–
–
–
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
Period jitter at the CLK2X and CLK2X180 outputs
150
150
150
150
[0.5%
[0.5%
ofCLKIN
period
ofCLKIN
period
–
–
–
–
+ 100]
+ 100]
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing integer
division
150
150
ps
ps
Period jitter at the CLKDV output when performing non-integer
division
[0.5%
ofCLKIN
period
[0.5%
ofCLKIN
period
–
–
–
–
+ 100]
+ 100]
(4)
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270,
CLK2X, CLK2X180, and CLKDV outputs, including the
All
All
[1% of
CLKIN
period
+ 350]
[1% of
CLKIN
period
+ 350]
ps
BUFGMUX and clock tree duty-cycle distortion
(4)
Phase Alignment
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Phase offset between the CLKIN and CLKFB inputs
150
150
ps
ps
–
–
–
–
Phase offset between DLL outputs
[1% of
CLKIN
period
+ 100]
[1% of
CLKIN
period
+ 100]
CLK0 to CLK2X
(not CLK2X180)
[1% of
CLKIN
period
+ 150]
[1% of
CLKIN
period
+ 150]
ps
All others
–
–
Lock Time
(3)
LOCK_DLL
When using the DLL alone: The
time from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase
5 MHz < F
< 15 MHz
All
All
5
5
ms
µs
–
–
–
–
CLKIN
F
> 15 MHz
600
600
CLKIN
Delay Lines
(5)
DCM_DELAY_STEP
Finest delay resolution, averaged over all steps
15
35
15
35
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 36.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of
“ [1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps.
According to the data sheet, the maximum jitter is [100 ps + 150 ps] = 250ps.
5. The typical delay step size is 23 ps.
48
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Digital Frequency Synthesizer (DFS)
Table 38: Recommended Operating Conditions for the DFS
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
(2)
Input Frequency Ranges
(4)
(4)
F
CLKIN_FREQ_FX
Frequency for the CLKIN input
0.200
333
0.200
333
MHz
CLKIN
(3)
Input Clock Jitter Tolerance
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
F
F
< 150 MHz
> 150 MHz
300
300
ps
ps
ns
–
–
–
–
–
–
CLKFX
CLKFX
150
1
150
1
Period jitter at the CLKIN input
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 36.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM.
Table 39: Switching Characteristics for the DFS
Speed Grade
-5
-4
Symbol
Description
Device
All
Min
5
Max
350
Min
5
Max
320
Units
Output Frequency Ranges
(2)
CLKOUT_FREQ_FX
Frequency for the CLKFX and CLKFX180 outputs
MHz
(3,4)
Output Clock Jitter
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180
outputs.
All
Typ
Max
Typ
Max
Use the Spartan-3A Jitter Calculator:
ps
ps
CLKIN
≤ 20 MHz
www.xilinx.com/support/documentatio
n/data_sheets/s3a_jitter_calc.zip
[1% of
[1% of
[1% of
[1% of
CLKIN
> 20 MHz
CLKFX CLKFX CLKFX CLKFX
period
+ 100]
period
+ 200]
period
+ 100]
period
+ 200]
(5,6)
Duty Cycle
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
All
[1% of
CLKFX
period
+ 350]
[1% of
CLKFX
period
+ 350]
ps
–
–
(6)
Phase Alignment
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL
CLK0 output when both the DFS and DLL are used
All
All
200
200
ps
ps
–
–
–
–
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
[1% of
CLKFX
period
+ 200]
[1% of
CLKFX
period
+ 200]
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
49
DC and Switching Characteristics
Table 39: Switching Characteristics for the DFS(Continued)
Speed Grade
-5
-4
Symbol
Lock Time
Description
Device
Min
Max
Min
Max
Units
(2, 3)
LOCK_FX
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and CLKFX180
signals are valid. If using both the DLL and
the DFS, use the longer locking time.
5 MHz < F
All
5
5
ms
µs
CLKIN
–
–
–
–
< 15 MHz
F
>
450
450
CLKIN
15 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 38.
2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching)
on an XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB
utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the
system application.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “ [1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is [100 ps + 200 ps] = 300 ps.
50
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Units
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK
Frequency for the PSCLK input
1
167
1
167
MHz
)
Input Pulse Requirements
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period
40%
60%
40%
60%
-
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Phase Shifting Range
MAX_STEPS(2)
Description
Phase Shift Amount
Units
Maximum allowed number of
[INTEGER(10 • (TCLKIN – 3 ns))]
[INTEGER(15 • (TCLKIN – 3 ns))]
steps
CLKIN < 60
MHz
DCM_DELAY_STEP steps for a
given CLKIN clock period, where
T = CLKIN clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
CLKIN ≥ 60
MHz
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
[MAX_STEPS •
ns
ns
DCM_DELAY_STEP_MIN]
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
[MAX_STEPS •
DCM_DELAY_STEP_MAX]
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 40.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 37.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
51
DC and Switching Characteristics
Miscellaneous DCM Timing
Table 42: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
CLKIN
cycles
–
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
seconds
seconds
minutes
minutes
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA configuration
successfully completed (DONE pin goes High) and clocks
applied to DCM DLL
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex®-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
DNA Port Timing
Table 43: DNA_PORT Interface Timing
Symbol
TDNASSU
TDNASH
Description
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
Setup time on READ before the rising edge of CLK
Hold time on READ after the rising edge of CLK
Clock-to-output delay on DOUT after rising edge of CLK
CLK frequency
Min
1.0
0.5
1.0
0.5
5.0
0
Max
Units
ns
–
–
ns
TDNADSU
TDNADH
TDNARSU
TDNARH
–
–
ns
ns
10,000
–
ns
ns
TDNADCKO
TDNACLKF
TDNACLKH
TDNACLKL
0.5
0
1.5
100
∞
ns
MHz
ns
CLK High time
1.0
1.0
CLK Low time
∞
ns
Notes:
1. The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 µs.
2. The numbers in this table are based on the operating conditions set forth in Table 8.
52
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Suspend Mode Timing
Entering Suspend Mode
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
SUSPEND Input
AWAKE Output
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
tAWAKE_GWE
tSUSPEND_GWE
Flip-Flops, Block RAM,
Distributed RAM
Write Protected
tAWAKE_GTS
tSUSPEND_GTS
FPGA Outputs
Defined by SUSPEND constraint
tSUSPEND_DISABLE tSUSPEND_ENABLE
FPGA Inputs,
Interconnect
Blocked
DS610-3_08_061207
Figure 10: Suspend Mode Timing
Table 44: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
–
+160
–
7
+300
10
–
+600
–
ns
ns
ns
ns
ns
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–
<5
–
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
–
340
–
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not
include DCM lock time.
–
–
–
–
–
–
4 to 108
–
–
–
–
–
–
µs
µs
ns
µs
ns
µs
TSUSPEND_ENABLE
TAWAKE_GWE1
TAWAKE_GWE512
TAWAKE_GTS1
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
3.7 to 109
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
67
14
57
14
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
Notes:
1. These parameters based on characterization.
2. For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
53
DC and Switching Characteristics
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
1.2V
V
CCINT
1.0V
2.0V
2.0V
(Supply)
2.5V
or
V
CCAUX
(Supply)
3.3V
V
Bank 2
(Supply)
2.5V
or
CCO
3.3V
TPOR
PROG_B
(Input)
TPL
TPROG
INIT_B
(Open-Drain)
TICCK
CCLK
(Output)
DS529-3_01_052708
Notes:
1. The V
, V
, and V
supplies can be applied in any order.
CCO
CCINT CCAUX
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 11: Waveforms for Power-On and the Beginning of Configuration
Table 45: Power-On Timing and the Beginning of Configuration
All Speed Grades
Symbol
Description
Device
Min
Max
Units
(2)
TPOR
The time from the application of VCCINT, VCCAUX, and VCCO All
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
–
18
ms
TPROG
The width of the low-going pulse on the PROG_B pin
All
0.5
–
-
0.5
0.5
1
µs
ms
ms
ms
ms
ms
ns
(2)
TPL
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
All
–
–
–
2
–
2
TINIT
Minimum Low pulse width on INIT_B output
250
0.5
–
(3)
TICCK
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
4
µs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all V
, V
,
CCINT CCO
and V
lines.
CCAUX
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the Master Serial, SPI, and BPI modes.
4. For details on configuration, see UG332 Spartan-3 Generation Configuration User Guide.
54
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Configuration Clock (CCLK) Characteristics
Table 46: Master Mode CCLK Output Period by ConfigRate Opti0on Setting
ConfigRate
Temperature
Range
Symbol
TCCLK1
Description
Setting
Minimum
1,254
1,180
413
390
207
195
178
168
156
147
123
116
103
97
Maximum
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK clock period by
ConfigRate setting
Commercial
Industrial
1
2,500
(power-on value)
Commercial
Industrial
TCCLK3
3
833
417
357
313
250
208
192
147
114
100
93
Commercial
Industrial
TCCLK6
6 (default)
Commercial
Industrial
TCCLK7
7
8
Commercial
Industrial
TCCLK8
Commercial
Industrial
TCCLK10
TCCLK12
TCCLK13
TCCLK17
TCCLK22
TCCLK25
TCCLK27
TCCLK33
TCCLK44
TCCLK50
10
12
13
17
22
25
27
33
44
50
100
Commercial
Industrial
Commercial
Industrial
93
88
Commercial
Industrial
72
68
Commercial
Industrial
54
51
Commercial
Industrial
47
45
Commercial
Industrial
44
42
Commercial
Industrial
36
76
34
Commercial
Industrial
26
57
25
Commercial
Industrial
22
50
21
Commercial
Industrial
11.2
10.6
TCCLK100
25
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
55
DC and Switching Characteristics
Table 47: Master Mode CCLK Output Frequency by ConfigRate Option Setting
ConfigRate
Temperature
Range
Symbol
FCCLK1
Description
Setting
Minimum
Maximum
0.797
0.847
2.42
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Equivalent CCLK clock frequency
by ConfigRate setting
Commercial
Industrial
1
0.400
(power-on value)
Commercial
Industrial
FCCLK3
3
1.20
2.40
2.57
Commercial
Industrial
4.83
6
FCCLK6
(default)
5.13
Commercial
Industrial
5.61
FCCLK7
7
8
2.80
5.96
Commercial
Industrial
6.41
FCCLK8
3.20
6.81
Commercial
Industrial
8.12
FCCLK10
FCCLK12
FCCLK13
FCCLK17
FCCLK22
FCCLK25
FCCLK27
FCCLK33
FCCLK44
FCCLK50
FCCLK100
10
12
13
17
22
25
27
33
44
50
100
4.00
8.63
Commercial
Industrial
9.70
4.80
10.31
10.69
11.37
13.74
14.61
18.44
19.61
20.90
22.23
22.39
23.81
27.48
29.23
37.60
40.00
44.80
47.66
88.68
94.34
Commercial
Industrial
5.20
Commercial
Industrial
6.80
Commercial
Industrial
8.80
Commercial
Industrial
10.00
10.80
13.20
17.60
20.00
40.00
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Table 48: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting
12 13 17 22
Symbol
Description
1
3
6
7
8
10
25
27
33
44
50
100 Units
Master Mode Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3
ns
ns
T
T
CCLK
MCCL,
MCCH
Minimum Low
and High Time
Industrial
560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0
Table 49: Slave Mode CCLK Input Low and High Time
Symbol
Description
Min
Max
Units
ns
TSCCL,
TSCCH
CCLK Low and High time
5
∞
56
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Master Serial and Slave Serial Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input/Output)
TDCC
1/FCCSER
TCCD
DIN
(Input)
Bit n+1
TCCO
Bit n
Bit 0
Bit 1
DOUT
(Output)
Bit n-63
Bit n-64
DS312-3_05_103105
Figure 12: Waveforms for Master Serial and Slave Serial Configuration
Table 50: Timing for the Master Serial and Slave Serial Configuration Modes
All Speed Grades
Slave/
Master
Symbol
Description
Min
Max
Units
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Both
Both
1.5
10
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
7
–
–
ns
ns
Hold Times
TCCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Master
Slave
0
1.0
Clock Timing
TCCH
High pulse width at the CCLK input pin
Master
Slave
Master
Slave
Slave
See Table 48
See Table 49
See Table 48
See Table 49
100
TCCL
Low pulse width at the CCLK input pin
FCCSER
Frequency of the clock signal at the
CCLK input pin
No bitstream compression
With bitstream compression
0
0
MHz
MHz
100
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
57
DC and Switching Characteristics
Slave Parallel Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CSI_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input)
1/FCCPAR
TSMDCC
TSMCCD
D0 - D7
(Inputs)
Byte 0
Byte 1
Byte n
Byte n+1
DS529-3_02_051607
Notes:
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332 Chapter 7 section “Non-Continuous SelectMAP Data
Loading” for more details.
Figure 13: Waveforms for Slave Parallel Configuration
Table 51: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Min
Max
Units
Setup Times
(2)
TSMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
7
7
–
–
–
ns
ns
ns
TSMCSCC
TSMCCW
15
Hold Times
TSMCCD
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
1.0
0
–
–
–
ns
ns
ns
TSMCCCS
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
0
Clock Timing
TCCH
The High pulse width at the CCLK input pin
5
5
0
0
–
–
ns
ns
TCCL
The Low pulse width at the CCLK input pin
FCCPAR
Frequency of the clock signal No bitstream compression
80
80
MHz
MHz
at the CCLK input pin
With bitstream compression
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
58
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Serial Peripheral Interface (SPI) Configuration Timing
PROG_B
(Input)
PUDC_B
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
(Input)
VS[2:0]
(Input)
<1:1:1>
<0:0:1>
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
M[2:0]
(Input)
TMINIT
TINITM
INIT_B
(Open-Drain)
New ConfigRate active
TCCLK
TMCCH
T
n
MCCL
n
TMCCL1 TMCCH1
T
TCCLK1
CCLK1
n
CCLK
TV
DIN
Data
Data
TDCC
Data
Data
(Input)
TCSS
TCCD
CSO_B
MOSI
TCCO
Command Command
(msb) (msb-1)
TDSU
TDH
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
DS529-3_06_102506
Shaded values indicate specifications on attached SPI Flash PROM.
Figure 14: Waveforms for Serial Peripheral Interface (SPI) Configuration
Table 52: Timing for Serial Peripheral Interface (SPI) Configuration Mode
Symbol Description
TCCLK1
TCCLKn
TMINIT
Minimum
Maximum
See Table 46
See Table 46
–
Units
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate bitstream option setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
50
0
ns
ns
TINITM
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
–
TCCO
TDCC
TCCD
MOSI output valid delay after CCLK falling clock edge
See Table 50
See Table 50
See Table 50
Setup time on the DIN data input before CCLK rising clock edge
Hold time on the DIN data input after CCLK rising clock edge
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
59
DC and Switching Characteristics
Table 53: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol
TCCS
Description
SPI serial Flash PROM chip-select time
Requirement
Units
ns
TCCS ≤ TMCCL1 – TCCO
TDSU
TDH
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
ns
ns
TDSU ≤ TMCCL1 – TCCO
TDH ≤ TMCCH1
TV ≤ TMCCLn – TDCC
1
TV
ns
fC or fR
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
MHz
--------------------------------
≥
fC
TCCLKn(min)
Notes:
1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
60
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
PROG_B
(Input)
PUDC_B
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
M[2:0]
(Input)
<0:1:0>
TMINIT
TINITM
INIT_B
Open-Drain)
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
LDC[2:0]
HDC
CSO_B
New ConfigRate active
TCCLK1
TCCLKn
TINITADDR
TCCLK1
CCLK
TCCO
000_0000
Byte 0
Address
Address Address
TCCD
A[25:0]
000_0001
Byte 1
T
AVQV
TDCC
Data
D[7:0]
(Input)
Data
Data
Data
Shaded values indicate specifications on attached parallel NOR Flash PROM.
DS529-3_05_021009
Figure 15: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
Symbol
TCCLK1
TCCLKn
TMINIT
Description
Minimum
Maximum
Units
Initial CCLK clock period
See Table 46
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
See Table 46
50
0
–
–
5
ns
ns
TINITM
TINITADDR
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
5
TCCLK1
cycles
TCCO
TDCC
TCCD
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
See Table 50
See TSMDCC in Table 51
–
0
ns
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
61
DC and Switching Characteristics
Table 55: Configuration Timing Requirements for Attached Parallel NOR BPI Flash
Symbol
TCE
(tELQV
TOE
(tGLQV
TACC
(tAVQV
TBYTE
(tFLQV, FHQV
Notes:
Description
Requirement
Units
Parallel NOR Flash PROM chip-select time
ns
TCE ≤ TINITADDR
)
Parallel NOR Flash PROM output-enable time
Parallel NOR Flash PROM read access time
For x8/x16 PROMs only: BYTE# to output valid time(3)
ns
ns
ns
TOE ≤ TINITADDR
TACC ≤ 50%TCCLKn(min) – TCCO – TDCC – PCB
TBYTE ≤ TINITADDR
)
)
t
)
1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
2. Subtract additional printed circuit board routing delay as required by the application.
3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
62
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
DC and Switching Characteristics
IEEE 1149.1/1532 JTAG Test Access Port Timing
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_020709
Figure 16: JTAG Waveforms
Table 56: Timing for the JTAG Test Access Port
All Speed
Grades
Symbol
Description
Min
Max
11.0
–
Units
ns
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
1.0
Setup Times
TTDITCK The time from the setup of data at the All devices and functions except those shown below
TDI pin to the rising transition at the
7.0
ns
Boundary scan commands (INTEST, EXTEST,
SAMPLE) on XC3S700A and XC3S1400A FPGAs
11.0
TCK pin
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
7.0
–
–
ns
ns
Hold Times
TTCKTDI The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below
0
Configuration commands (CFG_IN, ISC_PROGRAM)
2.0
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
0
–
ns
Clock Timing
TCCH
TCCL
The High pulse width at the TCK pin All functions except ISC_DNA command
The Low pulse width at the TCK pin
5
5
–
–
ns
ns
TCCHDNA The High pulse width at the TCK pin During ISC_DNA command
TCCLDNA The Low pulse width at the TCK pin
10
10
0
10,000
10,000
33
ns
ns
FTCK
Frequency of the TCK signal
All operations on XC3S50A, XC3S200A, and
XC3S400A FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
MHz
All operations on XC3S700A and XC3S1400A FPGAs,
except for BYPASS or HIGHZ instructions
20
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For details on JTAG see Chapter 9 “JTAG Configuration Mode and Boundary-Scan” in UG332 Spartan-3 Generation Configuration User
Guide.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
63
DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/05/06
02/02/07
Initial release.
1.1
Promoted to Preliminary status. Moved Table 15 to under "DC Electrical Characteristics" section. Updated all
timing specifications for the v1.32 speed files. Added recommended Simultaneous Switching Output (SSO)
limits in Table 29. Set a 10 µs maximum pulse width for the DNA_PORT READ signal and the JTAG clock
input during the ISC_DNA command, affecting both Table 43 and Table 56. Described "External Termination
Requirements for Differential I/O." Added separate DIN hold time for Slave mode in Table 50. Corrected
wording in Table 52 and Table 54; no specifications affected.
03/16/07
1.2
Updated all AC timing specifications to the v1.34 speeds file. Promoted the XC3S700A and XC3S1400A
FPGAs offered in the -4 speed grade to Production status, as shown in Table 16. Added Note 2 to Table 39
regarding the extra logic (one LUT) automatically added by ISE 9.1i and later software revisions for any DCM
application that leverages the Digital Frequency Synthesizer (DFS). Separated some JTAG specifications by
array size or function, as shown in Table 56. Updated quiescent current limits in Table 10.
04/23/07
05/08/07
1.3
1.4
Updated all AC timing specifications to the v1.35 speeds file. Promoted all devices except the XC3S400A to
Production status, as shown in Table 16.
Updated XC3S400A to Production and v1.36 speeds file. Added banking rules and other explanatory
footnotes to Table 12 and Table 13. Corrected DIFF_SSTL3_II VOL Max in Table 14. Improved XC3S400A
Pin-to-Pin Clock-to-Output times in Table 18. Updated XC3S400A Pin-to-Pin Setup Times in Table 19.
Updated TIOICKPD for -5 in Table 20. Added SSO numbers to Table 28 and Table 29. Removed invalid
Embedded Multiplier Hold Times in Table 34. Improved CLKOUT_FREQ_CLK90 in Table 37. Improved
TTDITCK and FTCK performance for XC3S400A in Table 56.
07/10/07
04/15/08
1.5
1.6
Added DIFF_HSTL_I and DIFF_HSTL_III to Table 13, Table 14, Table 27, and Table 29. Updated TMDS DC
characteristics in Table 14. Updated for speed file v1.37 in ISE 9.2.01i as shown in Table 17. Updated
pin-to-pin setup and hold times in Table 19. Updated TMDS output adjustment in Table 26. Updated I/O Test
Method values in Table 27. Added BLVDS SSO numbers inTable 29. For Multiplier block, updated setup times
and added hold times to Table 34. Updated block RAM clock width in Table 35. Updated
CLKOUT_PER_JITT_2X and CLKOUT_PER_JITT_DV2 in Table 37. Added CCLK specifications for
Commercial in Table 46 through Table 48.
Added VIN to Recommended Operating Conditions in Table 8 and added reference to XAPP459, “Eliminating
I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical
ICCINTQ and ICCAUXQ quiescent current values by 12%-58% in Table 10. Increased VIL max to 0.4V for
LVCMOS12/15/18 and improved VIH min to 0.7V for LVCMOS12 in Table 11. Changed VOL max to 0.4V and
VOH min to VCCO-0.4V for LVCMOS15/18 in Table 12. Noted latest speed file v1.39 in ISE 10.1 software in
Table 16. Added new packages to SSO limits in Table 28 and Table 29. Improved SSTL18_II SSO limit for
FG packages in Table 29. Improved FBUFG for -4 to 334 MHz in Table 33. Added references to 375 MHz
performance via SCD 4103 in Table 33,Table 38, Table 39, and Table 40. Restored Units column to Table 44.
Updated CCLK output maximum period in Table 46 to match minimum frequency in Table 47. Corrected BPI
active clock edge in Figure 15 and Table 54.
05/28/08
03/06/09
1.7
1.8
Improved VCCAUXT and VCCO2T POR minimum in Table 5 and updated VCCO POR levels in Figure 11.
Clarified recommended VIN in Table 8. Added reference to VCCAUX in "Simultaneously Switching Output
Guidelines". Added reference to Sample Window in Table 21. Removed DNA_RETENTION limit of 10 years
in Table 15 since number of Read cycles is the only unique limit. Added references to UG332.
Changed typical quiescent current temperature from ambient to junction. Updated BPI configuration
waveforms in Figure 15 and updated Table 55. Updated selected I/O standard DC characteristics. Added
TIOPI and TIOPID in Table 22.
Removed references to SCD 4103.
08/19/10
2.0
Added IIK to Table 4. Updated VIN in Table 8 and footnoted IL in Table 9 to note potential leakage between
pins of a differential pair. Clarified LVPECL notes to Table 13. Corrected symbols for TSUSPEND_GTS and
TSUSPEND_GWE in Table 44.
64
www.xilinx.com
DS529-3 (v2.0) August 19, 2010
132
Spartan-3A FPGA Family:
Pinout Descriptions
0
DS529-4 (v2.0) August 19, 2010
Product Specification
Introduction
This section describes how the various pins on a
Spartan®-3A FPGA connect within the supported
Except for the thermal characteristics, all information for the
standard package applies equally to the Pb-free package.
component packages, and provides device-specific thermal
characteristics. For general information on the pin functions
and the package characteristics, see the Packaging section
of UG331: Spartan-3 Generation FPGA User Guide.
Pin Types
Most pins on a Spartan-3A FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3A FPGA packages, as
outlined in Table 57. In the package footprint drawings that
follow, the individual pins are color-coded according to pin
type as in the table.
•
UG331: Spartan-3 Generation FPGA User Guide
www.xilinx.com/support/documentation
/user_guides/ug331.pdf
Spartan-3A FPGAs are available in both standard and
Pb-free, RoHS versions of each package, with the Pb-free
version adding a “G” to the middle of the package code.
Table 57: Types of Pins on Spartan-3A FPGAs
Type / Color
Description
Pin Name(s) in Type
Code
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form
differential I/Os.
IO_#
IO_Lxxy_#
I/O
Unrestricted, general-purpose input-only pin. This pin does not have an output structure, IP_#
INPUT
DUAL
differential termination resistor, or PCI clamp diode.
IP_Lxxy_#
Dual-purpose pin used in some configuration modes during the configuration process and M[2:0]
then usually available as a user I/O after configuration. If the pin is not used during
configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation
Configuration User Guide for additional information on these signals.
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other
IP/VREF_#
VREF pins in the same bank, provides a reference voltage input for certain I/O standards. IP_Lxxy_#/VREF_#
VREF
CLK
If used for a reference voltage within a bank, all VREF pins within the bank must be
connected.
IO/VREF_#
IO_Lxxy_#/VREF_#
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 IO_Lxxy_#/GCLK[15:0],
global clock inputs that optionally clock the entire device. The exceptions are the TQ144 IO_Lxxy_#/LHCLK[7:0],
and the XC3S50A in the FT256 package). The RHCLK inputs optionally clock the right half IO_Lxxy_#/RHCLK[7:0]
of the device. The LHCLK inputs optionally clock the left half of the device. See the Using
Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for
additional information on these signals.
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every
package has two dedicated configuration pins. These pins are powered by VCCAUX. See
the UG332: Spartan-3 Generation Configuration User Guide for additional information on
the DONE and PROG_B signals.
DONE, PROG_B
CONFIG
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
65
Pinout Descriptions
Table 57: Types of Pins on Spartan-3A FPGAs(Continued)
Type / Color
Description
Code
Pin Name(s) in Type
Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated
SUSPEND, AWAKE
PWR
MGMT
pin and is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is
enabled in the application, AWAKE is available as a user-I/O pin.
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has
four dedicated JTAG pins. These pins are powered by VCCAUX.
TDI, TMS, TCK, TDO
JTAG
Dedicated ground pin. The number of GND pins depends on the package used. All must GND
be connected.
GND
VCCAUX
VCCINT
VCCO
N.C.
Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the
package used. All must be connected. VCCAUX can be either 2.5V or 3.3V. Set on board
and using CONFIG VCCAUX constraint.
VCCAUX
Dedicated internal core logic power supply pin. The number of VCCINT pins depends on VCCINT
the package used. All must be connected to +1.2V.
Along with all the other VCCO pins in the same bank, this pin supplies power to the output VCCO_#
buffers within the I/O bank and sets the input threshold voltage for some I/O standards. All
must be connected.
This package pin is not connected in this specific device/package combination but may be N.C.
connected in larger devices in the same package.
Notes:
1. # = I/O bank number, an integer between 0 and 3.
Package Pins by Type
Each package has three separate voltage supply
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 59. The table shows the
maximum number of single-ended I/O pins available,
assuming that all I/O-, INPUT-, DUAL-, VREF-, and
CLK-type pins are used as general-purpose I/O. AWAKE is
counted here as a dual-purpose I/O pin. Likewise, the table
shows the maximum number of differential pin-pairs
available on the package. Finally, the table shows how the
total maximum user-I/Os are distributed by pin type,
including the number of unconnected—N.C.—pins on the
device.
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 58.
Table 58: Power and Ground Supply Pins by Package
Package
VCCINT VCCAUX VCCO GND
VQ100
TQ144
4
4
3
4
6
13
13
28
50
32
43
53
77
8
FT256 (50A/200A/400A)
FT256 (700A/1400A)
FG320
6
4
16
13
16
22
24
36
15
6
10
8
Not all I/O standards are supported on all I/O banks. The left
and right banks (I/O banks 1 and 3) support higher output
drive current than the top and bottom banks (I/O banks 0
and 2). Similarly, true differential output standards, such as
LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only
supported in the top or bottom banks (I/O banks 0 and 2).
Inputs are unrestricted. For more details, see the chapter
“Using I/O Resources” in UG331.
FG400
9
8
FG484
15
23
10
14
FG676
66
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
.
Table 59: Maximum User I/O by Package
Maximum
All Possible I/Os by Type
Maximum
Input-
Only
Maximum
Differential
Pairs
User I/Os
and
Device
Package
I/O
INPUT
DUAL
VREF
CLK
N.C.
Input-Only
XC3S50A
68
6
60
60
17
17
2
20
20
26
26
52
52
52
52
52
52
52
52
52
52
52
6
23
23
30
30
32
32
30
30
32
32
32
32
32
32
32
0
0
VQ100
TQ144
XC3S200A
XC3S50A
68
6
2
6
108
144
195
195
161
161
248
251
311
311
372
375
502
7
50
42
2
8
0
XC3S50A
32
35
35
13
13
56
59
63
63
84
87
94
64
53
20
21
21
2
15
21
21
18
18
23
24
26
26
33
34
38
51
0
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S200A
XC3S400A
XC3S400A
XC3S700A
XC3S700A
XC3S1400A
XC3S1400A
90
69
FT256
90
69
0
60
59
0
60
59
2
0
112
112
142
142
165
165
227
101
101
155
155
194
195
313
40
42
46
46
61
62
67
3
FG320
FG400
0
0
0
3
FG484
FG676
0
17
Notes:
1. Some VREFs are on INPUT pins. See pinout tables for details.
Electronic versions of the package pinout tables and foot-
prints are available for download from the Xilinx website.
Using a spreadsheet program, the data can be sorted and
reformatted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
http://www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
67
Pinout Descriptions
Package Overview
Table 60 shows the six low-cost, space-saving production package styles for the Spartan-3A family.
Table 60: Spartan-3A Family Package Options
(1)
Maximum Lead Pitch
Body Area
(mm)
Height
(mm)
Mass
(g)
Package
Leads
Type
I/O
(mm)
0.5
0.5
1.0
1.0
1.0
1.0
1.0
VQ100 / VQG100
TQ144 / TQG144
FT256 / FTG256
FG320 / FGG320
FG400 / FGG400
FG484 / FGG484
FG676 / FGG676
100
144
256
320
400
484
676
Very Thin Quad Flat Pack (VQFP)
Thin Quad Flat Pack (TQFP)
68
14 x 14
20 x 20
17 x 17
19 x 19
21 x 21
23 x 23
27 x 27
1.20
1.60
1.55
2.00
2.43
2.60
2.60
0.6
1.4
0.9
1.4
2.2
2.2
3.4
108
195
251
311
375
502
Fine-pitch Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Notes:
1. Package mass is ±10%.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For example,
the standard “CS484” package becomes “CSG484” when
ordered as the Pb-free option. The mechanical dimensions
of the standard and Pb-free packages are similar, as shown
in the mechanical drawings provided in Table 61.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table 61.
Material Declaration Data Sheets (MDDS) are also available
on the Xilinx web site for each package.
For additional package information, see UG112: Device
Package User Guide.
Table 61: Xilinx Package Documentation
Package
VQ100
Drawing
MDDS
Package Drawing
PK173_VQ100
PK130_VQG100
PK169_TQ144
PK126_TQG144
PK158_FT256
PK115_FTG256
PK152_FG320
PK106_FGG320
PK182_FG400
PK108_FGG400
PK183_FG484
PK110_FGG484
PK155_FG676
PK111_FGG676
VQG100
TQ144
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
TQG144
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
FG676
FGG676
68
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Package Thermal Characteristics
The power dissipated by an FPGA application has
The junction-to-case thermal resistance (θJC) indicates the
difference between the temperature measured on the
package body (case) and the die junction temperature per
watt of power consumption. The junction-to-board (θJB)
value similarly reports the difference between the board and
junction temperature. The junction-to-ambient (θJA) value
reports the temperature difference between the ambient
environment and the junction temperature. The θJA value is
reported at different air velocities, measured in linear feet
per minute (LFM). The “Still Air (0 LFM)” column shows the
implications on package selection and system design. The
power consumed by a Spartan-3A FPGA is reported using
either the XPower Power Estimator or the XPower Analyzer
calculator integrated in the Xilinx® ISE® development
software. Table 62 provides the thermal characteristics for
the various Spartan-3A FPGA package offerings. This
information is also available using the Thermal Query tool
on xilinx.com (www.xilinx.com/cgi-bin/thermal/thermal.pl).
θ
JA value in a system without a fan. The thermal resistance
drops with increasing air flow.
Table 62: Spartan-3A Package Thermal Characteristics
Junction-to-Ambient (θ
)
JA
at Different Air Flows
Junction-to-Case
(θ
Junction-to-
Still Air
(0 LFM)
Package
Device
XC3S50A
XC3S200A
)
Board (θ
)
JB
250 LFM
40.4
500 LFM
37.6
750 LFM
36.6
Units
°C/Watt
°C/Watt
JC
12.9
10.9
30.1
48.5
42.9
VQ100
VQG100
25.7
35.7
33.2
32.4
TQ144
TQG144
XC3S50A
16.5
32.0
42.4
36.3
35.8
34.9
°C/Watt
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
XC3S200A
XC3S400A
XC3S400A
XC3S700A
XC3S700A
XC3S1400A
16.0
10.3
8.4
33.5
23.8
19.3
18.6
14.1
18.5
15.4
15.5
13.0
12.8
9.9
42.3
32.7
29.9
28.1
24.2
27.8
25.2
25.6
23.1
22.3
19.5
35.6
26.6
24.9
22.3
18.7
22.3
19.8
19.2
17.9
17.4
14.7
35.5
26.1
23.0
21.2
17.5
21.1
18.6
18.0
16.7
16.2
13.5
34.5
25.2
22.3
20.7
17.0
20.3
17.8
17.3
16.0
15.5
12.8
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
FT256
FTG256
7.8
5.4
11.7
9.9
FG320
FGG320
9.8
FG400
FGG400
8.2
7.9
FG484
FGG484
6.0
FG676
FGG676
XC3S1400A
5.8
9.4
17.8
13.5
12.4
11.8
°C/Watt
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
69
Pinout Descriptions
VQ100: 100-lead Very Thin Quad Flat Package
The XC3S50A and XC3S200 are available in the 100-lead
very thin quad flat package, VQ100.
Table 63: Spartan-3A VQ100 Pinout(Continued)
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
IO_L02P_1/RHCLK0
IO_L03N_1/TRDY1/RHCLK3
IO_L03P_1/RHCLK2
IO_L04N_1/RHCLK7
IO_L04P_1/IRDY1/RHCLK6
IO_L05N_1
P59
P62
P61
P65
P64
P71
P70
P73
P72
P68
P67
P46
P25
P23
P27
P24
CLK
CLK
CLK
CLK
CLK
IO
Table 63 lists all the package pins. They are sorted by bank
number and then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined
earlier.
The VQ100 does not support Suspend mode (SUSPEND
and AWAKE are not connected), the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode,
or daisy chain configuration (DOUT is not connected).
IO_L05P_1
IO
IO_L06N_1
IO
IO_L06P_1
IO
Table 63 also indicates that some differential I/O pairs have
different assignments between the XC3S50A and the
XC3S200A, highlighted in light blue. See "Footprint
Migration Differences," page 72 for additional information.
IP_1/VREF_1
VREF
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
VCCO_1
IO_2/MOSI/CSI_B
IO_L01N_2/M0
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L03N_2/VS1 (3S50A)
IO_L04P_2/VS1 (3S200A)
2
P30
DUAL
Pinout Table
2
2
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
P28
P31
DUAL
DUAL
Table 63: Spartan-3A VQ100 Pinout
Bank
0
Pin Name
IO_0/GCLK11
Pin
P90
P78
P77
P84
P83
P86
P85
P89
P88
P94
P93
P99
P98
P97
P82
P79
P96
P57
P56
P60
Type
CLK
IO
IO_L04P_2/VS2 (3S50A)
IO_L03N_2/VS2 (3S200A)
2
2
P29
P34
DUAL
DUAL
0
IO_L01N_0
IO_L05N_2/D7 (3S50A)
IO_L06P_2/D7 (3S200A)
0
IO_L01P_0/VREF_0
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L04N_0/GCLK9
IO_L04P_0/GCLK8
IO_L05N_0
VREF
CLK
CLK
CLK
CLK
CLK
CLK
IO
0
2
2
IO_L05P_2
P32
P35
IO
0
IO_L06N_2/D6
DUAL
0
IO_L06P_2 (3S50A)
IO_L05N_2 (3S200A)
2
P33
IO
0
2
2
2
2
2
2
2
2
IO_L07N_2/D4
P37
P36
P41
P40
P44
P43
P49
P48
DUAL
DUAL
CLK
0
IO_L07P_2/D5
0
IO_L08N_2/GCLK15
IO_L08P_2/GCLK14
IO_L09N_2/GCLK1
IO_L09P_2/GCLK0
IO_L10N_2/D3
0
CLK
0
IO_L05P_0
IO
CLK
0
IO_L06N_0/PUDC_B
IO_L06P_0/VREF_0
IP_0
DUAL
VREF
IP
CLK
0
DUAL
DUAL
0
IO_L10P_2/INIT_B
0
IP_0/VREF_0
VREF
VCCO
VCCO
IO
IO_L11N_2/D0/DIN/MISO
(3S50A)
IO_L12P_2/D0/DIN/MISO
(3S200A)
0
VCCO_0
2
P51
DUAL
0
VCCO_0
1
IO_L01N_1
2
2
IO_L11P_2/D2
P50
P53
DUAL
DUAL
1
IO_L01P_1
IO
IO_L12N_2/CCLK
1
IO_L02N_1/RHCLK1
CLK
70
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 63: Spartan-3A VQ100 Pinout(Continued)
Table 63: Spartan-3A VQ100 Pinout(Continued)
IO_L12P_2/D1 (3S50A)
IO_L11N_2/D1 (3S200A)
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P17
P38
P66
P81
VCCINT
VCCINT
VCCINT
VCCINT
2
P52
DUAL
2
2
IP_2/VREF_2
VCCO_2
P39
P26
P45
P4
VREF
VCCO
VCCO
IO
2
VCCO_2
3
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3/LHCLK1
IO_L03P_3/LHCLK0
IO_L04N_3/IRDY2/LHCLK3
IO_L04P_3/LHCLK2
IO_L05N_3/LHCLK7
IO_L05P_3/TRDY2/LHCLK6
IO_L06N_3
IO_L06P_3
IP_3
3
P3
IO
3
P6
IO
3
P5
IO
3
P10
P9
CLK
3
CLK
3
P13
P12
P16
P15
P20
P19
P21
P7
CLK
3
CLK
3
CLK
3
CLK
3
IO
3
IO
3
IP
3
IP_3/VREF_3
VCCO_3
VREF
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
VCCAUX
VCCAUX
VCCAUX
3
P11
P14
P18
P42
P47
P58
P63
P69
P74
P8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P80
P87
P91
P95
P54
P100
P76
P2
GND
GND
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
VCCAUX TDO
P75
P1
VCCAUX TMS
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
P22
P55
P92
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
71
Pinout Descriptions
User I/Os by Bank
Table 64 indicates how the 68 available user-I/O pins are
distributed between the four I/O banks on the VQ100
package.
Table 64: User I/Os Per Bank for the XC3S50A and XC3S200A in the VQ100 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
3
INPUT
DUAL
VREF
CLK
7
Top
0
1
2
3
15
13
26
14
68
1
0
0
1
2
1
0
3
1
1
1
6
Right
6
6
Bottom
Left
2
19
0
4
6
6
TOTAL
17
20
23
Footprint Migration Differences
The XC3S50A and XC3S200 have common VQ100 pinouts
except for some differences in alignment of differential I/O
pairs.
Differential I/O Alignment Differences
Some differential I/O pairs in the VQ100 on the XC3S50A
FPGA are aligned differently than the corresponding pairs
on the XC3S200A FPGAs, as shown in Table 65. All the
mismatched pairs are in I/O Bank 2. These differences are
indicated with the black diamond character () in the
footprint diagrams Figure 17 and Figure 18.
Table 65: Differential I/O Differences in VQ100
VQ100 Pin Bank
XC3S50A
IIO_L04P_2/VS2
IO_L03N_2/VS1
IO_L06P_2
XC3S200A
IO_L03N_2/VS2
IO_L04P_2/VS1
IO_L05N_2
P29
P30
P33
2
P34
IO_L05N_2/D7
IO_L06P_2/D7
IO_L11N_2/D0/DIN/ IO_L12P_2/D0/DIN/
P51
P52
MISO
MISO
IO_L12P_2/D1
IO_L11N_2/D1
72
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
VQ100 Footprint (XC3S50A)
Note pin 1 indicator in top-left corner and logo orientation.
TMS
TDI
1
2
3
4
5
6
7
8
9
75 TDO
74 GND
Bank 0
IO_L01P_3
IO_L01N_3
IO_L02P_3
73 IO_L06N_1
72 IO_L06P_1
71 IO_L05N_1
70 IO_L05P_1
IO_L02N_3
IP_3/VREF_3
69 GND
GND
68 IP_1/VREF_1
67 VCCO_1
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1 10
VCCO_3 11
66 VCCINT
65 IO_L04N_1/RHCLK7
64 IO_L04P_1/IRDY1/RHCLK6
63 GND
IO_L04P_3/LHCLK2 12
IO_L04N_3/IRDY2/LHCLK3 13
GND 14
62 IO_L03N_1/TRDY1/RHCLK3
61 IO_L03P_1/RHCLK2
60 IO_L02N_1/RHCLK1
59 IO_L02P_1/RHCLK0
58 GND
IO_L05P_3/TRDY2/LHCLK6 15
IO_L05N_3/LHCLK7 16
VCCINT 17
GND 18
IO_L06P_3 19
57 IO_L01N_1
IO_L06N_3 20
56 IO_L01P_1
IP_3 21
55 VCCAUX
VCCAUX 22
54 DONE
IO_L01P_2/M1 23
IO_L02P_2/M2 24
IO_L01N_2/M0 25
53 IO_L12N_2/CCLK
52 IO_L12P_2/D1(◆)
51 IO_L11N_2/D0/DIN/MISO (◆)
Bank 2
Figure 17: VQ100 Package Footprint - XC3S50A (Top View)
I/O: Unrestricted, general-purpose
DUAL: Configuration pins, then
VREF: User I/O or input voltage
17
20
23
6
6
user I/O
possible user I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
2
CONFIG: Dedicated configuration
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
2
0
4
4
3
pins
voltage (+1.2V)
N.C.: Not connected
VCCAUX: Auxiliary supply voltage
13
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
73
Pinout Descriptions
VQ100 Footprint (XC3S200A)
Note pin 1 indicator in top-left corner and logo orientation.
TMS
TDI
1
2
3
4
5
6
7
8
9
75 TDO
Bank 0
74 GND
IO_L01P_3
IO_L01N_3
IO_L02P_3
73 IO_L06N_1
72 IO_L06P_1
71 IO_L05N_1
70 IO_L05P_1
IO_L02N_3
IP_3/VREF_3
69 GND
GND
68 IP_1/VREF_1
67 VCCO_1
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1 10
VCCO_3 11
66 VCCINT
65 IO_L04N_1/RHCLK7
64 IO_L04P_1/IRDY1/RHCLK6
63 GND
IO_L04P_3/LHCLK2 12
IO_L04N_3/IRDY2/LHCLK3 13
GND 14
62 IO_L03N_1/TRDY1/RHCLK3
61 IO_L03P_1/RHCLK2
60 IO_L02N_1/RHCLK1
59 IO_L02P_1/RHCLK0
58 GND
IO_L05P_3/TRDY2/LHCLK6 15
IO_L05N_3/LHCLK7 16
VCCINT 17
GND 18
IO_L06P_3 19
57 IO_L01N_1
IO_L06N_3 20
56 IO_L01P_1
IP_3 21
55 VCCAUX
VCCAUX 22
54 DONE
IO_L01P_2/M1 23
IO_L02P_2/M2 24
IO_L01N_2/M0 25
53 IO_L12N_2/CCLK
52 IO_L11N_2/D1(◆)
51 IO_L12P_2/D0/DIN/MISO (◆)
Bank 2
200A
Figure 18: VQ100 Package Footprint - XC3S200A (Top View)
I/O: Unrestricted, general-purpose
DUAL: Configuration pins, then
VREF: User I/O or input voltage
17
20
23
6
6
user I/O
possible user I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
2
CONFIG: Dedicated configuration
JTAG: Dedicated JTAG port pins
GND: Ground
VCCINT: Internal core supply
2
0
4
4
3
pins
voltage (+1.2V)
N.C.: Not connected
VCCAUX: Auxiliary supply voltage
13
74
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
TQ144: 144-lead Thin Quad Flat Package
The XC3S50A is available in the 144-lead thin quad flat
package, TQ144.
Table 66: Spartan-3A TQ144 Pinout(Continued)
Pin Name
IP_0/VREF_0
Bank
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
Pin
P123
P119
P136
P79
P78
P76
P77
P75
P84
P82
P85
P83
P88
P87
P92
P90
P93
P91
P98
P96
P101
P99
P104
P102
P105
P103
P80
P97
P86
P95
P62
P38
P37
P41
P39
P44
P42
P45
P43
P48
Type
VREF
VCCO
VCCO
I/O
Table 66 lists all the package pins. They are sorted by bank
number and then by pin name. Pins that form a differential
I/O pair appear together in the table. The table also shows
the pin number for each pin and the pin type, as defined
earlier.
VCCO_0
VCCO_0
IO_1
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1
DUAL
DUAL
DUAL
DUAL
I/O
The XC3S50A does not support the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode.
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L03P_1
I/O
IO_L04N_1/RHCLK1
IO_L04P_1/RHCLK0
IO_L05N_1/TRDY1/RHCLK3
IO_L05P_1/RHCLK2
IO_L06N_1/RHCLK5
IO_L06P_1/RHCLK4
IO_L07N_1/RHCLK7
IO_L07P_1/IRDY1/RHCLK6
IO_L08N_1
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
Pinout Table
Table 66: Spartan-3A TQ144 Pinout
Bank
0
Pin Name
Pin
Type
I/O
IO_0
P142
P111
P110
P113
P112
P117
P115
P116
P114
P121
P120
P126
P124
P127
P125
P131
P129
P132
P130
P135
P134
P139
P138
P143
P141
P140
0
IO_L01N_0
I/O
0
IO_L01P_0
I/O
0
IO_L02N_0
I/O
0
IO_L02P_0/VREF_0
IO_L03N_0
VREF
I/O
IO_L08P_1
I/O
0
IO_L09N_1
I/O
0
IO_L03P_0
I/O
IO_L09P_1
I/O
0
IO_L04N_0
I/O
IO_L10N_1
I/O
0
IO_L04P_0
I/O
IO_L10P_1
I/O
0
IO_L05N_0
I/O
IO_L11N_1
I/O
0
IO_L05P_0
I/O
IO_L11P_1
I/O
0
IO_L06N_0/GCLK5
IO_L06P_0/GCLK4
IO_L07N_0/GCLK7
IO_L07P_0/GCLK6
IO_L08N_0/GCLK9
IO_L08P_0/GCLK8
IO_L09N_0/GCLK11
IO_L09P_0/GCLK10
IO_L10N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
IP_1/VREF_1
VREF
VREF
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
0
IP_1/VREF_1
0
VCCO_1
0
VCCO_1
0
IO_2/MOSI/CSI_B
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS1
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L04P_2/VS2
IO_L05N_2/D7
0
0
0
0
0
IO_L10P_0
I/O
0
IO_L11N_0
I/O
0
IO_L11P_0
I/O
0
IO_L12N_0/PUDC_B
IO_L12P_0/VREF_0
IP_0
DUAL
VREF
INPUT
0
0
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
75
Pinout Descriptions
Table 66: Spartan-3A TQ144 Pinout(Continued)
Table 66: Spartan-3A TQ144 Pinout(Continued)
Bank
Pin Name
IO_L05P_2
Pin
P46
P49
P47
P51
P50
P55
P54
P59
P57
P60
P58
P64
Type
I/O
Bank
3
Pin Name
IO_L10P_3
Pin
P27
P30
P28
P32
P31
P35
P33
P14
P23
P9
Type
I/O
2
2
2
2
2
2
2
2
2
2
2
2
IO_L06N_2/D6
DUAL
I/O
3
IO_L11N_3
IO_L11P_3
IO_L12N_3
IO_L12P_3
IP_L13N_3/VREF_3
IP_L13P_3
VCCO_3
VCCO_3
GND
I/O
IO_L06P_2
3
I/O
IO_L07N_2/D4
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
DUAL
3
I/O
IO_L07P_2/D5
3
I/O
IO_L08N_2/GCLK15
IO_L08P_2/GCLK14
IO_L09N_2/GCLK1
IO_L09P_2/GCLK0
IO_L10N_2/GCLK3
IO_L10P_2/GCLK2
IO_L11N_2/DOUT
3
VREF
INPUT
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P17
P26
P34
P56
P65
P81
P89
P100
P106
P118
P128
P137
GND
PWR
MGMT
GND
2
IO_L11P_2/AWAKE
P63
GND
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L12N_2/D3
IO_L12P_2/INIT_B
IO_L13N_2/D0/DIN/MISO
IO_L13P_2/D2
IO_L14N_2/CCLK
IO_L14P_2/D1
IP_2/VREF_2
P68
P67
P71
P69
P72
P70
P53
P40
P61
P6
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
VCCO
VCCO
I/O
GND
GND
GND
GND
GND
GND
GND
VCCO_2
GND
VCCO_2
PWR
MGMT
VCCAUX SUSPEND
P74
IO_L01N_3
IO_L01P_3
P4
I/O
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
P73
P144
P109
P2
CONFIG
CONFIG
JTAG
IO_L02N_3
P5
I/O
IO_L02P_3
P3
I/O
IO_L03N_3
P8
I/O
VCCAUX TDI
JTAG
IO_L03P_3
P7
I/O
VCCAUX TDO
P107
P1
JTAG
IO_L04N_3/VREF_3
IO_L04P_3
P11
P10
P13
P12
P16
P15
P20
P18
P21
P19
P25
P24
P29
VREF
I/O
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P36
P66
VCCAUX
VCCAUX
IO_L05N_3/LHCLK1
IO_L05P_3/LHCLK0
IO_L06N_3/IRDY2/LHCLK3
IO_L06P_3/LHCLK2
IO_L07N_3/LHCLK5
IO_L07P_3/LHCLK4
IO_L08N_3/LHCLK7
IO_L08P_3/TRDY2/LHCLK6
IO_L09N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
P108 VCCAUX
P133 VCCAUX
P22
P52
VCCINT
VCCINT
VCCINT
VCCINT
P94
P122
IO_L09P_3
I/O
IO_L10N_3
I/O
76
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
User I/Os by Bank
Table 67 indicates how the 108 available user-I/O pins are
distributed between the four I/O banks on the TQ144
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3S50A in the TQ144 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
14
11
2
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
27
25
1
0
0
1
2
1
4
3
2
1
2
8
Right
8
Bottom
Left
30
21
0
6
26
15
42
8
TOTAL
108
26
30
Footprint Migration Differences
The XC3S50A FPGA is the only Spartan-3A device offered
in the TQ144 package.
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
77
Pinout Descriptions
TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.
TMS
TDI
1
2
108 VCCAUX
107 TDO
Bank 0
IO_L02P_3
IO_L01P_3
IO_L02N_3
IO_L01N_3
IO_L03P_3
IO_L03N_3
GND
3
4
5
6
7
8
9
106 GND
105 IO_L11N_1
104 IO_L10N_1
103 IO_L11P_1
102 IO_L10P_1
101 IO_L09N_1
100 GND
IO_L04P_3 10
IO_L04N_3/VREF_3 11
IO_L05P_3/LHCLK0 12
IO_L05N_3/LHCLK1 13
VCCO_3 14
99 IO_L09P_1
98 IO_L08N_1
97 IP_1/VREF_1
96 IO_L08P_1
95 VCCO_1
IO_L06P_3/LHCLK2 15
IO_L06N_3/LHCLK3 16
GND 17
94 VCCINT
93 IO_L07N_1/RHCLK7
92 IO_L06N_1/RHCLK5
91 IO_L07P_1/RHCLK6
90 IO_L06P_1/RHCLK4
89 GND
IO_L07P_3/LHCLK4 18
IO_L08P_3/LHCLK6 19
IO_L07N_3/LHCLK5 20
IO_L08N_3/LHCLK7 21
VCCINT 22
88 IO_L05N_1/RHCLK3
87 IO_L05P_1/RHCLK2
86 VCCO_1
VCCO_3 23
IO_L09P_3 24
85 IO_L04N_1/RHCLK1
84 IO_L03N_1
IO_L09N_3 25
GND 26
83 IO_L04P_1/RHCLK0
82 IO_L03P_1
IO_L10P_3 27
IO_L11P_3 28
81 GND
IO_L10N_3 29
80 IP_1/VREF_1
79 IO_1
IO_L11N_3 30
IO_L12P_3 31
78 IO_L01N_1/LDC2
77 IO_L02N_1/LDC0
76 IO_L01P_1/HDC
75 IO_L02P_1/LDC1
IO_L12N_3 32
IP_L13P_3 33
GND 34
IP_L13N_3/VREF_3 35
VCCAUX 36
74
73
SUSPEND
Bank 2
DONE
DS529-4_10_031207
Figure 19: TQ144 Package Footprint (Top View)
I/O: Unrestricted, general-purpose
DUAL: Configuration pins, then
VREF: User I/O or input voltage
42
2
25
30
8
8
user I/O
possible user I/O
reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or global
buffer input
VCCO: Output voltage supply for
bank
CONFIG: Dedicated configuration
JTAG: Dedicated JTAG port pins
VCCINT: Internal core supply
2
0
4
4
4
pins
voltage (+1.2V)
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply voltage
13
SUSPEND: Dedicated SUSPEND
and dual-purpose AWAKE Power
Management pins
2
78
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FT256: 256-ball Fine-pitch, Thin Ball Grid Array
The 256-ball fine-pitch, thin ball grid array package, FT256,
Pinout Table
supports all five Spartan-3A FPGAs. The XC3S200A and
XC3S400A have identical footprints, and the XC3S700A
and XC3S1400A have identical footprints. The XC3S50A is
compatible with the XC3S200A/XC3S400A but has 51
unconnected balls. The XC3S200A/XC3S400A is similar to
the XC3S700A/XC3S1400A, but the XC3S700A/
XC3S1400A adds more power and ground pins and
therefore is not compatible.
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400)
XC3S200A
XC3S400A
FT256
Ball
Bank
XC3S50A
IO_L01N_0
Type
I/O
0
0
0
IO_L01N_0
C13
D13
B14
IO_L01P_0
IO_L02N_0
IO_L01P_0
IO_L02N_0
I/O
I/O
Table 68 lists all the package pins for the XC3S50A,
XC3S200A, and XC3S400A. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
IO_L02P_0/
VREF_0
IO_L02P_0/
VREF_0
0
B15
VREF
0
0
0
0
0
0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
N.C. (◆)
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
D11
C12
A13
A14
A12
B12
I/O
I/O
I/O
I/O
I/O
I/O
The highlighted rows indicate pinout differences between
the XC3S50A, the XC3S200A, and the XC3S400A FPGAs.
The XC3S50A has 51 unconnected balls, indicated as N.C.
(No Connection) in Table 68 and Figure 20 and with the
black diamond character () in Table 68. Figure 21
provides the common footprint for the XC3S200A and
XC3S400A.
IP_0
IO_L06N_0/
VREF_0
0
N.C. (◆)
E10
VREF
0
0
0
0
0
N.C. (◆)
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
D10
A11
C11
A10
B10
I/O
I/O
I/O
I/O
I/O
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
Table 68 also indicates that some differential I/O pairs have
different assignments between the XC3S50A and the
XC3S200A/XC3S400A, highlighted in light blue. See
"Footprint Migration Differences," page 99 for additional
information.
IO_L09N_0/
GCLK5
IO_L09N_0/
GCLK5
0
0
0
0
0
0
0
0
D9
C10
A9
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
All other balls have nearly identical functionality on all three
devices. Table 73 summarizes the XC3S50A FPGA footprint
migration differences for the FT256 package.
IO_L09P_0/
GCLK4
IO_L09P_0/
GCLK4
IO_L10N_0/
GCLK7
IO_L10N_0/
GCLK7
The XC3S50A does not support the address output pins for
the Byte-wide Peripheral Interface (BPI) configuration mode.
IO_L10P_0/
GCLK6
IO_L10P_0/
GCLK6
C9
D8
C8
B8
Table 69 lists all the package pins for the XC3S700A and
XC3S1400A. They are sorted by bank number and then by
pin name. Pins that form a differential I/O pair appear
together in the table. The table also shows the pin number
for each pin and the pin type, as defined earlier. Figure 22
provides the common footprint for the XC3S200A and
XC3S400A.
IO_L11N_0/
GCLK9
IO_L11N_0/
GCLK9
IO_L11P_0/
GCLK8
IO_L11P_0/
GCLK8
IO_L12N_0/
GCLK11
IO_L12N_0/
GCLK11
IO_L12P_0/
GCLK10
IO_L12P_0/
GCLK10
A8
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
0
0
N.C. (◆)
N.C. (◆)
IO_L13N_0
IO_L13P_0
C7
A7
I/O
I/O
IO_L14N_0/
VREF_0
0
N.C. (◆)
E7
VREF
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
0
0
0
0
0
0
N.C. (◆)
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
F8
B6
A6
C6
D7
C5
I/O
I/O
I/O
I/O
I/O
I/O
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
79
Pinout Descriptions
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued)
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued)
XC3S200A
XC3S400A
FT256
Ball
XC3S200A
XC3S400A
FT256
Ball
Bank
XC3S50A
IO_L17P_0
Type
I/O
Bank
XC3S50A
Type
IO_L12N_1/
IO_L12N_1/
TRDY1/RHCLK3 TRDY1/RHCLK3
0
0
0
0
0
IO_L17P_0
A5
B4
A4
B3
A3
1
J16
K16
H14
J14
RHCLK
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
I/O
IO_L12P_1/
RHCLK2
IO_L12P_1/
RHCLK2
1
1
1
1
1
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
I/O
IO_L14N_1/
RHCLK5
IO_L14N_1/
RHCLK5
I/O
IO_L14P_1/
RHCLK4
IO_L14P_1/
RHCLK4
IO_L20N_0/
PUDC_B
IO_L20N_0/
PUDC_B
0
0
D5
C4
DUAL
VREF
IO_L15N_1/
RHCLK7
IO_L15N_1/
RHCLK7
H16
H15
IO_L20P_0/
VREF_0
IO_L20P_0/
VREF_0
IO_L15P_1/
IRDY1/RHCLK6
IO_L15P_1/
IRDY1/RHCLK6
0
0
0
0
0
0
0
0
0
0
0
IP_0
IP_0
D6
D12
E6
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
IP_0
IP_0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N.C. (◆)
IO_L16N_1/A11
IO_L16P_1/A10
IO_L17N_1/A13
IO_L17P_1/A12
IO_L18N_1/A15
IO_L18P_1/A14
IO_L19N_1/A17
IO_L19P_1/A16
IO_L20N_1/A19
IO_L20P_1/A18
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
F16
G16
G14
H13
F15
E16
F14
G13
F13
E14
D15
D16
D14
E13
C15
C16
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
IP_0
IP_0
N.C. (◆)
IP_0
IP_0
F7
N.C. (◆)
IP_0
IP_0
F9
N.C. (◆)
IP_0
IP_0
F10
E9
N.C. (◆)
IP_0/VREF_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IP_0/VREF_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
N.C. (◆)
B5
VCCO
VCCO
VCCO
VCCO
N.C. (◆)
B9
N.C. (◆)
B13
E8
IO_L20N_1
IO_L20P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
IO_L01N_1/
LDC2
IO_L01N_1/
LDC2
1
1
1
1
N14
N13
P15
R15
DUAL
DUAL
DUAL
DUAL
IO_L01P_1/
HDC
IO_L01P_1/
HDC
IO_L02N_1/
LDC0
IO_L02N_1/
LDC0
IO_L02P_1/
LDC1
IO_L02P_1/
LDC1
IP_L04N_1/
VREF_1
IP_L04N_1/
VREF_1
1
1
IO_L03N_1
IO_L03P_1
IO_L03N_1/A1
IO_L03P_1/A0
N16
P16
DUAL
DUAL
1
K12
VREF
1
1
IP_L04P_1
IP_L04P_1
IP_L09N_1
K11
J11
INPUT
INPUT
IO_L05N_1/
VREF_1
1
N.C. (◆)
M14
VREF
N.C. (◆)
IP_L09P_1/
VREF_1
1
1
1
1
1
1
1
1
1
N.C. (◆)
N.C. (◆)
N.C. (◆)
N.C. (◆)
N.C. (◆)
N.C. (◆)
N.C. (◆)
IO_L10N_1
IO_L10P_1
IO_L05P_1
M13
K13
L13
M16
M15
L16
L14
J13
J12
I/O
1
N.C. (◆)
J10
VREF
IO_L06N_1/A3
IO_L06P_1/A2
IO_L07N_1/A5
IO_L07P_1/A4
IO_L08N_1/A7
IO_L08P_1/A6
IO_L10N_1/A9
IO_L10P_1/A8
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
1
1
1
IP_L13N_1
IP_L13P_1
IP_L21N_1
IP_L13N_1
IP_L13P_1
IP_L21N_1
H11
H10
G11
INPUT
INPUT
INPUT
IP_L21P_1/
VREF_1
IP_L21P_1/
VREF_1
1
1
1
G12
F11
F12
VREF
INPUT
VREF
IP_L25N_1
IP_L25N_1
IP_L25P_1/
VREF_1
IP_L25P_1/
VREF_1
1
1
1
1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
E15
H12
J15
VCCO
VCCO
VCCO
VCCO
IO_L11N_1/
RHCLK1
IO_L11N_1/
RHCLK1
1
1
K14
K15
RHCLK
RHCLK
IO_L11P_1/
RHCLK0
IO_L11P_1/
RHCLK0
N15
80
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued)
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued)
XC3S200A
XC3S400A
FT256
Ball
XC3S200A
FT256
Ball
Bank
XC3S50A
IO_L01N_2/M0
IO_L01P_2/M1
Type
DUAL
DUAL
Bank
XC3S50A
IO_L20P_2/D1
IO_L18P_2/D2
N.C. (◆)
XC3S400A
IO_L18N_2/D1
IO_L18P_2/D2
IO_L19N_2
Type
DUAL
DUAL
I/O
2
2
IO_L01N_2/M0
IO_L01P_2/M1
P4
N4
2
2
2
2
R13
T13
P13
N12
IO_L02N_2/
CSO_B
IO_L02N_2/
CSO_B
2
T2
DUAL
N.C. (◆)
IO_L19P_2
I/O
2
2
IO_L02P_2/M2
IO_L04P_2/VS2
IO_L02P_2/M2
IO_L03N_2/VS2
R2
T3
DUAL
DUAL
IO_L20N_2/
CCLK
IO_L20N_2/
CCLK
2
2
R14
T14
DUAL
DUAL
IO_L03P_2/
RDWR_B
IO_L03P_2/
RDWR_B
IO_L18N_2/D0/
DIN/MISO
IO_L20P_2/D0/
DIN/MISO
2
R3
DUAL
2
2
2
2
2
2
2
2
2
2
IO_L04N_2/VS0
IO_L03N_2/VS1
IO_L06P_2
IO_L04N_2/VS0
IO_L04P_2/VS1
IO_L05N_2
P5
N6
R5
T4
T6
T5
P6
N7
N8
P7
DUAL
DUAL
I/O
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
IP_2
IP_2
L7
L8
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VCCO
VCCO
VCCO
VCCO
I/O
IP_2
IP_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
L9
IO_L05P_2
IO_L05P_2
I/O
L10
M7
M8
M11
N5
M9
R4
R8
R12
C1
C2
D3
D4
E1
IO_L06N_2/D6
IO_L05N_2/D7
N.C. (◆)
IO_L06N_2/D6
IO_L06P_2/D7
IO_L07N_2
DUAL
DUAL
I/O
N.C. (◆)
IO_L07P_2
I/O
IO_L08N_2/D4
IO_L08P_2/D5
IO_L08N_2/D4
IO_L08P_2/D5
DUAL
DUAL
VCCO_2
VCCO_2
IO_L09N_2/
GCLK13
VCCO_2
VCCO_2
2
2
2
2
2
2
2
2
N.C. (◆)
N.C. (◆)
T7
R7
T8
P8
P9
N9
T9
R9
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VCCO_2
VCCO_2
IO_L09P_2/
GCLK12
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
N.C. (◆)
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L07N_3
IO_L07P_3
I/O
IO_L10N_2/
GCLK15
IO_L10N_2/
GCLK15
I/O
IO_L10P_2/
GCLK14
IO_L10P_2/
GCLK14
I/O
I/O
IO_L11N_2/
GCLK1
IO_L11N_2/
GCLK1
D1
E2
I/O
IO_L11P_2/
GCLK0
IO_L11P_2/
GCLK0
I/O
N.C. (◆)
E3
I/O
IO_L12N_2/
GCLK3
IO_L12N_2/
GCLK3
N.C. (◆)
G4
F3
I/O
IO_L12P_2/
GCLK2
IO_L12P_2/
GCLK2
N.C. (◆)
I/O
IO_L08N_3/
VREF_3
IO_L08N_3/
VREF_3
2
2
N.C. (◆)
N.C. (◆)
IO_L13N_2
IO_L13P_2
M10
N10
I/O
I/O
3
G1
VREF
3
3
3
3
3
IO_L08P_3
N.C. (◆)
N.C. (◆)
N.C. (◆)
N.C. (◆)
IO_L08P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
F1
H4
G3
H5
H6
I/O
I/O
I/O
I/O
I/O
IO_L14P_2/
MOSI/CSI_B
IO_L14N_2/
MOSI/CSI_B
2
2
2
P10
T10
R11
DUAL
I/O
IO_L14N_2
IO_L14P_2
IO_L15N_2/
DOUT
IO_L15N_2/
DOUT
DUAL
IO_L15P_2/
AWAKE
IO_L15P_2/
AWAKE
PWR
IO_L11N_3/
LHCLK1
IO_L11N_3/
LHCLK1
2
T11
3
3
3
3
H1
G2
J3
LHCLK
LHCLK
LHCLK
LHCLK
MGMT
2
2
2
IO_L16N_2
IO_L16P_2
IO_L16N_2
IO_L16P_2
N11
P11
P12
I/O
I/O
IO_L11P_3/
LHCLK0
IO_L11P_3/
LHCLK0
IO_L12N_3/
IRDY2/LHCLK3
IO_L12N_3/
IRDY2/LHCLK3
IO_L17N_2/D3
IO_L17N_2/D3
DUAL
IO_L17P_2/
INIT_B
IO_L17P_2/
INIT_B
IO_L12P_3/
LHCLK2
IO_L12P_3/
LHCLK2
2
T12
DUAL
H3
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
81
Pinout Descriptions
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued)
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued)
XC3S200A
XC3S400A
FT256
Ball
XC3S200A
XC3S400A
FT256
Ball
Bank
XC3S50A
Type
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XC3S50A
GND
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L14N_3/
LHCLK5
IO_L14N_3/
LHCLK5
GND
B11
C3
3
J1
J2
K1
LHCLK
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L14P_3/
LHCLK4
IO_L14P_3/
LHCLK4
3
3
LHCLK
LHCLK
C14
E5
IO_L15N_3/
LHCLK7
IO_L15N_3/
LHCLK7
E12
F2
IO_L15P_3/
TRDY2/LHCLK6
IO_L15P_3/
TRDY2/LHCLK6
3
3
3
K3
L2
L1
LHCLK
I/O
F6
N.C. (◆)
N.C. (◆)
IO_L16N_3
G8
IO_L16P_3/
VREF_3
VREF
G10
G15
H9
3
3
3
3
3
3
3
3
3
3
3
3
3
3
N.C. (◆)
IO_L17N_3
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
J6
J4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C. (◆)
N.C. (◆)
L3
J8
N.C. (◆)
K4
L4
K2
N.C. (◆)
K7
N.C. (◆)
M3
N1
M1
P1
N2
P2
R1
M4
N3
K9
IO_L20N_3
IO_L20P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
L11
L15
M5
M12
P3
P14
R6
R10
T1
IP_L04N_3/
VREF_3
IP_L04N_3/
VREF_3
3
3
3
F4
E4
G5
VREF
INPUT
VREF
T16
IP_L04P_3
IP_L04P_3
PWR
MGMT
IP_L06N_3/
VREF_3
VCCAUX SUSPEND
SUSPEND
R16
N.C. (◆)
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
DONE
CONFIG
CONFIG
JTAG
T15
A2
3
3
3
3
3
N.C. (◆)
IP_L06P_3
IP_L13N_3
IP_L13P_3
IP_L21N_3
IP_L21P_3
G6
J7
INPUT
INPUT
INPUT
INPUT
INPUT
PROG_B
TCK
IP_L13N_3
IP_L13P_3
IP_L21N_3
IP_L21P_3
A15
B1
H7
K6
K5
VCCAUX TDI
TDI
JTAG
VCCAUX TDO
TDO
JTAG
B16
B2
VCCAUX TMS
TMS
JTAG
IP_L25N_3/
VREF_3
IP_L25N_3/
VREF_3
3
L6
VREF
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
E11 VCCAUX
3
3
IP_L25P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
IP_L25P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
L5
D2
H2
J5
INPUT
VCCO
VCCO
VCCO
VCCO
GND
F5
L12
M6
G7
G9
H8
J9
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
3
3
3
M2
A1
A16
B7
GND
GND
GND
GND
GND
GND
GND
GND
GND
82
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 69: Spartan-3A FT256 Pinout (XC3S700A,
Table 68: Spartan-3A FT256 Pinout (XC3S50A,
XC3S200A, XC3S400) (Continued)
XC3S700A
XC3S1400A
FT256
Ball
Bank
Type
XC3S200A
XC3S400A
FT256
Ball
Bank
XC3S50A
Type
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L18N_0
B4
A4
I/O
VCCINT VCCINT
VCCINT VCCINT
VCCINT
VCCINT
K8
VCCINT
VCCINT
IO_L18P_0
I/O
K10
IO_L19N_0
B3
I/O
IO_L19P_0
A3
I/O
Table 69: Spartan-3A FT256 Pinout (XC3S700A, XC3S1400A)
IO_L20N_0/PUDC_B
IO_L20P_0/VREF_0
IP_0
D5
DUAL
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
XC3S700A
XC3S1400A
FT256
Ball
Bank
Type
C4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L01N_0
C13
D13
B14
B15
D12
C12
A13
A14
A12
B12
D10
D11
A11
C11
A10
B10
D9
I/O
I/O
E6
IO_L01P_0
VCCO_0
B13
B5
IO_L02N_0
I/O
VCCO_0
IO_L02P_0/VREF_0
IO_L03N_0
VREF
I/O
VCCO_0
B9
VCCO_0
E8
IO_L03P_0
I/O
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L06N_1/A3
IO_L06P_1/A2
IO_L07N_1/A5
IO_L07P_1/A4
IO_L08N_1/A7
IO_L08P_1/A6
IO_L10N_1/A9
IO_L10P_1/A8
IO_L11N_1/RHCLK1
IO_L11P_1/RHCLK0
IO_L12N_1/TRDY1/RHCLK3
IO_L12P_1/RHCLK2
IO_L15N_1/RHCLK7
IO_L15P_1/IRDY1/RHCLK6
IO_L16N_1/A11
IO_L16P_1/A10
IO_L17N_1/A13
IO_L17P_1/A12
IO_L18N_1/A15
IO_L18P_1/A14
IO_L19N_1/A17
IO_L19P_1/A16
IO_L20N_1/A19
N14
N13
P15
R15
N16
P16
K13
L13
M16
M15
L16
L14
J13
J12
K14
K15
J16
K16
H16
H15
F16
G16
G14
H13
F15
E16
F14
G13
F13
IO_L04N_0
I/O
IO_L04P_0
I/O
IO_L05N_0
I/O
IO_L05P_0
I/O
IO_L06N_0/VREF_0
IO_L06P_0
VREF
I/O
IO_L07N_0
I/O
IO_L07P_0
I/O
IO_L08N_0
I/O
IO_L08P_0
I/O
IO_L09N_0/GCLK5
IO_L09P_0/GCLK4
IO_L10N_0/GCLK7
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L11P_0/GCLK8
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
IO_L13N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
C10
A9
C9
D8
C8
B8
A8
C7
IO_L13P_0
A7
I/O
IO_L14N_0/VREF_0
IO_L14P_0
E7
VREF
I/O
E9
IO_L15N_0
B6
I/O
IO_L15P_0
A6
I/O
IO_L16N_0
C6
I/O
IO_L16P_0
D7
I/O
IO_L17N_0
C5
I/O
IO_L17P_0
A5
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
83
Pinout Descriptions
Table 69: Spartan-3A FT256 Pinout (XC3S700A,
Table 69: Spartan-3A FT256 Pinout (XC3S700A,
XC3S700A
XC3S1400A
FT256
Ball
XC3S700A
XC3S1400A
FT256
Ball
Bank
Type
Bank
Type
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L20P_1/A18
E14
D15
D16
D14
E13
C15
C16
H12
J14
M13
M14
E15
J15
N15
P4
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
VREF
VREF
VREF
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L16N_2
N11
P11
P12
T12
R13
T13
P13
N12
R14
T14
M11
M7
M9
N5
I/O
I/O
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
IP_1/VREF_1
IO_L16P_2
IO_L17N_2/D3
IO_L17P_2/INIT_B
IO_L18N_2/D1
IO_L18P_2/D2
IO_L19N_2
DUAL
DUAL
DUAL
DUAL
I/O
IO_L19P_2
I/O
IP_1/VREF_1
IO_L20N_2/CCLK
IO_L20P_2/D0/DIN/MISO
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
DUAL
DUAL
VREF
VREF
VREF
VREF
VREF
VCCO
VCCO
VCCO
I/O
IP_1/VREF_1
IP_1/VREF_1
VCCO_1
VCCO_1
VCCO_1
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS2
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L04P_2/VS1
IO_L05N_2
P6
N4
R12
R4
T2
VCCO_2
R2
VCCO_2
R8
T3
IO_L01N_3
C1
R3
IO_L01P_3
C2
I/O
P5
IO_L02N_3
D3
I/O
N6
IO_L02P_3
D4
I/O
R5
IO_L03N_3
E1
I/O
IO_L05P_2
T4
I/O
IO_L03P_3
D1
I/O
IO_L06N_2/D6
IO_L06P_2/D7
IO_L08N_2/D4
IO_L08P_2/D5
IO_L09N_2/GCLK13
IO_L09P_2/GCLK12
IO_L10N_2/GCLK15
IO_L10P_2/GCLK14
IO_L11N_2/GCLK1
IO_L11P_2/GCLK0
IO_L12N_2/GCLK3
IO_L12P_2/GCLK2
IO_L14N_2/MOSI/CSI_B
IO_L14P_2
T6
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
DUAL
I/O
IO_L04N_3
F4
I/O
T5
IO_L04P_3
E4
I/O
N8
IO_L05N_3
E2
I/O
P7
IO_L05P_3
E3
I/O
T7
IO_L07N_3
G3
F3
I/O
R7
IO_L07P_3
I/O
T8
IO_L08N_3/VREF_3
IO_L08P_3
G1
F1
VREF
I/O
P8
P9
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L12N_3/IRDY2/LHCLK3
IO_L12P_3/LHCLK2
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
H1
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
N9
G2
J3
T9
R9
H3
P10
T10
R11
T11
J1
J2
IO_L15N_2/DOUT
IO_L15P_2/AWAKE
DUAL
PWRMGT
K1
K3
84
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 69: Spartan-3A FT256 Pinout (XC3S700A,
Table 69: Spartan-3A FT256 Pinout (XC3S700A,
XC3S700A
XC3S1400A
FT256
Ball
XC3S700A
XC3S1400A
FT256
Ball
Bank
Type
Bank
Type
3
3
IO_L16N_3
L2
L1
I/O
VREF
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G8
H11
H5
GND
GND
IO_L16P_3/VREF_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L22N_3
IO_L22P_3/VREF_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP_3
3
L3
GND
3
K4
I/O
H7
GND
3
L4
I/O
H9
GND
3
M3
N1
M1
P1
I/O
J10
J6
GND
3
I/O
GND
3
I/O
J8
GND
3
I/O
K11
K12
K2
GND
3
N2
P2
VREF
I/O
GND
3
GND
3
R1
M4
N3
J4
I/O
K5
GND
3
I/O
K7
GND
3
I/O
K9
GND
3
INPUT
VREF
VREF
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L10
L11
L15
L6
GND
3
IP_3/VREF_3
IP_3/VREF_3
VCCO_3
VCCO_3
VCCO_3
GND
G4
J5
GND
3
GND
3
D2
H2
M2
A1
GND
3
L8
GND
3
M12
M5
M8
N10
N7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A16
B11
B7
GND
GND
GND
GND
GND
GND
C14
C3
E10
E12
E5
P14
P3
GND
GND
GND
GND
R10
R6
GND
GND
GND
GND
T1
GND
GND
F11
F2
T16
R16
T15
A2
GND
GND
VCCAUX SUSPEND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
PWRMGT
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
VCCAUX
VCCAUX
VCCAUX
GND
F6
GND
F7
GND
F8
A15
B1
GND
F9
VCCAUX TDI
GND
G10
G12
G15
G5
G6
VCCAUX TDO
B16
B2
GND
VCCAUX TMS
GND
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
D6
GND
E11
F12
GND
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
85
Pinout Descriptions
Table 69: Spartan-3A FT256 Pinout (XC3S700A,
XC3S700A
XC3S1400A
FT256
Ball
Bank
Type
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
F5
H14
H4
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
L12
L5
M10
M6
F10
G11
G7
G9
H10
H6
H8
J11
J7
J9
K10
K6
K8
L7
L9
86
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
User I/Os by Bank
Table 70, Table 71, and Table 72 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FT256 package. The AWAKE pin is counted as a
dual-purpose I/O.
The XC3S50A FPGA in the FT256 package has 51
unconnected balls, labeled with an “N.C.” type. These pins
are also indicated in Figure 20.
Table 70: User I/Os Per Bank on XC3S50A in the FT256 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
I/O
21
12
5
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
40
32
7
5
1
4
3
3
Right
8
Bottom
Left
40
2
21
0
6
6
32
15
53
6
3
8
TOTAL
144
20
26
15
30
.
Table 71: User I/Os Per Bank on XC3S200A and XC3S400A in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
27
1
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
47
50
6
6
5
5
Right
30
21
0
8
Bottom
Left
48
11
30
69
2
6
8
50
7
5
8
TOTAL
195
21
52
21
32
Table 72: User I/Os Per Bank on XC3S700A and XC3S1400A in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
27
0
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
41
40
1
0
0
1
2
4
4
Right
30
21
0
6
Bottom
Left
41
7
5
8
39
25
59
5
8
TOTAL
161
52
18
30
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
87
Pinout Descriptions
Footprint Migration Differences
Unconnected Balls on XC3S50A
Table 73: FT256 XC3S50A Footprint Migration
Table 73 summarizes any footprint and functionality
differences between the XC3S50A and the XC3S200A or
XC3S400A FPGAs that might affect easy migration between
these devices in the FT256 package. The XC3S200A and
XC3S400A have identical pinouts. The XC3S50A pinout is
compatible, but there are 52 balls that are different.
Generally, designs easily migrate upward from the
XC3S50A to either the XC3S200A or XC3S400A. If using
differential I/O, see Table 74. If using the BPI configuration
mode (parallel Flash), see Table 75.
XC3S200A/
XC3S400A
Type
FT256
Ball
XC3S50A
Type
Bank
3
Migration
Æ
K4
K13
L1
N.C.
I/O
1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Æ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
Æ
L2
3
Æ
L3
3
Æ
L4
3
Æ
Table 73: FT256 XC3S50A Footprint Migration Difference
L13
L14
L16
M3
1
Æ
XC3S200A/
FT256
Ball
XC3S50A
Type
XC3S400A
Type
1
Æ
Bank
0
Migration
Æ
1
Æ
A7
A12
B12
C7
N.C.
I/O
3
Æ
0
N.C.
INPUT
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Æ
I/O
M10
M13
M14
M15
M16
N7
2
Æ
0
Æ
I/O
1
Æ
0
Æ
I/O
1
Æ
D10
E2
0
Æ
I/O
1
Æ
3
Æ
I/O
1
Æ
E3
3
Æ
I/O
2
Æ
E7
0
Æ
I/O
N10
N12
P6
2
Æ
E10
E16
F3
0
Æ
I/O
2
Æ
1
Æ
I/O
2
Æ
3
Æ
I/O
P13
R7
2
Æ
F8
0
Æ
I/O
2
Æ
F14
F15
F16
G3
1
Æ
I/O
T7
2
Æ
1
Æ
I/O
DIFFERENCES
Legend:
52
1
Æ
I/O
3
Æ
I/O
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
Æ
G4
3
Æ
I/O
G5
3
Æ
INPUT
INPUT
I/O
G6
3
Æ
G13
G14
G16
H4
1
Æ
1
Æ
I/O
1
Æ
I/O
3
Æ
I/O
H5
3
Æ
I/O
H6
3
Æ
I/O
H13
J4
1
Æ
I/O
3
Æ
I/O
J6
3
Æ
I/O
J10
J11
1
Æ
INPUT
INPUT
1
Æ
88
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
XC3S50A Differential I/O Alignment Differences
Also, some differential I/O pairs on the XC3S50A FPGA are
aligned differently than the corresponding pairs on the
XC3S200A or XC3S400A FPGAs, as shown in Table 74. All
the mismatched pairs are in I/O Bank 2. The shading
highlights the N side of each pair.
Table 74: Differential I/O Differences in FT256
FT256
Ball
XC3S200A
XC3S400A
Bank
XC3S50A
T3
N6
R5
T5
IO_L04P_2/VS2
IO_L03N_2/VS1
IO_L06P_2
IO_L03N_2/VS2
IO_L04P_2/VS1
IO_L05N_2
IO_L05N_2/D7
IO_L06P_2/D7
2
IO_L14P_2/MOSI IO_L14N_2/MOSI
P10
/CSI_B
/CSI_B
T10
R13
T14
IO_L14N_2
IO_L20P_2
IO_L18N_2
IO_L14P_2
IO_L18N_2
IO_L20P_2
XC3S50A Does Not Have BPI Mode Address Outputs
The XC3S50A FPGA does not generate the BPI-mode
address pins during configuration. Table 75 summarizes
these differences.
Table 75: XC3S50A BPI Functional Differences
FT256
Ball
XC3S200A
XC3S400A
Bank
XC3S50A
IO_L03N_1
N16
P16
J13
IO_L03N_1/A1
IO_L03P_1/A0
IO_L10N_1/A9
IO_L10P_1/A8
IO_L20N_1/A19
IO_L20P_1/A18
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
IO_L03P_1
IO_L10N_1
IO_L10P_1
IO_L20N_1
IO_L20P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1
IO_L23P_1
IO_L24N_1
IO_L24P_1
J12
F13
E14
D15
D16
D14
E13
C15
C16
1
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
89
Pinout Descriptions
Differences Between XC3S200A/XC3S400A and XC3S700A/XC3S1400A
The XC3S700A and XC3S1400A FPGAs have several
additional power and ground pins as compared to the
XC3S200A and XC3S400A. Table 76 summarizes all the
differences. All dedicated and dual-purpose configuration
pins are in the same location.
Table 76: Differences Between XC3S200A/XC3S400A
and XC3S700A/XC3S1400A (Continued)
XC3S200A
XC3S700A
FT256
Ball
XC3S400A
XC3S1400A
Bank
Pin Name
Type
I/O
Pin Name
GND
Type
Table 76: Differences Between XC3S200A/XC3S400A
and XC3S700A/XC3S1400A
N10
M10
2
2
IO_L13P_2
IO_L13N_2
GND
I/O
VCCAUX
VCCAUX
XC3S200A
XC3S400A
XC3S700A
IP_2/
FT256
Ball
XC3S1400A
P6
2
IO_L07N_2
I/O
VREF
Bank
VREF_2
Pin Name
Type
I/O
Pin Name
Type
GND
I/O
L8
L7
2
2
IP_2
IP_2
INPUT GND
GND
F8
0
0
IO_L14P_0
IO_L03N_0
GND
INPUT VCCINT
VCCINT
D11
I/O
IO_L06P_0
IP_2/
VCCO
M9
L10
M8
L9
2
2
2
2
VCCO_2
VREF
GND
VREF_2
IO_L06N_0/
VREF_0
D10
0
IO_L06P_0
I/O
VREF
IP_2/
VREF_2
VREF GND
VREF GND
VREF VCCINT
F7
F9
0
0
0
IP_0
IP_0
IP_0
INPUT GND
GND
GND
I/O
IP_2/
VREF_2
INPUT GND
GND
D12
INPUT IO_L03N_0
IP_2/
VREF_2
VCCINT
IP_0/
VREF_0
E9
0
INPUT IO_L14P_0
I/O
H5
J6
3
3
3
3
3
3
IO_L10N_3
IO_L17N_3
IO_L09P_3
IO_L17P_3
IO_L09N_3
IO_L10P_3
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
D6
0
0
IP_0
IP_0
INPUT VCCAUX
INPUT VCCINT
VCCAUX
VCCINT
GND
F10
G3
J4
IO_L07N_3
IP_3
I/O
IO_L06N_0/
VREF_0
E10
M13
0
1
VREF GND
GND
IP
H4
H6
VCCAUX
VCCINT
VCCAUX
VCCINT
IP_1/
I/O
IO_L05P_1
VREF
VREF_1
F11
H11
K11
G11
H10
J11
1
1
1
1
1
1
IP_L25N_1 INPUT GND
IP_L13N_1 INPUT GND
IP_L04P_1 INPUT GND
IP_L21N_1 INPUT VCCINT
IP_L13P_1 INPUT VCCINT
IP_L09N_1 INPUT VCCINT
GND
GND
IO_L22P_3/
VREF_3
N2
G4
3
3
IO_L22P_3
IO_L07N_3
I/O
I/O
VREF
VREF
IP_3/
VREF_3
GND
VCCINT
VCCINT
VCCINT
G6
H7
K5
E4
L5
J7
3
3
3
3
3
3
3
IP_L06P_3 INPUT GND
IP_L13P_3 INPUT GND
IP_L21P_3 INPUT GND
IP_L04P_3 INPUT IO_L04P_3
IP_L25P_3 INPUT VCCAUX
IP_L13N_3 INPUT VCCINT
IP_L21N_3 INPUT VCCINT
IP_3/
GND
GND
GND
IO_L14N_1/
RHCLK VCCAUX
RHCLK5
H14
J14
H12
G12
J10
K12
F12
1
1
1
1
1
1
1
VCCAUX
VREF
VREF
GND
I/O
VCCAUX
VCCINT
VCCINT
IO_L14P_1/
RHCLK4
IP_1/
RHCLK
VCCO
VREF_1
IP_1/
VREF_1
VCCO_1
K6
IP_L21P_1/
VREF_1
J5
G5
L6
F4
3
3
3
3
VCCO_3
VCCO
VREF
GND
GND
I/O
VREF GND
VREF GND
VREF GND
VREF VCCAUX
VREF_3
IP_L06N_3/
VREF_3
IP_L09P_1/
VREF_1
VREF GND
GND
IP_L25N_3/
VREF_3
IP_L04N_1/
VREF_1
VREF GND
GND
IP_L04N_3/
VREF_3
IP_L25P_1/
VREF_1
VREF IO_L04N_3
VCCAUX
IO_L05N_1/
VREF_1
IP_1/
VREF
M14
N7
1
2
VREF
GND
VREF_1
IO_L07P_2
I/O
GND
90
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FT256 Footprint (XC3S50A)
(Differential Outputs)
(Differential Outputs)
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
N.C.
N.C.
TCK
GND
L12P_0
L10N_0
A
B
C
D
E
F
L19P_0
L18P_0
L17P_0
L15P_0
L08N_0
L07N_0
L04N_0
L04P_0
GCLK10
GCLK7
I/O
L12N_0
GCLK11
I/O
L02P_0
VREF_0
I/O
L19N_0
I/O
L18N_0
I/O
L15N_0
I/O
L08P_0
I/O
L02N_0
VCCO_0
VCCO_0
VCCO_0
TDI
TMS
GND
N.C.
GND
INPUT
TDO
I/O
L20P_0
VREF_0
I/O
L11P_0
GCLK8
I/O
L10P_0
GCLK6
I/O
L09P_0
GCLK4
I/O
L01N_3
I/O
L01P_3
I/O
L17N_0
I/O
L16N_0
I/O
L07P_0
I/O
L03P_0
I/O
L01N_0
I/O
L24N_1
I/O
L24P_1
GND
GND
I/O
L20N_0
PUDC_B
I/O
L11N_0
GCLK9
I/O
L09N_0
GCLK5
I/O
L03P_3
I/O
L02N_3
I/O
L02P_3
I/O
L16P_0
I/O
L03N_0
I/O
L01P_0
I/O
L23N_1
I/O
L22N_1
I/O
L22P_1
VCCO_3
N.C.
INPUT
INPUT
GND
N.C.
N.C.
INPUT
GND
I/O
L03N_3
INPUT
L04P_3
INPUT
VREF_0
I/O
L23P_1
I/O
L20P_1
VCCO_0
VCCAUX
VCCO_1
N.C.
N.C.
N.C.
N.C.
GND
VCCAUX
N.C.
N.C.
N.C.
N.C.
N.C.
INPUT
L04N_3
VREF_3
INPUT
L25P_1
VREF_1
I/O
L08P_3
INPUT
L25N_1
I/O
L20N_1
GND
INPUT
N.C.
INPUT INPUT
N.C.
N.C.
I/O
L08N_3
VREF_3 LHCLK0
I/O
L11P_3
INPUT
L21P_1
VREF_1
INPUT
L21N_1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C. VCCINT GND VCCINT GND
N.C.
N.C.
GND
G
H
J
I/O
L15P_1
IRDY1
I/O
I/O
L12P_3
LHCLK2
I/O
L14N_1
RHCLK5
I/O
L15N_1
RHCLK7
INPUT
INPUT INPUT
L13P_1
VCCO_3
L11N_3
VCCO_1
N.C.
N.C.
N.C.
VCCINT GND
L13P_3
L13N_1
LHCLK1
RHCLK6
I/O
L12N_3
IRDY2
LHCLK3
I/O
L12N_1
TRDY1
RHCLK3
I/O
L14N_3
LHCLK5 LHCLK4
I/O
L14P_3
I/O
L14P_1
RHCLK4
INPUT
L13N_3
I/O
L10P_1
I/O
L10N_1
VCCO_3
VCCO_1
GND VCCINT N.C.
N.C.
I/O
L15P_3
TRDY2
LHCLK6
I/O
L15N_3
LHCLK7
INPUT
L04N_1
VREF_1
I/O
L11N_1
I/O
L11P_1
I/O
L12P_1
INPUT INPUT
L21P_3
INPUT
L04P_1
GND
N.C.
GND VCCINT GND VCCINT
N.C.
N.C.
N.C.
K
L
L21N_3
RHCLK1 RHCLK0 RHCLK2
INPUT
L25N_3
VREF_3
INPUT
L25P_3
INPUT INPUT
INPUT INPUT
VCCAUX
GND
N.C.
N.C.
N.C.
GND
N.C.
N.C.
GND
N.C.
N.C.
N.C.
VREF_2 VREF_2
I/O
L20P_3
I/O
L24N_3
INPUT INPUT
VREF_2 VREF_2
INPUT
VREF_2
VCCO_3
VCCAUX
VCCO_2
GND
N.C.
N.C.
M
N
P
R
T
I/O
L01P_2
M1
I/O
L03N_2
VS1
I/O
L08N_2
D4
I/O
L11P_2
GCLK0
I/O
L01P_1
HDC
I/O
L01N_1
LDC2
I/O
L20N_3
I/O
L22P_3
I/O
L24P_3
INPUT
VREF_2
I/O
L16N_2
I/O
L03N_1
VCCO_1
N.C.
N.C.
I/O
L14P_2
MOSI
I/O
L01N_2
M0
I/O
L04N_2
VS0
I/O
L08P_2
D5
I/O
L10P_2
GCLK14
I/O
L11N_2
GCLK1
I/O
L17N_2
D3
I/O
L02N_1
LDC0
I/O
L22N_3
I/O
L23N_3
I/O
L16P_2
I/O
L03P_1
GND
N.C.
N.C.
GND
CSI_B
I/O
L02P_2
M2
I/O
L03P_2
RDWR_B
I/O
L12P_2
GCLK2
I/O
L15N_2
DOUT
I/O
L20P_2
D1
I/O
L20N_2
CCLK
I/O
L02P_1
LDC1
I/O
L23P_3
I/O
L06P_2
VCCO_2
VCCO_2
VCCO_2
GND
N.C.
N.C.
GND
I/O
L18N_2
D0
I/O
L02N_2
CSO_B
I/O
L04P_2
VS2
I/O
L05N_2
D7
I/O
L06N_2
D6
I/O
L10N_2
GCLK15
I/O
L12N_2
GCLK3
I/O
L15P_2
AWAKE
I/O
L17P_2
INIT_B
I/O
L18P_2
D2
I/O
L05P_2
I/O
L14N_2
GND
DONE
GND
DIN/MISO
(Differential Outputs)
Bank 2
(Differential Outputs)
DS529-4_09_012009
Figure 20: XC3S50A FT256 Package Footprint (Top View)
I/O: Unrestricted,
DUAL: Configuration pins,
VREF: User I/O or input
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
53
20
2
25
30
4
15
16
6
2
general-purpose user I/O
then possible user I/O
voltage reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or
global buffer input
VCCO: Output voltage
supply for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
supply voltage (+1.2V)
N.C.: Not connected
(XC3S50A only)
GND: Ground
VCCAUX: Auxiliary supply
voltage
51
28
4
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
91
Pinout Descriptions
FT256 Footprint (XC3S200A, XC3S400A)
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
TCK
GND
L12P_0
L10N_0
A
B
C
D
E
F
L19P_0
L18P_0
L17P_0
L15P_0
L13P_0
L08N_0
L07N_0
L05N_0
L04N_0
L04P_0
GCLK10
GCLK7
I/O
L12N_0
GCLK11
I/O
L02P_0
VREF_0
I/O
L19N_0
I/O
L18N_0
I/O
L15N_0
I/O
L08P_0
I/O
L05P_0
I/O
L02N_0
VCCO_0
VCCO_0
VCCO_0
TDI
TMS
GND
GND
TDO
I/O
L20P_0
VREF_0
I/O
L11P_0
GCLK8
I/O
L10P_0
GCLK6
I/O
L09P_0
GCLK4
I/O
L24N_1
A25
I/O
L24P_1
A24
I/O
L01N_3
I/O
L01P_3
I/O
L17N_0
I/O
L16N_0
I/O
L13N_0
I/O
L07P_0
I/O
L03P_0
I/O
L01N_0
GND
GND
I/O
L20N_0
PUDC_B
I/O
L11N_0
GCLK9
I/O
L09N_0
GCLK5
I/O
L23N_1
A23
I/O
L22N_1
A21
I/O
L22P_1
A20
I/O
L03P_3
I/O
L02N_3
I/O
L02P_3
I/O
L16P_0
I/O
L06P_0
I/O
L03N_0
I/O
L01P_0
VCCO_3
INPUT
INPUT
GND
INPUT
GND
I/O
L14N_0
VREF_0
I/O
L06N_0
VREF_0
I/O
L23P_1
A22
I/O
L20P_1
A18
I/O
L18P_1
A14
I/O
L03N_3
I/O
L05N_3
I/O
L05P_3
INPUT
L04P_3
INPUT
VREF_0
VCCO_0
VCCAUX
VCCO_1
GND
INPUT
L04N_3
VREF_3
INPUT
L25P_1
VREF_1
I/O
L20N_1
A19
I/O
L19N_1
A17
I/O
L18N_1
A15
I/O
L16N_1
A11
I/O
L08P_3
I/O
L07P_3
I/O
L14P_0
INPUT
L25N_1
VCCAUX
GND
INPUT
INPUT INPUT
I/O
I/O
INPUT
L06N_3
VREF_3
INPUT
L21P_1
VREF_1
I/O
L19P_1
A16
I/O
L17N_1
A13
I/O
L16P_1
A10
I/O
I/O
INPUT
INPUT
VCCINT GND VCCINT GND
GND
L08N_3
L11P_3
G
H
J
L09P_3
L07N_3
L06P_3
L21N_1
VREF_3 LHCLK0
I/O
L15P_1
IRDY1
I/O
I/O
L12P_3
LHCLK2
I/O
L17P_1
A12
I/O
L14N_1
RHCLK5
I/O
L15N_1
RHCLK7
I/O
L09N_3
I/O
L10N_3
I/O
L10P_3
INPUT
INPUT INPUT
VCCO_3
L11N_3
VCCO_1
VCCINT GND
GND VCCINT
L13P_3
L13P_1
L13N_1
LHCLK1
RHCLK6
I/O
L12N_3
IRDY2
LHCLK3
I/O
L12N_1
TRDY1
RHCLK3
I/O
L14N_3
LHCLK5 LHCLK4
I/O
L14P_3
INPUT
L09P_1
VREF_1
I/O
L10P_1
A8
I/O
L10N_1
A9
I/O
L14P_1
RHCLK4
I/O
L17P_3
I/O
L17N_3
INPUT
L13N_3
INPUT
L09N_1
VCCO_3
VCCO_1
I/O
L15P_3
TRDY2
LHCLK6
I/O
INPUT
L04N_1
VREF_1
I/O
L06N_1
A3
I/O
I/O
I/O
I/O
L18P_3
INPUT INPUT
INPUT
L04P_1
GND
GND VCCINT GND VCCINT
L15N_3
L11N_1
L11P_1
L12P_1
K
L
L21P_3
L21N_3
LHCLK7
RHCLK1 RHCLK0 RHCLK2
I/O
INPUT
L25N_3
VREF_3
I/O
L06P_1
A2
I/O
L08P_1
A6
I/O
L08N_1
A7
I/O
L16N_3
I/O
L18N_3
I/O
L19N_3
INPUT
L25P_3
INPUT INPUT
INPUT INPUT
VCCAUX
GND
GND
L16P_3
VREF_2 VREF_2
VREF_3
I/O
I/O
L07P_1
A4
I/O
L07N_1
A5
I/O
I/O
I/O
INPUT INPUT
I/O
INPUT
I/O
VCCO_3
VCCAUX
VCCO_2
GND
GND
L05N_1
M
N
P
R
T
L20P_3
L19P_3
L24N_3
VREF_2 VREF_2
L13N_2 VREF_2
L05P_1
VREF_1
I/O
L01P_2
M1
I/O
L04P_2
VS1
I/O
I/O
I/O
L11P_2
GCLK0
I/O
L01P_1
HDC
I/O
L01N_1
LDC2
I/O
L03N_1
A1
I/O
L20N_3
I/O
L22P_3
I/O
L24P_3
INPUT
VREF_2
I/O
L13P_2
I/O
L16N_2
I/O
L19P_2
VCCO_1
L08N_2
L07P_2
D4
I/O
L14N_2
MOSI
I/O
L01N_2
M0
I/O
L04N_2
VS0
I/O
L08P_2
D5
I/O
I/O
L11N_2
GCLK1
I/O
L17N_2
D3
I/O
L02N_1
LDC0
I/O
L03P_1
A0
I/O
L22N_3
I/O
L23N_3
I/O
L07N_2
I/O
L16P_2
I/O
L19N_2
GND
GND
L10P_2
GCLK14
CSI_B
I/O
L02P_2
M2
I/O
L03P_2
RDWR_B
I/O
L09P_2
I/O
L12P_2
GCLK2
I/O
L15N_2
DOUT
I/O
L18N_2
D1
I/O
L20N_2
CCLK
I/O
L02P_1
LDC1
I/O
L23P_3
I/O
L05N_2
VCCO_2
VCCO_2
VCCO_2
GND
GND
GCLK12
I/O
L20P_2
D0
I/O
L02N_2
CSO_B
I/O
L03N_2
VS2
I/O
L06P_2
D7
I/O
L06N_2
D6
I/O
L09N_2
I/O
L10N_2
I/O
L12N_2
GCLK3
I/O
L15P_2
AWAKE
I/O
L17P_2
INIT_B
I/O
L18P_2
D2
I/O
L05P_2
I/O
L14P_2
GND
DONE
GND
GCLK13 GCLK15
DIN/MISO
DS529-4_06_012009
Bank 2
Figure 21: XC3S200A and XC3S400A FT256 Package Footprint (Top View)
I/O: Unrestricted,
DUAL: Configuration pins,
VREF: User I/O or input
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
69
21
2
51
32
4
21
16
6
2
general-purpose user I/O
then possible user I/O
voltage reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or
global buffer input
VCCO: Output voltage
supply for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
supply voltage (+1.2V)
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage
0
28
4
92
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FT256 Footprint (XC3S700A, XC3S1400A)
Bank 0
11
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND PROG_B
GND
TCK
L12P_0 L10N_0
GCLK10
A
B
C
D
E
F
L19P_0 L18P_0 L17P_0 L15P_0 L13P_0
L08N_0 L07N_0 L05N_0 L04N_0 L04P_0
GCLK7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
TMS
I/O
VCCO_0
I/O
GND L12N_0 VCCO_0
GND
I/O
VCCO_0
I/O
L02P_0
VREF_0
TDO
I/O
L19N_0 L18N_0
L15N_0
L08P_0
L05P_0
L02N_0
GCLK11
I/O
L20P_0
VREF_0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
L11P_0 L10P_0 L09P_0
GCLK8 GCLK6 GCLK4
GND
I/O
L24N_1 L24P_1
L01N_3 L01P_3
L17N_0 L16N_0 L13N_0
L07P_0 L03P_0 L01N_0
A25
A24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L16P_0
I/O
I/O
I/O
VCCO_3
L03P_3
L20N_0 VCCAUX
L11N_0 L09N_0 L06N_0
GCLK9 GCLK5 VREF_0
L23N_1 L22N_1 L22P_1
L02N_3 L02P_3
L06P_0 L03N_0 L01P_0
PUDC_B
A23
A21
A20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L14P_0
GND
INPUT L14N_0 VCCO_0
GND VCCAUX GND
L23P_1 L20P_1 VCCO_1 L18P_1
L03N_3 L05N_3 L05P_3 L04P_3
VREF_0
A22
A18
A14
I/O
I/O
I/O
I/O
I/O
L08P_3
I/O
I/O
GND
I/O
VCCAUX GND
GND
GND
GND
GND VCCINT GND VCCAUX L20N_1 L19N_1 L18N_1 L16N_1
L07P_3 L04N_3
A19
A17
A15
A11
I/O
I/O
I/O
I/O
L16P_1
A10
I/O
L07N_3
INPUT
VREF_3
L08N_3 L11P_3
VREF_3 LHCLK0
GND
GND
VCCINT
VCCINT
GND
VCCINT GND
INPUT
L19P_1 L17N_1
GND
G
H
J
A16
A13
I/O
I/O
I/O
I/O
I/O
L15N_1
RHCLK7
L15P_1
IRDY1
RHCLK6
L11N_3 VCCO_3 L12P_3 VCCAUX GND VCCINT GND VCCINT GND VCCINT GND
L17P_1 VCCAUX
A12
VREF_1
LHCLK1
LHCLK2
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
VREF_3
INPUT
VREF_1
L12N_3
IRDY2
LHCLK3
L12N_1
TRDY1
RHCLK3
L14N_3 L14P_3
LHCLK5 LHCLK4
INPUT
GND
VCCINT
GND
VCCINT
GND
VCCINT L10P_1 L10N_1
VCCO_1
A8
A9
I/O
I/O
L15N_3
LHCLK7
I/O
I/O
I/O
I/O
I/O
L18P_3
L15P_3
TRDY2
LHCLK6
GND
GND VCCINT GND VCCINT GND VCCINT GND
GND
L06N_1 L11N_1 L11P_1 L12P_1
K
L
A3
RHCLK1 RHCLK0 RHCLK2
I/O
I/O
I/O
I/O
L08N_1
A7
I/O
I/O
I/O
L16P_3
VREF_3
VCCAUX GND
GND VCCAUX
VCCINT
GND
VCCINT
GND
VCCAUX
GND
GND VCCAUX L06P_1 L08P_1
GND
I/O
L16N_3 L18N_3 L19N_3
A2
A6
I/O
I/O
L20P_3
I/O
I/O
INPUT
VREF_2
INPUT
VREF_2
INPUT
INPUT INPUT
VREF_1 VREF_1
VCCO_3
GND
I/O
L08N_2 L11P_2
D4
GND
I/O
L07P_1 L07N_1
M
N
P
R
T
L19P_3 L24N_3
VREF_2
A4
A5
I/O
L22P_3
VREF_3
I/O
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
L20N_3
I/O
L01P_2
L24P_3
M1
L04P_2
GND
I/O
L01P_1 L01N_1 VCCO_1 L03N_1
VREF_2
VS1
L16N_2 L19P_2
GCLK0
HDC
LDC2
GND
I/O
A1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L19N_2
I/O
I/O
INPUT
L14N_2
MOSI
GND
I/O
L01N_2 L04N_2
L08P_2 L10P_2 L11N_2
D5
L17N_2
L16P_2
D3
L02N_1 L03P_1
L22N_3 L23N_3
VREF_2
VS0
M0
GCLK14 GCLK1
LDC0
A0
CSI_B
I/O
I/O
L23P_3
I/O
I/O
I/O
I/O
I/O
I/O
L05N_2
L02P_2 L03P_2 VCCO_2
M2
GND
L09P_2 VCCO_2 L12P_2
GND
L15N_2 VCCO_2 L18N_2 L20N_2 L02P_1
RDWR_B
GCLK12
GCLK2
DOUT
D1
CCLK
LDC1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L14P_2
I/O
L05P_2
L20P_2
D0/DIN
MISO
GND
L02N_2 L03N_2
L06P_2 L06N_2 L09N_2 L10N_2 L12N_2
L15P_2 L17P_2 L18P_2
DONE
GND
CSO_B
VS2
D7
D6
GCLK13 GCLK15 GCLK3
AWAKE INIT_B
D2
Bank 2
DS529-4_012009
Figure 22: XC3S700A and XC3S1400A FT256 Package Footprint (Top View)
I/O: Unrestricted,
DUAL: Configuration, then
VREF: User I/O or input
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
2
59
2
51
30
4
18
13
15
10
general-purpose user I/O
possible user I/O
voltage reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or
global buffer input
VCCO: Output voltage
supply for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
supply voltage (+1.2V)
2
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage
0
50
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
93
Pinout Descriptions
FG320: 320-ball Fine-pitch Ball Grid Array
The 320-ball fine-pitch ball grid array package, FG320,
supports two Spartan-3A FPGAs, the XC3S200A and the
XC3S400A, as shown in Table 77 and Figure 23.
Table 77: Spartan-3A FG320 Pinout(Continued)
FG320
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L09P_0
Ball
B11
D10
C11
C9
B10
B9
Type
I/O
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
IO_L10N_0
I/O
Table 77 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
IO_L10P_0
I/O
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L13N_0/GCLK9
IO_L13P_0/GCLK8
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
The shaded rows indicate pinout differences between the
XC3S200A and the XC3S400A FPGAs. The XC3S200A
has three unconnected balls, indicated as N.C. (No
Connection) in Table 77 and with the black diamond
character () in Table 77 and Figure 23.
A10
B7
A8
C8
B8
All other balls have nearly identical functionality on all three
devices. Table 80 summarizes the Spartan-3A FPGA
footprint migration differences for the FG320 package.
C7
D8
E9
IO_L15P_0
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
IO_L16N_0
I/O
IO_L16P_0
D9
B6
I/O
IO_L17N_0
I/O
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L17P_0
A6
I/O
IO_L18N_0/VREF_0
IO_L18P_0
A4
VREF
I/O
Pinout Table
A5
Table 77: Spartan-3A FG320 Pinout
IO_L19N_0
E7
I/O
IO_L19P_0
F8
I/O
FG320
Bank
Pin Name
IO_L01N_0
Ball
C15
C16
A16
B16
A14
A15
C14
B15
D12
C13
A13
B13
B12
C12
F11
E11
A11
Type
I/O
IO_L20N_0
D6
C6
A3
I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L20P_0
I/O
IO_L01P_0
I/O
IO_L21N_0
I/O
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
I/O
IO_L21P_0
B4
I/O
VREF
I/O
IO_L22N_0
D5
C5
A2
I/O
IO_L22P_0
I/O
I/O
IO_L23N_0
I/O
IO_L04N_0
IO_L04P_0
I/O
IO_L23P_0
B3
I/O
I/O
IO_L24N_0/PUDC_B
IO_L24P_0/VREF_0
IP_0
E5
DUAL
VREF
INPUT
INPUT
INPUT
IO_L05N_0
IO_L05P_0
I/O
E6
I/O
D13
D14
E12
IO_L06N_0/VREF_0
IO_L06P_0
VREF
I/O
IP_0
IP_0
IO_L07N_0
IO_L07P_0
I/O
XC3S400A: IP_0
XC3S200A: N.C. (◆)
0
E13
INPUT
I/O
0
0
0
IP_0
IP_0
IP_0
F7
F9
INPUT
INPUT
INPUT
IO_L08N_0
IO_L08P_0
I/O
I/O
F10
IO_L09N_0
I/O
94
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 77: Spartan-3A FG320 Pinout(Continued)
Table 77: Spartan-3A FG320 Pinout(Continued)
FG320
FG320
Ball
Bank
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
Ball
F12
G7
Type
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
Pin Name
IO_L21N_1
Type
I/O
IP_0
IP_0
IP_0
IP_0
IP_0
F17
G17
E18
F18
H15
J14
D17
D18
E16
F16
F15
G15
E15
D16
B18
C18
B17
C17
N14
P15
L14
M13
L16
M15
K14
K13
J13
K12
G14
H13
G13
H12
F13
F14
E17
H14
L15
P17
U3
IO_L21P_1
I/O
G8
IO_L22N_1/A13
IO_L22P_1/A12
IO_L23N_1/A15
IO_L23P_1/A14
IO_L25N_1
DUAL
DUAL
DUAL
DUAL
I/O
G9
G11
E10
B5
IP_0/VREF_0
VCCO_0
VCCO_0
B14
D11
E8
IO_L25P_1
I/O
VCCO_0
IO_L26N_1/A17
IO_L26P_1/A16
IO_L27N_1/A19
IO_L27P_1/A18
IO_L29N_1/A21
IO_L29P_1/A20
IO_L30N_1/A23
IO_L30P_1/A22
IO_L31N_1/A25
IO_L31P_1/A24
IP_L04N_1/VREF_1
IP_L04P_1
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
INPUT
VREF
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
VCCO_0
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1
T17
R16
U18
U17
R17
T18
N16
P16
M14
N15
P18
R18
M17
M16
N18
N17
L12
L13
K16
L17
K17
L18
J17
K18
K15
J16
H17
H18
G16
H16
IO_L05P_1
I/O
IO_L06N_1
I/O
IO_L06P_1
I/O
IO_L07N_1/VREF_1
IO_L07P_1
VREF
I/O
IP_L08N_1/VREF_1
IP_L08P_1
IO_L09N_1/A3
IO_L09P_1/A2
IO_L10N_1/A5
IO_L10P_1/A4
IO_L11N_1/A7
IO_L11P_1/A6
IO_L13N_1/A9
IO_L13P_1/A8
IO_L14N_1/RHCLK1
IO_L14P_1/RHCLK0
IO_L15N_1/TRDY1/RHCLK3
IO_L15P_1/RHCLK2
IO_L17N_1/RHCLK5
IO_L17P_1/RHCLK4
IO_L18N_1/RHCLK7
IO_L18P_1/IRDY1/RHCLK6
IO_L19N_1/A11
IO_L19P_1/A10
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
IP_L12N_1
IP_L12P_1/VREF_1
IP_L16N_1
IP_L16P_1
IP_L20N_1
IP_L20P_1/VREF_1
IP_L24N_1
IP_L24P_1
IP_L28N_1
IP_L28P_1/VREF_1
IP_L32N_1
IP_L32P_1/VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_1
IO_L01N_2/M0
IO_L01P_2/M1
T3
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
95
Pinout Descriptions
Table 77: Spartan-3A FG320 Pinout(Continued)
Table 77: Spartan-3A FG320 Pinout(Continued)
FG320
FG320
Bank
2
Pin Name
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS2
IO_L03P_2/RDWR_B
IO_L04N_2
Ball
Type
DUAL
DUAL
DUAL
DUAL
I/O
Bank
Pin Name
IO_L21P_2
Ball
V14
U15
V15
T15
R14
U16
V16
M8
Type
I/O
V3
2
2
2
2
2
2
2
2
2
2
2
V2
IO_L22N_2/D1
IO_L22P_2/D2
IO_L23N_2
IO_L23P_2
IO_L24N_2/CCLK
IO_L24P_2/D0/DIN/MISO
IP_2
DUAL
DUAL
I/O
2
U4
2
T4
2
T5
I/O
2
IO_L04P_2
R5
I/O
DUAL
DUAL
INPUT
INPUT
INPUT
2
IO_L05N_2/VS0
IO_L05P_2/VS1
IO_L06N_2
V5
DUAL
DUAL
I/O
2
V4
2
U6
IP_2
M9
2
IO_L06P_2
T6
I/O
IP_2
M12
2
IO_L07N_2
P8
I/O
XC3S400A: IP_2
2
N7
INPUT
XC3S200A: N.C. (◆)
2
IO_L07P_2
N8
I/O
2
2
2
2
2
2
2
2
2
IP_2
N9
N11
R6
INPUT
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
2
IO_L08N_2/D6
IO_L08P_2/D7
IO_L09N_2
T7
DUAL
DUAL
I/O
IP_2
2
R7
IP_2
2
R9
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
M11
N10
P6
2
IO_L09P_2
T8
I/O
2
IO_L10N_2/D4
IO_L10P_2/D5
IO_L11N_2/GCLK13
IO_L11P_2/GCLK12
IO_L12N_2/GCLK15
IO_L12P_2/GCLK14
IO_L13N_2/GCLK1
IO_L13P_2/GCLK0
IO_L14N_2/GCLK3
IO_L14P_2/GCLK2
IO_L15N_2
V6
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
2
U7
P7
2
V8
P9
2
U8
P13
2
V9
XC3S400A: IP_2/VREF_2
XC3S200A: N.C. (◆)
2
P14
VREF
2
U9
2
T10
U10
U11
V11
R10
P10
T11
R11
V13
U12
U13
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VCCO_2
P11
R8
U5
U14
C1
C2
B1
B2
D2
D3
G5
F5
VCCO
VCCO
VCCO
VCCO
I/O
2
VCCO_2
2
VCCO_2
2
VCCO_2
2
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L09N_3
IO_L09P_3
2
IO_L15P_2
I/O
I/O
2
IO_L16N_2/MOSI/CSI_B
IO_L16P_2
DUAL
I/O
I/O
2
I/O
2
IO_L17N_2
I/O
I/O
2
IO_L17P_2
I/O
I/O
2
IO_L18N_2/DOUT
DUAL
I/O
PWR
MGMT
I/O
2
IO_L18P_2/AWAKE
T12
E3
F4
I/O
2
2
2
2
2
IO_L19N_2
P12
N12
R13
T13
T14
I/O
I/O
I/O
IO_L19P_2
E1
D1
G4
F3
I/O
IO_L20N_2/D3
IO_L20P_2/INIT_B
IO_L21N_2
DUAL
DUAL
I/O
I/O
I/O
I/O
96
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 77: Spartan-3A FG320 Pinout(Continued)
Table 77: Spartan-3A FG320 Pinout(Continued)
FG320
FG320
Ball
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L10N_3/VREF_3
IO_L10P_3
Ball
F1
F2
J6
Type
VREF
I/O
Bank
3
Pin Name
IP_L16N_3
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
GND
K6
J5
3
IP_L16P_3
IP_L20N_3
IP_L20P_3
IP_L24N_3
IP_L24P_3
IP_L28N_3
IP_L28P_3
IP_L32N_3/VREF_3
IP_L32P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
IO_L11N_3
I/O
3
L6
IO_L11P_3
J7
I/O
3
L7
IO_L13N_3
H1
H2
J3
I/O
3
M4
M3
M5
M6
P4
IO_L13P_3
I/O
3
IO_L14N_3/LHCLK1
IO_L14P_3/LHCLK0
IO_L15N_3/IRDY2/LHCLK3
IO_L15P_3/LHCLK2
IO_L17N_3/LHCLK5
IO_L17P_3/LHCLK4
IO_L18N_3/LHCLK7
IO_L18P_3/TRDY2/LHCLK6
IO_L19N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
3
H3
J1
3
3
J2
3
P5
K5
J4
3
E2
3
H4
K3
K2
L2
3
L5
3
P2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
IO_L19P_3/VREF_3
IO_L21N_3
L1
VREF
I/O
GND
A7
GND
M2
N1
N2
P1
L4
GND
A12
A18
C10
D4
GND
IO_L21P_3
I/O
GND
GND
IO_L22N_3
I/O
GND
GND
IO_L22P_3
I/O
GND
GND
IO_L23N_3
I/O
GND
D7
GND
IO_L23P_3
L3
I/O
GND
D15
F6
GND
IO_L25N_3
R2
R1
N4
N3
T2
T1
N6
N5
R3
P3
U2
U1
H7
G6
H5
H6
G2
G3
I/O
GND
GND
IO_L25P_3
I/O
GND
G1
G12
G18
H8
GND
IO_L26N_3
I/O
GND
GND
IO_L26P_3
I/O
GND
GND
IO_L27N_3
I/O
GND
GND
IO_L27P_3
I/O
GND
H10
J11
J15
K4
GND
IO_L29N_3
I/O
GND
GND
IO_L29P_3
I/O
GND
GND
IO_L30N_3
I/O
GND
GND
IO_L30P_3
I/O
GND
K8
GND
IO_L31N_3
I/O
GND
L9
GND
IO_L31P_3
I/O
GND
L11
M1
M7
M18
N13
R4
GND
IP_L04N_3/VREF_3
IP_L04P_3
VREF
INPUT
VREF
INPUT
INPUT
INPUT
GND
GND
GND
GND
IP_L08N_3/VREF_3
IP_L08P_3
GND
GND
GND
GND
IP_L12N_3
GND
GND
IP_L12P_3
GND
R12
GND
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
97
Pinout Descriptions
Table 77: Spartan-3A FG320 Pinout(Continued)
FG320
Bank
GND
GND
GND
GND
GND
GND
Pin Name
Ball
R15
T9
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V1
V7
V12
V18
PWR
MGMT
VCCAUX SUSPEND
T16
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
V17
C4
CONFIG
CONFIG
JTAG
A17
E4
VCCAUX TDI
JTAG
VCCAUX TDO
E14
C3
JTAG
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
A9
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
G10
J12
J18
K1
K7
M10
V10
H9
H11
J8
K11
L8
L10
98
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
User I/Os by Bank
Table 78 and Table 79 indicate how the available user-I/O
pins are distributed between the four I/O banks on the
FG320 package. The AWAKE pin is counted as a
dual-purpose I/O.
Table 78: User I/Os Per Bank for XC3S200A in the FG320 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
I/O
35
9
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
60
64
11
10
6
5
7
Right
Bottom
Left
30
21
0
8
60
19
38
101
6
8
64
13
40
5
8
TOTAL
248
52
23
32
Table 79: User I/Os Per Bank for XC3S400A in the FG320 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
I/O
35
9
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
61
64
12
10
7
5
7
Right
Bottom
Left
30
21
0
8
62
19
38
101
7
8
64
13
42
5
8
TOTAL
251
52
24
32
Footprint Migration Differences
Table 80 summarizes any footprint and functionality
differences between the XC3S200A and the XC3S400A
FPGAs that might affect easy migration between devices
available in the FG320 package. There are three such balls.
All other pins not listed in Table 80 unconditionally migrate
between Spartan-3A devices available in the FG320
package.
The arrows indicate the direction for easy migration.
Table 80: FG320 Footprint Migration Differences
Pin
E13
N7
Bank
XC3S200A
N.C.
Migration
XC3S400A
INPUT
0
2
2
Æ
Æ
Æ
3
N.C.
N.C.
INPUT
P14
INPUT/VREF
DIFFERENCES
Legend:
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
Æ
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
99
Pinout Descriptions
FG320 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
I/O
L18N_0
VREF_0
I/O
L13P_0
GCLK8
I/O
L12P_0
GCLK6
I/O
L06N_0
VREF_0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
GND
GND
GND
TCK
GND
A
B
C
D
E
F
L23N_0
L21N_0
L18P_0
L17P_0
L09N_0
L03N_0
L03P_0
L02N_0
I/O
L13N_0
GCLK9
I/O
L14P_0
GCLK10
I/O
L12N_0
GCLK7
I/O
L11P_0
GCLK4
I/O
L02P_0
VREF_0
I/O
L31N_1
A25
I/O
L30N_1
A23
I/O
L02N_3
I/O
L02P_3
I/O
L23P_0
I/O
L21P_0
I/O
L17N_0
I/O
L09P_0
I/O
L07N_0
I/O
L06P_0
I/O
L04P_0
VCCO_0
VCCO_0
I/O
L14N_0
GCLK11
I/O
L11N_0
GCLK5
I/O
L31P_1
A24
I/O
L30P_1
A22
I/O
L01N_3
I/O
L01P_3
I/O
L22P_0
I/O
L20P_0
I/O
L15N_0
I/O
L10P_0
I/O
L07P_0
I/O
L05P_0
I/O
L04N_0
I/O
L01N_0
I/O
L01P_0
TMS
GND
I/O
L29P_1
A20
I/O
L07P_3
I/O
L03N_3
I/O
L03P_3
I/O
L22N_0
I/O
L20N_0
I/O
L15P_0
I/O
L16P_0
I/O
L10N_0
I/O
L05N_0
I/O
L25N_1
I/O
L25P_1
VCCO_0
GND
TDI
GND
INPUT INPUT
GND
I/O
L24N_0
PUDC_B VREF_0
I/O
L24P_0
I/O
L29N_1
A21
I/O
L26N_1
A17
I/O
L22N_1
A13
INPUT
TDO
◆
I/O
L07N_3
I/O
L06N_3
I/O
L19N_0
I/O
L16N_0
INPUT
VREF_0
I/O
L08P_0
VCCO_3
VCCO_0
VCCO_1
INPUT
INPUT
GND
I/O
L10N_3
VREF_3
INPUT
INPUT
L32N_1
I/O
L27N_1
A19
I/O
L26P_1
A16
I/O
L22P_1
A12
I/O
L10P_3
I/O
L09P_3
I/O
L06P_3
I/O
I/O
L19P_0
I/O
L08N_0
I/O
L21N_1
GND
L05P_3
INPUT
INPUT INPUT
L32P_1
VREF_1
I/O
L27P_1
A18
I/O
L19N_1
A11
INPUT INPUT
L12N_3
I/O
L09N_3
I/O
L05N_3
INPUT
L04P_3
INPUT INPUT
L28N_1
I/O
L21P_1
VCCAUX
GND
INPUT INPUT INPUT
INPUT
INPUT
GND
G
H
J
L12P_3
L24N_1
I/O
L18P_1
IRDY1
I/O
L14P_3
LHCLK0
INPUT
L08N_3
VREF_3
INPUT
L28P_1
VREF_1
I/O
L23N_1
A15
I/O
L19P_1
A10
I/O
L18N_1
RHCLK7
I/O
L13N_3
I/O
L13P_3
INPUT
L08P_3
INPUT
L24P_1
VCCO_3
VCCO_1
GND VCCINT GND VCCINT
L04N_3
VREF_3
RHCLK6
I/O
L15N_3
IRDY2
LHCLK3
I/O
L15N_1
TRDY1
RHCLK3
I/O
L15P_3
I/O
L14N_3
I/O
L17P_3
I/O
L23P_1
A14
I/O
L17P_1
RHCLK4
INPUT
L16P_3
I/O
L11N_3
I/O
L11P_3
INPUT
L20N_1
VCCAUX
VCCAUX
VCCINT
GND
GND
GND
LHCLK2 LHCLK1 LHCLK4
I/O
I/O
I/O
L17N_3
LHCLK5
INPUT
L20P_1
VREF_1
I/O
L17N_1
RHCLK5
I/O
L13N_1
A9
I/O
L14N_1
RHCLK1 RHCLK2
I/O
L15P_1
INPUT
L16N_3
INPUT INPUT
L16P_1
L18P_3
VCCAUX
VCCAUX
GND
VCCINT
K
L
L18N_3
LHCLK7
TRDY2
LHCLK6
L16N_1
I/O
L19P_3
VREF_3
I/O
L11N_1
A7
I/O
L11P_1
A6
INPUT
L08N_1
VREF_1
I/O
L13P_1
A8
I/O
L14P_1
RHCLK0
I/O
L19N_3
I/O
L23P_3
I/O
L23N_3
INPUT INPUT
L20N_3
INPUT
L12N_1
VCCO_3
VCCO_1
VCCINT GND VCCINT GND
INPUT
L20P_3
INPUT
L12P_1
VREF_1
I/O
L09P_1
A2
I/O
L09N_1
A3
I/O
L21N_3
INPUT INPUT INPUT INPUT
INPUT
L08P_1
I/O
L06N_1
VCCAUX
GND
GND
INPUT INPUT
INPUT
GND
M
N
P
R
T
L24P_3
L24N_3
L28N_3
L28P_3
VREF_2
INPUT
L04N_1
VREF_1
I/O
L10P_1
A4
I/O
L10N_1
A5
INPUT
I/O
L21P_3
I/O
L22N_3
I/O
L26P_3
I/O
L26N_3
I/O
L29P_3
I/O
L29N_3
I/O
INPUT
VREF_2
I/O
L19P_2
I/O
L06P_1
I/O
L05N_1
INPUT
L07P_2
INPUT
GND
◆
INPUT
VREF_2
INPUT
L32N_3
VREF_3
I/O
L07N_1
VREF_1
I/O
L22P_3
I/O
L30P_3
INPUT INPUT INPUT
L32P_3
I/O
L07N_2
INPUT
VREF_2
I/O
L15P_2
I/O
L19N_2
INPUT
VREF_2
INPUT
L04P_1
I/O
L05P_1
VCCO_3
VCCO_2
VCCO_1
VREF_2 VREF_2
◆
I/O
L08P_2
D7
I/O
L20N_2
D3
I/O
L01P_1
HDC
I/O
L03N_1
A1
I/O
L25P_3
I/O
L25N_3
I/O
L30N_3
I/O
L04P_2
I/O
L09N_2
I/O
L15N_2
I/O
L16P_2
I/O
L23P_2
I/O
L07P_1
VCCO_2
GND
INPUT
GND
GND
I/O
L16N_2
MOSI
I/O
L01P_2
M1
I/O
L03P_2
RDWR_B
I/O
L08N_2
D6
I/O
L13N_2
GCLK1
I/O
L18P_2
AWAKE
I/O
L20P_2
INIT_B
I/O
L01N_1
LDC2
I/O
L03P_1
A0
I/O
L27P_3
I/O
L27N_3
I/O
L04N_2
I/O
L06P_2
I/O
L09P_2
I/O
L21N_2
I/O
L23N_2
GND
CSI_B
I/O
L01N_2
M0
I/O
L03N_2
VS2
I/O
L10P_2
D5
I/O
I/O
I/O
L13P_2
GCLK0
I/O
L14N_2
GCLK3
I/O
L18N_2
DOUT
I/O
L22N_2
D1
I/O
L24N_2
CCLK
I/O
L02P_1
LDC1
I/O
L02N_1
LDC0
I/O
I/O
I/O
I/O
VCCO_2
VCCO_2
U
V
L11P_2
L12P_2
L31P_3
L31N_3
L06N_2
L17P_2
GCLK12 GCLK14
I/O
L24P_2
D0
I/O
L02P_2
M2
I/O
L02N_2
CSO_B
I/O
L05P_2
VS1
I/O
L05N_2
VS0
I/O
L10N_2
D4
I/O
L11N_2
GCLK13 GCLK15
I/O
L12N_2
I/O
L14P_2
GCLK2
I/O
L22P_2
D2
I/O
L17N_2
I/O
L21P_2
VCCAUX
GND
GND
GND
DONE
GND
DIN/MISO
Bank 2
DS529-4_05_012009
Figure 23: FG320 Package Footprint (Top View)
I/O: Unrestricted,
general-purpose user I/O
DUAL: Configuration
pins, then possible
user-I/O
VREF: User I/O or input
voltage reference for
bank
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
23 -
24
101
51
2
INPUT: Unrestricted,
general-purpose input
pin
CLK: User I/O, input, or
VCCO: Output voltage
40 -
42
global buffer input
supply for bank
32
4
16
6
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
supply voltage (+1.2V)
2
3
N.C.: Not connected.
Only the XC3S200A has
these pins ().
GND: Ground
VCCAUX: Auxiliary
supply voltage
32
8
100
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3A FPGAs, the XC3S400A and the
XC3S700A. Both devices share a common footprint for this
package as shown in Table 81 and Figure 24.
Table 81: Spartan-3A FG400 Pinout(Continued)
FG400
Ball
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L13P_0
Type
I/O
B12
C11
B11
E11
D11
C10
A10
E10
D10
A8
Table 81 lists all the FG400 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
IO_L14N_0
I/O
IO_L14P_0
I/O
IO_L15N_0/GCLK5
IO_L15P_0/GCLK4
IO_L16N_0/GCLK7
IO_L16P_0/GCLK6
IO_L17N_0/GCLK9
IO_L17P_0/GCLK8
IO_L18N_0/GCLK11
IO_L18P_0/GCLK10
IO_L19N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
Pinout Table
A9
C9
B9
Table 81: Spartan-3A FG400 Pinout
IO_L19P_0
I/O
FG400
Bank
0
Pin Name
IO_L01N_0
Ball
A18
B18
C17
D17
E15
D16
A17
B17
A16
C16
C15
D15
A14
C14
A15
B15
F13
E13
C13
D14
C12
B13
F12
D12
A12
Type
I/O
IO_L20N_0
C8
B8
I/O
IO_L20P_0
I/O
0
IO_L01P_0
I/O
IO_L21N_0
D8
C7
F9
I/O
0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
I/O
IO_L21P_0
I/O
0
VREF
I/O
IO_L22N_0/VREF_0
IO_L22P_0
VREF
I/O
0
E9
0
I/O
IO_L23N_0
F8
I/O
0
IO_L04N_0
IO_L04P_0/VREF_0
IO_L05N_0
IO_L05P_0
I/O
IO_L23P_0
E8
I/O
0
VREF
I/O
IO_L24N_0
A7
I/O
0
IO_L24P_0
B7
I/O
0
I/O
IO_L25N_0
C6
A6
I/O
0
IO_L06N_0
IO_L06P_0
I/O
IO_L25P_0
I/O
0
I/O
IO_L26N_0
B5
I/O
0
IO_L07N_0
IO_L07P_0
I/O
IO_L26P_0
A5
I/O
0
I/O
IO_L27N_0
F7
I/O
0
IO_L08N_0
IO_L08P_0
I/O
IO_L27P_0
E7
I/O
0
I/O
IO_L28N_0
D6
C5
C4
A4
I/O
0
IO_L09N_0
IO_L09P_0
I/O
IO_L28P_0
I/O
0
I/O
IO_L29N_0
I/O
0
IO_L10N_0/VREF_0
IO_L10P_0
VREF
I/O
IO_L29P_0
I/O
0
IO_L30N_0
B3
I/O
0
IO_L11N_0
IO_L11P_0
I/O
IO_L30P_0
A3
I/O
0
I/O
IO_L31N_0
F6
I/O
0
IO_L12N_0
IO_L12P_0
I/O
IO_L31P_0
E6
I/O
0
I/O
IO_L32N_0/PUDC_B
B2
DUAL
0
IO_L13N_0
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
101
Pinout Descriptions
Table 81: Spartan-3A FG400 Pinout(Continued)
Table 81: Spartan-3A FG400 Pinout(Continued)
FG400
FG400
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L32P_0/VREF_0
IP_0
Ball
Type
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L13N_1/A5
Ball
N19
N18
M18
M17
L16
L15
M20
M19
L18
L19
L17
K18
J20
Type
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
I/O
A2
E14
F11
F14
G8
IO_L13P_1/A4
IO_L14N_1/A7
IO_L14P_1/A6
IO_L16N_1/A9
IO_L16P_1/A8
IO_L17N_1/RHCLK1
IO_L17P_1/RHCLK0
IO_L18N_1/TRDY1/RHCLK3
IO_L18P_1/RHCLK2
IO_L20N_1/RHCLK5
IO_L20P_1/RHCLK4
IO_L21N_1/RHCLK7
IO_L21P_1/IRDY1/RHCLK6
IO_L22N_1/A11
IO_L22P_1/A10
IO_L24N_1
IP_0
IP_0
IP_0
IP_0
G9
IP_0
G10
G12
G13
H9
IP_0
IP_0
IP_0
IP_0
H10
H11
H12
G11
B4
IP_0
IP_0
IP_0/VREF_0
VCCO_0
K20
J18
VCCO_0
B10
B16
D7
J19
VCCO_0
K16
J17
VCCO_0
IO_L24P_1
I/O
VCCO_0
D13
F10
V20
W20
U18
V19
R16
T17
T20
T18
U20
U19
P17
P16
R17
R18
R20
R19
P20
P18
N17
N15
IO_L25N_1/A13
IO_L25P_1/A12
IO_L26N_1/A15
IO_L26P_1/A14
IO_L28N_1
H18
H19
G20
H20
H17
G18
F19
F20
F18
G17
E19
E20
F17
E18
D18
D20
F16
G16
C19
C20
B19
B20
DUAL
DUAL
DUAL
DUAL
I/O
VCCO_0
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1
IO_L05P_1
IO_L06N_1
IO_L06P_1
IO_L07N_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1/VREF_1
IO_L10P_1
IO_L12N_1/A3
IO_L12P_1/A2
IO_L28P_1
I/O
IO_L29N_1/A17
IO_L29P_1/A16
IO_L30N_1/A19
IO_L30P_1/A18
IO_L32N_1
DUAL
DUAL
DUAL
DUAL
I/O
I/O
I/O
I/O
IO_L32P_1
I/O
I/O
IO_L33N_1
I/O
I/O
IO_L33P_1
I/O
I/O
IO_L34N_1
I/O
I/O
IO_L34P_1
I/O
I/O
IO_L36N_1/A21
IO_L36P_1/A20
IO_L37N_1/A23
IO_L37P_1/A22
IO_L38N_1/A25
IO_L38P_1/A24
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
VREF
I/O
DUAL
DUAL
102
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 81: Spartan-3A FG400 Pinout(Continued)
Table 81: Spartan-3A FG400 Pinout(Continued)
FG400
FG400
Ball
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IP_1/VREF_1
Ball
N14
P15
P14
M15
M16
M13
M14
L13
L14
K14
K15
J15
J16
J13
J14
H14
H15
G14
G15
D19
H16
K19
N16
T19
V4
Type
VREF
VREF
INPUT
VREF
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
I/O
Bank
2
Pin Name
IO_L09N_2/VS0
Type
DUAL
DUAL
I/O
W6
V6
IP_L04N_1/VREF_1
IP_L04P_1
2
IO_L09P_2/VS1
IO_L10N_2
2
Y7
IP_L11N_1/VREF_1
IP_L11P_1
2
IO_L10P_2
Y6
I/O
2
IO_L11N_2
U9
I/O
IP_L15N_1
2
IO_L11P_2
T9
I/O
IP_L15P_1/VREF_1
IP_L19N_1
2
IO_L12N_2/D6
IO_L12P_2/D7
IO_L13N_2
W8
V7
DUAL
DUAL
I/O
2
IP_L19P_1
2
V9
IP_L23N_1
2
IO_L13P_2
V8
I/O
IP_L23P_1/VREF_1
IP_L27N_1
2
IO_L14N_2/D4
IO_L14P_2/D5
IO_L15N_2/GCLK13
IO_L15P_2/GCLK12
IO_L16N_2/GCLK15
IO_L16P_2/GCLK14
IO_L17N_2/GCLK1
IO_L17P_2/GCLK0
IO_L18N_2/GCLK3
IO_L18P_2/GCLK2
IO_L19N_2
T10
U10
Y9
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
2
IP_L27P_1
2
IP_L31N_1
2
W9
W10
V10
V11
Y11
V12
U11
R12
T12
W12
Y12
W13
Y13
V13
U13
IP_L31P_1/VREF_1
IP_L35N_1
2
2
IP_L35P_1
2
IP_L39N_1
2
IP_L39P_1/VREF_1
VCCO_1
2
2
VCCO_1
2
VCCO_1
2
IO_L19P_2
I/O
VCCO_1
2
IO_L20N_2/MOSI/CSI_B
IO_L20P_2
DUAL
I/O
VCCO_1
2
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2
2
IO_L21N_2
I/O
U4
2
IO_L21P_2
I/O
Y2
2
IO_L22N_2/DOUT
IO_L22P_2/AWAKE
DUAL
W3
W4
Y3
PWR
MGMT
2
2
2
2
2
2
2
2
2
2
2
2
IO_L23N_2
R13
T13
W14
Y14
T14
V14
V15
Y15
T15
U15
W16
I/O
I/O
IO_L03P_2
I/O
IO_L23P_2
IO_L04N_2
R7
I/O
IO_L24N_2/D3
IO_L24P_2/INIT_B
IO_L25N_2
DUAL
DUAL
I/O
IO_L04P_2
T6
I/O
IO_L05N_2
U5
I/O
IO_L05P_2
V5
I/O
IO_L25P_2
I/O
IO_L06N_2
U6
I/O
IO_L26N_2/D1
IO_L26P_2/D2
IO_L27N_2
DUAL
DUAL
I/O
IO_L06P_2
T7
I/O
IO_L07N_2/VS2
IO_L07P_2/RDWR_B
IO_L08N_2
U7
DUAL
DUAL
I/O
T8
IO_L27P_2
I/O
Y5
IO_L28N_2
I/O
IO_L08P_2
Y4
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
103
Pinout Descriptions
Table 81: Spartan-3A FG400 Pinout(Continued)
Table 81: Spartan-3A FG400 Pinout(Continued)
FG400
FG400
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L28P_2
Ball
Y16
U16
V16
Y18
Y17
U17
V17
Y19
W18
P9
Type
I/O
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L08P_3
Ball
H6
G4
F3
F2
E3
H2
G3
G1
F1
H3
J4
Type
I/O
IO_L29N_2
IO_L29P_2
IO_L30N_2
IO_L30P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2/CCLK
IO_L32P_2/D0/DIN/MISO
IP_2
I/O
IO_L09N_3
I/O
I/O
IO_L09P_3
I/O
I/O
IO_L10N_3
I/O
I/O
IO_L10P_3
I/O
I/O
IO_L12N_3
I/O
I/O
IO_L12P_3
I/O
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
IO_L13N_3/VREF_3
IO_L13P_3
VREF
I/O
IO_L14N_3
I/O
IP_2
P12
P13
R8
IO_L14P_3
I/O
IP_2
IO_L16N_3
J2
I/O
IP_2
IO_L16P_3
J3
I/O
IP_2
R10
T11
N9
IO_L17N_3/LHCLK1
IO_L17P_3/LHCLK0
IO_L18N_3/IRDY2/LHCLK3
IO_L18P_3/LHCLK2
IO_L20N_3/LHCLK5
IO_L20P_3/LHCLK4
IO_L21N_3/LHCLK7
IO_L21P_3/TRDY2/LHCLK6
IO_L22N_3
K2
J1
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
IP_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
VCCO_2
L3
N12
P8
K3
L5
P10
P11
R14
R11
U8
K4
M1
L1
M3
M2
M5
M4
N2
N1
N4
N3
R1
P1
P4
P3
R3
R2
T2
T1
R4
T3
U3
VCCO_2
IO_L22P_3/VREF_3
IO_L24N_3
VREF
I/O
VCCO_2
U14
W5
W11
W17
D3
VCCO_2
IO_L24P_3
I/O
VCCO_2
IO_L25N_3
I/O
VCCO_2
IO_L25P_3
I/O
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L26N_3
I/O
D4
I/O
IO_L26P_3
I/O
C2
I/O
IO_L28N_3
I/O
B1
I/O
IO_L28P_3
I/O
D2
I/O
IO_L29N_3
I/O
C1
I/O
IO_L29P_3
I/O
E1
I/O
IO_L30N_3
I/O
D1
I/O
IO_L30P_3
I/O
G5
I/O
IO_L32N_3
I/O
F4
I/O
IO_L32P_3/VREF_3
IO_L33N_3
VREF
I/O
J5
I/O
J6
I/O
IO_L33P_3
I/O
H4
I/O
IO_L34N_3
I/O
104
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 81: Spartan-3A FG400 Pinout(Continued)
Table 81: Spartan-3A FG400 Pinout(Continued)
FG400
FG400
Ball
Bank
Pin Name
IO_L34P_3
Ball
U1
T4
Type
I/O
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E12
F15
G2
3
IO_L36N_3
IO_L36P_3
IO_L37N_3
IO_L37P_3
IO_L38N_3
IO_L38P_3
IP_3
I/O
3
R5
V2
V1
W2
W1
H7
G6
G7
J7
I/O
3
I/O
G19
H8
3
I/O
3
I/O
H13
J9
3
I/O
3
INPUT
VREF
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
GND
J11
K1
3
IP_L04N_3/VREF_3
IP_L04P_3
IP_L11N_3/VREF_3
IP_L11P_3
IP_L15N_3
IP_L15P_3
IP_L19N_3
IP_L19P_3
IP_L23N_3
IP_L23P_3
IP_L27N_3
IP_L27P_3
IP_L31N_3
IP_L31P_3
IP_L35N_3
IP_L35P_3
IP_L39N_3/VREF_3
IP_L39P_3
VCCO_3
3
K10
K12
K17
L4
3
3
J8
3
K7
K8
K5
K6
L6
3
L9
3
L11
L20
M10
M12
N8
3
3
3
3
L7
M7
M8
N7
M6
N6
P5
P7
P6
E2
H5
L2
3
N11
N13
P2
3
3
3
P19
R6
3
3
R9
3
T16
U12
V3
3
3
VCCO_3
3
VCCO_3
V18
W7
W15
Y1
3
VCCO_3
N5
U2
A1
A11
A20
B6
B14
C3
C18
D9
E5
3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Y10
Y20
GND
GND
GND
GND
PWR
MGMT
VCCAUX SUSPEND
R15
GND
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
W19
D5
CONFIG
CONFIG
JTAG
GND
GND
GND
GND
A19
F5
GND
GND
JTAG
GND
GND
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
105
Pinout Descriptions
Table 81: Spartan-3A FG400 Pinout(Continued)
FG400
Bank
Pin Name
Ball
E17
E4
Type
VCCAUX TDO
JTAG
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
A13
E16
H1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
K13
L8
N20
T5
Y8
J10
J12
K9
K11
L10
L12
M9
M11
N10
User I/Os by Bank
Table 82 indicates how the 311 available user-I/O pins are
distributed between the four I/O banks on the FG400
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 82: User I/Os Per Bank for the XC3S400A and XC3S700A in the FG400 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
I/O
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
77
79
50
12
1
6
8
Right
Bottom
Left
21
12
30
21
0
8
76
35
6
6
8
79
49
16
6
8
TOTAL
311
155
46
52
26
32
Footprint Migration Differences
The XC3S400A and XC3S700A FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S400A and XC3S700A FPGAs without
further consideration.
106
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FG400 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
Left Half of FG400
Package (Top View)
I/O
L32P_0
VREF_0
I/O
L18N_0
GCLK11 GCLK10
I/O
L18P_0
I/O
L16P_0
GCLK6
I/O
L30P_0
I/O
L29P_0
I/O
L26P_0
I/O
L25P_0
I/O
L24N_0
GND
A
B
C
D
E
F
I/O
L32N_0
PUDC_B
I/O
L02P_3
I/O
L30N_0
I/O
L26N_0
I/O
L24P_0
I/O
L20P_0
I/O
L19P_0
VCCO_0
VCCO_0
GND
I/O: Unrestricted,
general-purpose user I/O
155
I/O
L16N_0
GCLK7
I/O
L03P_3
I/O
L02N_3
I/O
L29N_0
I/O
L28P_0
I/O
L25N_0
I/O
L21P_0
I/O
L20N_0
I/O
L19N_0
GND
INPUT: Unrestricted,
general-purpose input pin
I/O
L17P_0
GCLK8
46
I/O
L05P_3
I/O
L03N_3
I/O
L01N_3
I/O
L01P_3
I/O
L28N_0
I/O
L21N_0
VCCO_0
GND
PROG_B
DUAL: Configuration pins,
51
I/O
L17N_0
GCLK9
I/O
L05N_3
I/O
L10P_3
I/O
L31P_0
I/O
L27P_0
I/O
L23P_0
I/O
L22P_0
VCCO_3
TMS
GND
then possible user I/O
VREF: User I/O or input
voltage reference for bank
I/O
L22N_0
VREF_0
I/O
L13P_3
I/O
L10N_3
I/O
L09P_3
I/O
L06P_3
I/O
L31N_0
I/O
L27N_0
I/O
L23N_0
26
VCCO_0
TDI
I/O
INPUT
L04N_3
VREF_3
CLK: User I/O, input, or
I/O
I/O
I/O
INPUT
GND
INPUT INPUT INPUT
L13N_3
G
H
J
clock buffer input
L12P_3
L09N_3
L06N_3
L04P_3
32
VREF_3
I/O
L12N_3
I/O
L14N_3
I/O
L08N_3
I/O
L08P_3
VCCAUX
VCCO_3
INPUT
GND
INPUT INPUT
GND VCCINT
VCCINT GND
GND VCCINT
VCCINT GND
CONFIG: Dedicated
configuration pins
2
I/O
L17P_3
LHCLK0
INPUT
L11N_3
VREF_3
I/O
L16N_3
I/O
L16P_3
I/O
L14P_3
I/O
L07N_3
I/O
L07P_3
INPUT
L11P_3
JTAG: Dedicated JTAG
port pins
4
I/O
L17N_3
I/O
L18P_3
I/O
L20P_3
INPUT INPUT INPUT INPUT
GND
K
L
L19N_3
L19P_3
L15N_3
L15P_3
SUSPEND: Dedicated
LHCLK1 LHCLK2 LHCLK4
SUSPEND and
2
I/O
L21P_3
TRDY2
LHCLK6
I/O
L18N_3
IRDY2
LHCLK3
dual-purpose AWAKE
I/O
L20N_3
LHCLK5
INPUT INPUT
L23N_3
VCCO_3
VCCAUX
Power Management pins
GND
L23P_3
GND: Ground
I/O
L21N_3
LHCLK7 VREF_3
I/O
L22P_3
I/O
L22N_3
I/O
L24P_3
I/O
L24N_3
INPUT INPUT INPUT
L31P_3
43
M
N
P
R
T
L27N_3
L27P_3
I/O
L25P_3
I/O
L25N_3
I/O
L26P_3
I/O
L26N_3
INPUT INPUT
L35N_3
INPUT
VCCINT
VREF_2
VCCO: Output voltage
supply for bank
VCCO_3
GND
L31N_3
22
INPUT
L39N_3
VREF_3
I/O
L28P_3
I/O
L29P_3
I/O
L29N_3
INPUT INPUT
INPUT
VREF_2
INPUT
INPUT
GND
VCCINT: Internal core
supply voltage (+1.2V)
L35P_3
L39P_3
VREF_2
9
I/O
L28N_3
I/O
L30P_3
I/O
L30N_3
I/O
L33N_3
I/O
L36P_3
I/O
L04N_2
GND
INPUT
GND
INPUT
VCCAUX: Auxiliary supply
voltage
8
I/O
L32P_3
VREF_3
I/O
I/O
L14N_2
D4
I/O
L32N_3
I/O
L33P_3
I/O
L36N_3
I/O
L04P_2
I/O
L06P_2
I/O
L11P_2
VCCAUX
L07P_2
RDWR_B
I/O
L01P_2
M1
I/O
L07N_2
VS2
I/O
L14P_2
D5
I/O
I/O
I/O
I/O
I/O
VCCO_3
VCCO_2
U
V
W
Y
L34P_3
L34N_3
L05N_2
L06N_2
L11N_2
I/O
L01N_2
M0
I/O
L09P_2
VS1
I/O
L12P_2
D7
I/O
L16P_2
GCLK14
I/O
L37P_3
I/O
L37N_3
I/O
L05P_2
I/O
L13P_2
I/O
L13N_2
GND
I/O
L02P_2
M2
I/O
L09N_2
VS0
I/O
L12N_2
D6
I/O
L15P_2
I/O
L16N_2
GCLK12 GCLK15
I/O
L38P_3
I/O
L38N_3
I/O
L03N_2
VCCO_2
GND
I/O
L02N_2
CSO_B
I/O
L15N_2
GCLK13
I/O
L03P_2
I/O
L08P_2
I/O
L08N_2
I/O
L10P_2
I/O
L10N_2
VCCAUX
GND
GND
Bank 2
DS529-4_03_011608
Figure 24: FG400 Package Footprint (Top View)
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
107
Pinout Descriptions
Bank 0
11
12
13
14
15
16
17
18
19
20
Right Half of FG400
Package (Top View)
I/O
I/O
I/O
I/O
I/O
I/O
VCCAUX
GND
TCK
GND
A
B
C
D
E
F
L13N_0
L07N_0
L08N_0
L05N_0
L04N_0
L01N_0
I/O
L04P_0
VREF_0
I/O
L38N_1
A25
I/O
L38P_1
A24
I/O
L14P_0
I/O
L13P_0
I/O
L11P_0
I/O
L08P_0
I/O
L01P_0
VCCO_0
GND
I/O
L10N_0
VREF_0
I/O
L37N_1
A23
I/O
L37P_1
A22
I/O
L14N_0
I/O
L11N_0
I/O
L07P_0
I/O
L06N_0
I/O
L05P_0
I/O
L02N_0
GND
I/O
L15P_0
GCLK4
I/O
L02P_0
VREF_0
I/O
L12P_0
I/O
L10P_0
I/O
L06P_0
I/O
L03P_0
I/O
L34N_1
I/O
L34P_1
VCCO_0
VCCO_1
I/O
L15N_0
GCLK5
I/O
L09P_0
I/O
L03N_0
I/O
L33P_1
I/O
L32N_1
I/O
L32P_1
VCCAUX
GND
INPUT
INPUT
TDO
I/O
L36N_1
A21
I/O
L30N_1
A19
I/O
L29N_1
A17
I/O
L29P_1
A16
I/O
L12N_0
I/O
L09N_0
I/O
L33N_1
INPUT
GND
INPUT
L39P_1
VREF_1
I/O
L36P_1
A20
I/O
L30P_1
A18
I/O
L26N_1
A15
INPUT
INPUT
I/O
INPUT INPUT
GND
G
H
J
VREF_0
L39N_1
L28P_1
I/O
L25N_1
A13
I/O
L25P_1
A12
I/O
L26P_1
A14
INPUT INPUT
I/O
L28N_1
VCCO_1
INPUT INPUT
GND VCCINT
VCCINT GND
GND VCCINT
VCCINT GND
GND
L35N_1
L35P_1
INPUT
L31P_1
VREF_1
I/O
L22N_1
A11
I/O
L22P_1
A10
I/O
L21N_1
RHCLK7
INPUT
L31N_1
INPUT INPUT
L27N_1
I/O
L24P_1
L27P_1
I/O
L21P_1
IRDY1
INPUT
L23P_1
VREF_1
I/O
L20P_1
RHCLK4
INPUT
L23N_1
I/O
L24N_1
VCCAUX
VCCO_1
GND
K
L
RHCLK6
I/O
L18N_1
TRDY1
RHCLK3
I/O
L16P_1
A8
I/O
L16N_1
A9
I/O
L20N_1
RHCLK5
I/O
L18P_1
RHCLK2
INPUT INPUT
GND
L19N_1
L19P_1
INPUT INPUT
I/O
L14P_1
A6
I/O
L14N_1
A7
I/O
L17P_1
I/O
L17N_1
RHCLK0 RHCLK1
INPUT
L15N_1
INPUT
L11P_1
L15P_1
L11N_1
M
N
P
R
T
VREF_1 VREF_1
I/O
INPUT
L12P_1
I/O
L12N_1
A3
I/O
L13P_1
A4
I/O
INPUT
GND
VCCO_1
VCCAUX
L13N_1
GND
VREF_2
VREF_1
A2
A5
INPUT
INPUT
I/O
L10N_1
VREF_1
INPUT
VREF_2
I/O
L07P_1
I/O
L07N_1
I/O
L10P_1
INPUT INPUT
GND
L04N_1
L04P_1
VREF_1
I/O
L03N_1
A1
I/O
I/O
INPUT
L23N_2 VREF_2
I/O
L08N_1
I/O
L08P_1
I/O
L09P_1
I/O
L09N_1
VCCO_2
L19N_2
SUSPEND
I/O
L03P_1
A0
I/O
L19P_2
I/O
L23P_2
I/O
L25N_2
I/O
L27N_2
I/O
L05P_1
I/O
L05N_1
VCCO_1
INPUT
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCO_2
GND
L18P_2
L22P_2
L02N_1
U
V
W
Y
L27P_2
L29N_2
L31N_2
L06P_1
L06N_1
GCLK2
AWAKE
LDC0
I/O
L17N_2
GCLK1
I/O
L18N_2
GCLK3
I/O
L22N_2
DOUT
I/O
L26N_2
D1
I/O
L02P_1
LDC1
I/O
L01N_1
LDC2
I/O
L25P_2
I/O
L29P_2
I/O
L31P_2
GND
I/O
L20N_2
MOSI
I/O
L32P_2
D0
I/O
L24N_2
D3
I/O
L01P_1
HDC
I/O
L21N_2
I/O
L28N_2
VCCO_2
VCCO_2
GND
DONE
CSI_B
DIN/MISO
I/O
L17P_2
GCLK0
I/O
L24P_2
INIT_B
I/O
L26P_2
D2
I/O
L32N_2
CCLK
I/O
L20P_2
I/O
L21P_2
I/O
L28P_2
I/O
L30P_2
I/O
L30N_2
GND
Bank 2
DS529-4_04_012009
108
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports both
the XC3S700A and the XC3S1400A FPGAs. There are
three pinout differences, as described in Table 86.
Table 83: Spartan-3A FG484 Pinout(Continued)
FG484
Ball
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L11P_0
Type
I/O
Table 83 lists all the FG484 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
D15
A15
A16
A14
B15
E13
F13
C13
D13
A13
B13
E12
C12
A11
A12
C11
B11
E11
D11
C10
A10
A8
IO_L12N_0/VREF_0
IO_L12P_0
VREF
I/O
IO_L13N_0
I/O
IO_L13P_0
I/O
The shaded rows indicate pinout differences between the
XC3S700A and the XC3S1400A FPGAs. The XC3S700A
has three unconnected balls, indicated as N.C. (No
Connection) in Table 83 and with the black diamond
character () in Table 83 and Figure 25.
IO_L14N_0
I/O
IO_L14P_0
I/O
IO_L15N_0
I/O
IO_L15P_0
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
IO_L16N_0
I/O
IO_L16P_0
I/O
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L17N_0/GCLK5
IO_L17P_0/GCLK4
IO_L18N_0/GCLK7
IO_L18P_0/GCLK6
IO_L19N_0/GCLK9
IO_L19P_0/GCLK8
IO_L20N_0/GCLK11
IO_L20P_0/GCLK10
IO_L21N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
Pinout Table
Table 83: Spartan-3A FG484 Pinout
FG484
Bank
0
Pin Name
IO_L01N_0
Ball
D18
E17
C19
D19
A20
B20
F15
E15
A18
C18
A19
B19
C17
D17
C16
D16
E14
C14
A17
B17
C15
Type
I/O
0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0
IO_L06P_0/VREF_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
I/O
0
I/O
IO_L21P_0
I/O
0
VREF
I/O
IO_L22N_0
I/O
0
IO_L22P_0
A9
I/O
0
I/O
IO_L23N_0
E10
D10
C9
I/O
0
I/O
IO_L23P_0
I/O
0
I/O
IO_L24N_0/VREF_0
IO_L24P_0
VREF
I/O
0
I/O
B9
0
I/O
IO_L25N_0
C8
I/O
0
I/O
IO_L25P_0
B8
I/O
0
VREF
I/O
IO_L26N_0
A6
I/O
0
IO_L26P_0
A7
I/O
0
I/O
IO_L27N_0
C7
I/O
0
I/O
IO_L27P_0
D7
I/O
0
I/O
IO_L28N_0
A5
I/O
0
I/O
IO_L28P_0
B6
I/O
0
I/O
IO_L29N_0
D6
I/O
0
I/O
IO_L29P_0
C6
I/O
0
I/O
IO_L30N_0
D8
I/O
0
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
109
Pinout Descriptions
Table 83: Spartan-3A FG484 Pinout(Continued)
Table 83: Spartan-3A FG484 Pinout(Continued)
FG484
FG484
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Pin Name
IO_L30P_0
Ball
Type
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L01P_1/HDC
Ball
AA22
W20
W19
T18
T17
W21
Y22
V20
V19
V22
W22
U21
U22
U19
U20
T22
T20
T19
R20
R22
R21
P22
P20
P18
R19
N21
N22
N19
N20
N17
N18
L22
Type
DUAL
DUAL
DUAL
DUAL
DUAL
I/O
E9
IO_L31N_0
IO_L31P_0
IO_L32N_0
IO_L32P_0
IO_L33N_0
IO_L33P_0
IO_L34N_0
IO_L34P_0
IO_L35N_0
IO_L35P_0
IO_L36N_0/PUDC_B
IO_L36P_0/VREF_0
IP_0
B4
I/O
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1
A4
I/O
D5
I/O
C5
I/O
B3
I/O
A3
I/O
IO_L05P_1
I/O
F8
I/O
IO_L06N_1
I/O
E7
I/O
IO_L06P_1
I/O
E6
I/O
IO_L07N_1
I/O
F7
I/O
IO_L07P_1
I/O
A2
DUAL
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
IO_L09N_1
I/O
B2
IO_L09P_1
I/O
E16
E8
IO_L10N_1
I/O
IP_0
IO_L10P_1
I/O
IP_0
F10
F12
F16
G10
G11
G12
G13
G14
G15
G16
G7
IO_L11N_1
I/O
IP_0
IO_L11P_1
I/O
IP_0
IO_L13N_1
I/O
IP_0
IO_L13P_1
I/O
IP_0
IO_L14N_1
I/O
IP_0
IO_L14P_1
I/O
IP_0
IO_L15N_1/VREF_1
IO_L15P_1
VREF
I/O
IP_0
IP_0
IO_L17N_1/A3
IO_L17P_1/A2
IO_L18N_1/A5
IO_L18P_1/A4
IO_L19N_1/A7
IO_L19P_1/A6
IO_L20N_1/A9
IO_L20P_1/A8
IO_L21N_1/RHCLK1
IO_L21P_1/RHCLK0
IO_L22N_1/TRDY1/RHCLK3
IO_L22P_1/RHCLK2
IO_L24N_1/RHCLK5
IO_L24P_1/RHCLK4
IO_L25N_1/RHCLK7
IO_L25P_1/IRDY1/RHCLK6
IO_L26N_1/A11
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
IP_0
IP_0
IP_0
G9
IP_0
H10
H13
H14
G8
IP_0
IP_0
IP_0/VREF_0
IP_0/VREF_0
IP_0/VREF_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
VCCO_0
IO_L01N_1/LDC2
H12
H9
M22
L20
B10
B14
B18
B5
L21
M20
M18
K19
K20
J22
F14
F9
Y21
110
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 83: Spartan-3A FG484 Pinout(Continued)
Table 83: Spartan-3A FG484 Pinout(Continued)
FG484
FG484
Ball
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L26P_1/A10
Ball
K22
L19
L18
J20
Type
DUAL
I/O
Bank
Pin Name
IP_L23P_1
Type
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
VREF
INPUT
INPUT
VREF
1
1
1
1
1
1
1
1
1
1
1
1
1
M17
L16
M15
K16
L15
K15
K14
H18
H17
J15
IO_L28N_1
IP_L27N_1
IO_L28P_1
I/O
IP_L27P_1/VREF_1
IP_L31N_1
IO_L29N_1/A13
IO_L29P_1/A12
IO_L30N_1/A15
IO_L30P_1/A14
IO_L32N_1
DUAL
DUAL
DUAL
DUAL
I/O
J21
IP_L31P_1
G22
H22
K18
K17
H20
H21
F21
F22
G20
G19
H19
J18
IP_L35N_1
IP_L35P_1/VREF_1
IP_L39N_1
IO_L32P_1
I/O
IP_L39P_1
IO_L33N_1/A17
IO_L33P_1/A16
IO_L34N_1/A19
IO_L34P_1/A18
IO_L36N_1
DUAL
DUAL
DUAL
DUAL
I/O
IP_L43N_1/VREF_1
IP_L43P_1
J16
IP_L47N_1
H15
H16
IP_L47P_1/VREF_1
PWR
MGMT
VCCAUX SUSPEND
U18
IO_L36P_1
I/O
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VCCO_1
E21
J17
K21
P17
P21
V21
W5
V6
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
I/O
IO_L37N_1
I/O
VCCO_1
IO_L37P_1
I/O
VCCO_1
IO_L38N_1
F20
E20
F18
F19
D22
E22
D20
D21
C21
C22
B21
B22
G17
G18
R16
R15
P16
P15
R18
R17
N16
N15
M16
I/O
VCCO_1
IO_L38P_1
I/O
VCCO_1
IO_L40N_1
I/O
VCCO_1
IO_L40P_1
I/O
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2
IO_L03P_2
IO_L04N_2
IO_L04P_2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2/VS2
IO_L09P_2/RDWR_B
IO_L10N_2
IO_L41N_1
I/O
IO_L41P_1
I/O
Y4
IO_L42N_1
I/O
W4
AA3
AB2
AA4
AB3
Y5
IO_L42P_1
I/O
IO_L44N_1/A21
IO_L44P_1/A20
IO_L45N_1/A23
IO_L45P_1/A22
IO_L46N_1/A25
IO_L46P_1/A24
IP_L04N_1/VREF_1
IP_L04P_1
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
INPUT
INPUT
INPUT
VREF
INPUT
VREF
INPUT
INPUT
I/O
I/O
I/O
I/O
W6
AB5
AB4
Y6
I/O
I/O
I/O
I/O
IP_L08N_1
W7
AB6
AA6
W9
V9
I/O
IP_L08P_1
I/O
IP_L12N_1/VREF_1
IP_L12P_1
I/O
DUAL
DUAL
I/O
IP_L16N_1/VREF_1
IP_L16P_1
AB7
IP_L23N_1
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
111
Pinout Descriptions
Table 83: Spartan-3A FG484 Pinout(Continued)
Table 83: Spartan-3A FG484 Pinout(Continued)
FG484
FG484
Bank
2
Pin Name
IO_L10P_2
Ball
Type
I/O
Bank
2
Pin Name
IO_L30N_2
Ball
V15
V14
V16
W16
AA19
AB19
V17
W18
W17
Y18
AA21
AB21
AA20
AB20
P12
R10
R11
R9
Type
I/O
Y7
2
IO_L11N_2/VS0
IO_L11P_2/VS1
IO_L12N_2
Y8
DUAL
DUAL
I/O
2
IO_L30P_2
IO_L31N_2
IO_L31P_2
IO_L32N_2
IO_L32P_2
IO_L33N_2
IO_L33P_2
IO_L34N_2
IO_L34P_2
IO_L35N_2
IO_L35P_2
IO_L36N_2/CCLK
IO_L36P_2/D0/DIN/MISO
IP_2
I/O
2
W8
2
I/O
2
AB8
AA8
Y10
V10
AB9
Y9
2
I/O
2
IO_L12P_2
I/O
2
I/O
2
IO_L13N_2
I/O
2
I/O
2
IO_L13P_2
I/O
2
I/O
2
IO_L14N_2/D6
IO_L14P_2/D7
IO_L15N_2
DUAL
DUAL
I/O
2
I/O
2
2
I/O
2
AB10
AA10
AB11
Y11
V11
U11
Y12
W12
AB12
AA12
U12
V12
Y13
AB13
AB14
AA14
Y14
W13
2
I/O
2
IO_L15P_2
I/O
2
I/O
2
IO_L16N_2/D4
IO_L16P_2/D5
IO_L17N_2/GCLK13
IO_L17P_2/GCLK12
IO_L18N_2/GCLK15
IO_L18P_2/GCLK14
IO_L19N_2/GCLK1
IO_L19P_2/GCLK0
IO_L20N_2/GCLK3
IO_L20P_2/GCLK2
IO_L21N_2
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
2
I/O
2
2
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
2
2
2
2
2
2
IP_2
2
2
IP_2
2
2
IP_2
2
2
IP_2
T13
2
2
IP_2
T14
2
2
IP_2
T9
2
2
IP_2
U10
U15
2
IO_L21P_2
I/O
2
IP_2
2
IO_L22N_2/MOSI/CSI_B
IO_L22P_2
DUAL
I/O
XC3S1400A: IP_2
XC3S700A: N.C. (◆)
2
2
U16
U7
INPUT
INPUT
2
XC3S1400A: IP_2
XC3S700A: N.C. (◆)
2
IO_L23N_2
I/O
2
IO_L23P_2
I/O
2
2
2
2
2
2
2
2
2
2
IP_2
U8
V7
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
IO_L24N_2/
DOUT
2
2
AA15
AB15
DUAL
IP_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
R12
R13
R14
T10
T11
T15
T16
T7
PWR
MGMT
IO_L24P_2/AWAKE
2
2
2
2
2
2
2
2
2
2
IO_L25N_2
Y15
W15
U13
I/O
I/O
IO_L25P_2
IO_L26N_2/D3
IO_L26P_2/INIT_B
IO_L27N_2
DUAL
DUAL
I/O
V13
Y16
IO_L27P_2
AB16
Y17
I/O
IO_L28N_2/D1
IO_L28P_2/D2
IO_L29N_2
DUAL
DUAL
I/O
XC3S1400A: IP_2/VREF_2
XC3S700A: N.C. (◆)
2
T8
VREF
AA17
AB18
AB17
2
2
IP_2/VREF_2
VCCO_2
V8
VREF
VCCO
IO_L29P_2
I/O
AA13
112
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 83: Spartan-3A FG484 Pinout(Continued)
Table 83: Spartan-3A FG484 Pinout(Continued)
FG484
FG484
Ball
Bank
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
Ball
AA18
AA5
AA9
U14
U9
D2
C1
C2
B1
E4
D3
G5
G6
E1
D1
E3
F4
Type
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L22P_3/LHCLK2
IO_L24N_3/LHCLK5
IO_L24P_3/LHCLK4
IO_L25N_3/LHCLK7
IO_L25P_3/TRDY2/LHCLK6
IO_L26N_3
Type
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
K1
M2
M1
M4
M3
N3
N1
P2
P1
P5
P3
N4
M5
R2
R1
R4
R3
T4
IO_L01N_3
IO_L01P_3
I/O
IO_L26P_3/VREF_3
IO_L28N_3
VREF
I/O
IO_L02N_3
I/O
IO_L02P_3
I/O
IO_L28P_3
I/O
IO_L03N_3
I/O
IO_L29N_3
I/O
IO_L03P_3
I/O
IO_L29P_3
I/O
IO_L05N_3
I/O
IO_L30N_3
I/O
IO_L05P_3
I/O
IO_L30P_3
I/O
IO_L06N_3
I/O
IO_L32N_3
I/O
IO_L06P_3
I/O
IO_L32P_3
I/O
IO_L07N_3
I/O
IO_L33N_3
I/O
IO_L07P_3
I/O
IO_L33P_3
I/O
IO_L08N_3
G4
F3
I/O
IO_L34N_3
I/O
IO_L08P_3
I/O
IO_L34P_3
R5
T3
I/O
IO_L09N_3
H6
H5
J5
I/O
IO_L36N_3
I/O
IO_L09P_3
I/O
IO_L36P_3/VREF_3
IO_L37N_3
T1
VREF
I/O
IO_L10N_3
I/O
U2
U1
V3
V1
U5
T5
IO_L10P_3
K6
F1
I/O
IO_L37P_3
I/O
IO_L12N_3
I/O
IO_L38N_3
I/O
IO_L12P_3
F2
I/O
IO_L38P_3
I/O
IO_L13N_3
G1
G3
H3
H4
H1
H2
J1
I/O
IO_L40N_3
I/O
IO_L13P_3
I/O
IO_L40P_3
I/O
IO_L14N_3
I/O
IO_L41N_3
U4
U3
W2
W1
W3
V4
Y2
Y1
AA2
AA1
J8
I/O
IO_L14P_3
I/O
IO_L41P_3
I/O
IO_L16N_3
I/O
IO_L42N_3
I/O
IO_L16P_3
I/O
IO_L42P_3
I/O
IO_L17N_3/VREF_3
IO_L17P_3
VREF
I/O
IO_L43N_3
I/O
J3
IO_L43P_3
I/O
IO_L18N_3
K4
K5
K2
K3
L3
I/O
IO_L44N_3
I/O
IO_L18P_3
I/O
IO_L44P_3
I/O
IO_L20N_3
I/O
IO_L45N_3
I/O
IO_L20P_3
I/O
IO_L45P_3
I/O
IO_L21N_3/LHCLK1
IO_L21P_3/LHCLK0
IO_L22N_3/IRDY2/LHCLK3
LHCLK
LHCLK
LHCLK
IP_3/VREF_3
IP_3/VREF_3
IP_L04N_3/VREF_3
VREF
VREF
VREF
L5
R6
H7
L1
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
113
Pinout Descriptions
Table 83: Spartan-3A FG484 Pinout(Continued)
Table 83: Spartan-3A FG484 Pinout(Continued)
FG484
FG484
Bank
Pin Name
IP_L04P_3
Ball
Type
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Ball
F17
F6
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
H8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
IP_L11N_3
IP_L11P_3
IP_L15N_3/VREF_3
IP_L15P_3
IP_L19N_3
IP_L19P_3
IP_L23N_3
IP_L23P_3
IP_L27N_3
IP_L27P_3
IP_L31N_3
IP_L31P_3
IP_L35N_3
IP_L35P_3
IP_L39N_3
IP_L39P_3
IP_L46N_3/VREF_3
IP_L46P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
K8
3
J7
G2
3
3
L8
G21
J11
J13
J14
J19
J4
K7
3
M8
L7
3
3
M6
M7
N9
3
3
J9
3
N8
K10
K12
L11
L13
L17
L2
3
N5
3
N6
3
P8
3
N7
3
R8
3
P7
L6
3
T6
L9
3
R7
M10
M12
M14
M21
N11
N13
P10
P14
P19
P4
3
E2
3
J2
3
J6
3
N2
3
P6
3
V2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
A22
AA11
AA16
AA7
AB1
AB22
B12
B16
B7
GND
GND
GND
GND
GND
P9
GND
GND
T12
T2
GND
GND
GND
GND
T21
U17
U6
GND
GND
GND
GND
GND
GND
W10
W14
Y20
Y3
GND
C20
C3
GND
GND
GND
GND
D14
D9
GND
GND
GND
PWR
MGMT
VCCAUX SUSPEND
U18
GND
F11
GND
114
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 83: Spartan-3A FG484 Pinout(Continued)
FG484
Bank
Pin Name
Ball
Y19
C4
Type
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
A21
F5
VCCAUX TDI
JTAG
VCCAUX TDO
E19
D4
JTAG
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
D12
E18
E5
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
H11
L4
M19
P11
V18
V5
W11
J10
J12
K11
K13
K9
L10
L12
L14
M11
M13
M9
N10
N12
N14
P13
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
115
Pinout Descriptions
User I/Os by Bank
Table 84 and Table 85 indicate how the user-I/O pins are
distributed between the four I/O banks on the FG484
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 84: User I/Os Per Bank for the XC3S700A in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
58
INPUT
17
DUAL
1
VREF
CLK
8
Top
0
1
2
3
92
94
8
8
Right
Bottom
Left
33
15
30
21
0
8
92
43
11
9
8
94
61
17
8
8
TOTAL
372
195
60
52
33
32
Table 85: User I/Os Per Bank for the XC3S1400A in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
58
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
92
94
17
15
13
17
62
8
8
Right
Bottom
Left
33
30
21
0
8
95
43
10
8
8
94
61
8
TOTAL
375
195
52
34
32
Footprint Migration Differences
Table 86 summarizes any footprint and functionality
differences between the XC3S700A and the XC3S1400A
FPGAs that might affect easy migration between devices
available in the FG484 package. There are three such balls.
All other pins not listed in Table 86 unconditionally migrate
between Spartan-3A devices available in the FG484
package.
The arrows indicate the direction for easy migration.
Table 86: FG484 Footprint Migration Differences
Pin
T8
Bank
XC3S700A
N.C.
Migration
XC3S1400A
INPUT/VREF
INPUT
2
2
2
Æ
Æ
Æ
3
U7
N.C.
N.C.
U16
INPUT
DIFFERENCES
Legend:
This pin can unconditionally migrate from the device
on the left to the device on the right. Migration in the
other direction is possible depending on how the pin is
configured for the device on the right.
Æ
116
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FG484 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
Left Half of FG484
Package (Top View)
I/O
I/O
L18N_0
GCLK7
I/O
I/O
I/O
I/O
I/O
I/O
L22N_0
I/O
L22P_0
I/O
L21P_0
GND
A
B
C
D
E
F
L36N_0
L33P_0
L31P_0
L28N_0
L26N_0
L26P_0
PUDC_B
I/O
L36P_0
VREF_0
I/O
L19P_0
GCLK8
I/O
L02P_3
I/O
L33N_0
I/O
L31N_0
I/O
L28P_0
I/O
L25P_0
I/O
L24P_0
VCCO_0
VCCO_0
GND
I/O: Unrestricted,
general-purpose user I/O
I/O
L24N_0
VREF_0
I/O
L19N_0
GCLK9
195
I/O
L01P_3
I/O
L02N_3
I/O
L32P_0
I/O
L29P_0
I/O
L27N_0
I/O
L25N_0
I/O
L21N_0
GND
PROG_B
I/O
L20P_0
GCLK10
INPUT: Unrestricted,
general-purpose input pin
I/O
L06P_3
I/O
L01N_3
I/O
L03P_3
I/O
L32N_0
I/O
L29N_0
I/O
L27P_0
I/O
L30N_0
I/O
L23P_0
60-
62
TMS
GND
I/O
L20N_0
GCLK11
I/O
L06N_3
I/O
L07N_3
I/O
L03N_3
I/O
L35N_0
I/O
L34P_0
I/O
L30P_0
I/O
L23N_0
VCCO_3
VCCAUX
INPUT
DUAL: Configuration pins,
then possible user I/O
51
I/O
L12N_3
I/O
L12P_3
I/O
L08P_3
I/O
L07P_3
I/O
L35P_0
I/O
L34N_0
VCCO_0
TDI
GND
INPUT
GND
VREF: User I/O or input
voltage reference for bank
33-
34
I/O
L13N_3
I/O
L13P_3
I/O
L08N_3
I/O
L05N_3
I/O
L05P_3
INPUT
VREF_0
GND
INPUT
INPUT INPUT INPUT
G
H
J
CLK: User I/O, input, or
INPUT
L04N_3
VREF_3
clock buffer input
32
2
I/O
L16N_3
I/O
L16P_3
I/O
L14N_3
I/O
L14P_3
I/O
L09P_3
I/O
L09N_3
INPUT INPUT
L04P_3 VREF_0
VCCAUX
INPUT
I/O
L17N_3
VREF_3
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
I/O
L17P_3
I/O
L10N_3
INPUT INPUT
L11P_3 VREF_3
VCCO_3
VCCO_3
GND
GND VCCINT GND
VCCINT GND VCCINT
GND VCCINT GND
VCCINT GND VCCINT
I/O
L22P_3
LHCLK2
I/O
L20N_3
I/O
L20P_3
I/O
L18N_3
I/O
L18P_3
I/O
L10P_3
INPUT INPUT
K
L
L15P_3
L11N_3
CONFIG: Dedicated
2
4
I/O
L22N_3
IRDY2
LHCLK3
configuration pins
I/O
L21N_3
LHCLK1
I/O
L21P_3
LHCLK0
INPUT
L15N_3
VREF_3
INPUT
L19P_3
VCCAUX
GND
GND
JTAG: Dedicated JTAG port
pins
I/O
L25P_3
TRDY2
LHCLK6
I/O
L24P_3
I/O
L24N_3
LHCLK4 LHCLK5
I/O
L25N_3
LHCLK7
I/O
L30P_3
INPUT INPUT INPUT
M
N
P
R
T
L23N_3
L23P_3
L19N_3
I/O
GND: Ground
I/O
L26N_3
I/O
L30N_3
INPUT INPUT INPUT INPUT INPUT
VCCO_3
L26P_3
VCCINT GND
53
24
15
10
L31N_3
L31P_3
L35P_3
L27P_3
L27N_3
VREF_3
I/O
L28P_3
I/O
L28N_3
I/O
L29P_3
I/O
L29N_3
INPUT INPUT
VCCO_3
VCCAUX
GND
GND
GND
VCCO: Output voltage
supply for bank
L39P_3
L35N_3
I/O
L32P_3
I/O
L32N_3
I/O
L33P_3
I/O
L33N_3
I/O
INPUT INPUT INPUT
INPUT INPUT INPUT
L34P_3 VREF_3 L46P_3
L39N_3
VCCINT: Internal core
supply voltage (+1.2V)
INPUT
I/O
L36P_3
VREF_3
INPUT
L46N_3
VREF_3
I/O
L36N_3
I/O
L34N_3
I/O
L40P_3
INPUT
VREF_2
INPUT INPUT
INPUT
VREF_2
GND
VREF_2 VREF_2
◆
I/O
L17P_2
GCLK12
INPUT
VCCAUX: Auxiliary supply
voltage
I/O
L37P_3
I/O
L37N_3
I/O
L41P_3
I/O
L41N_3
I/O
L40N_3
VCCO_2
GND
INPUT
INPUT
U
V
W
Y
◆
I/O
L01P_2
M1
I/O
L09P_2
RDWR_B
I/O
L17N_2
GCLK13
I/O
L38P_3
I/O
L38N_3
I/O
L43P_3
INPUT
VREF_2
I/O
L13P_2
VCCO_3
VCCAUX
INPUT
N.C.: Not connected
(XC3S700A only)
3
◆
I/O
L02P_2
M2
I/O
L01N_2
M0
I/O
L11P_2
VS1
I/O
L09N_2
VS2
I/O
L42P_3
I/O
L42N_3
I/O
L43N_3
I/O
L05P_2
I/O
L07P_2
VCCAUX
GND
I/O
L02N_2
CSO_B
I/O
L11N_2
VS0
I/O
L14P_2
D7
I/O
L16P_2
D5
I/O
L44P_3
I/O
L44N_3
I/O
L05N_2
I/O
L07N_2
I/O
L10P_2
I/O
L13N_2
GND
A
A
I/O
L45P_3
I/O
L45N_3
I/O
L03N_2
I/O
L04N_2
I/O
L08P_2
I/O
L12P_2
I/O
L15P_2
VCCO_2
VCCO_2
GND
GND
I/O
L14N_2
D6
I/O
L16N_2
D4
A
B
I/O
L03P_2
I/O
L04P_2
I/O
L06P_2
I/O
L06N_2
I/O
L08N_2
I/O
L10N_2
I/O
L12N_2
I/O
L15N_2
GND
Bank 2
DS529-4 01 101106
Figure 25: FG484 Package Footprint (Top View)
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
117
Pinout Descriptions
Bank 0
12
13
14
15
16
17
18
19
20
21
22
Right Half of FG484
Package (Top View)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
GND
L18P_0
L12N_0
A
B
C
D
E
F
L16N_0
L13N_0
L12P_0
L10N_0
L05N_0
L06N_0
L03N_0
GCLK6
VREF_0
I/O
L06P_0
VREF_0
I/O
L45N_1
A23
I/O
L45P_1
A22
I/O
L16P_0
I/O
L13P_0
I/O
L10P_0
I/O
L03P_0
VCCO_0
VCCO_0
GND
GND
I/O
L17P_0
GCLK4
I/O
L44N_1
A21
I/O
L44P_1
A20
I/O
L15N_0
I/O
L09P_0
I/O
L11N_0
I/O
L08N_0
I/O
L07N_0
I/O
L05P_0
I/O
L02N_0
GND
I/O
L02P_0
VREF_0
I/O
L15P_0
I/O
L11P_0
I/O
L08P_0
I/O
L07P_0
I/O
L01N_0
I/O
L42N_1
I/O
L42P_1
I/O
L41N_1
VCCAUX
GND
I/O
L17N_0
GCLK5
I/O
L14N_0
I/O
L09N_0
I/O
L04P_0
I/O
L01P_0
I/O
L38P_1
I/O
L41P_1
VCCAUX
VCCO_1
INPUT
INPUT
TDO
I/O
L34N_1
A19
I/O
L34P_1
A18
I/O
L14P_0
I/O
L04N_0
I/O
L40N_1
I/O
L40P_1
I/O
L38N_1
VCCO_0
INPUT
GND
I/O
L46N_1
A25
I/O
L46P_1
A24
I/O
L30N_1
A15
I/O
I/O
INPUT INPUT INPUT INPUT INPUT
INPUT
GND
G
H
J
L36P_1
L36N_1
I/O
L33N_1
A17
I/O
L33P_1
A16
I/O
L30P_1
A14
INPUT
INPUT
INPUT INPUT
L39P_1
I/O
L37N_1
INPUT INPUT
L47P_1
VREF_0
L47N_1
L39N_1
VREF_1
INPUT
L43N_1
VREF_1
I/O
L29N_1
A13
I/O
L29P_1
A12
I/O
L26N_1
A11
INPUT
I/O
L37P_1
VCCO_1
VCCINT GND
GND VCCINT
GND
GND
L43P_1
I/O
L25P_1
IRDY1
INPUT
L35P_1
VREF_1
I/O
L25N_1
RHCLK7
I/O
L26P_1
A10
INPUT INPUT
L35N_1
I/O
L32P_1
I/O
L32N_1
VCCO_1
K
L
L31N_1
RHCLK6
I/O
L22N_1
TRDY1
RHCLK3
I/O
L22P_1
I/O
L21N_1
RHCLK2 RHCLK1
INPUT INPUT
I/O
L28P_1
I/O
L28N_1
VCCINT GND VCCINT
GND VCCINT GND
VCCINT GND VCCINT
INPUT VCCINT GND
GND
L31P_1
L27N_1
INPUT
L27P_1
VREF_1
I/O
L24P_1
RHCLK4
I/O
L24N_1
RHCLK5
I/O
L21P_1
RHCLK0
INPUT INPUT
VCCAUX
GND
M
N
P
R
T
L23N_1
L23P_1
INPUT
L16N_1
VREF_1
I/O
L20N_1
A9
I/O
L20P_1
A8
I/O
L19N_1
A7
I/O
L19P_1
A6
I/O
L18N_1
A5
I/O
L18P_1
A4
INPUT
L16P_1
I/O
L17N_1
A3
I/O
L15N_1
VREF_1
INPUT INPUT
I/O
L15P_1
VCCO_1
VCCO_1
GND
L08P_1
L08N_1
INPUT
L04N_1
VREF_1
INPUT
L12N_1
VREF_1
I/O
L17P_1
A2
INPUT INPUT INPUT INPUT
VREF_2 VREF_2 VREF_2 L04P_1
INPUT
L12P_1
I/O
L13P_1
I/O
L14P_1
I/O
L14N_1
I/O
L03P_1
A0
I/O
L03N_1
A1
INPUT INPUT
I/O
L13N_1
I/O
L11P_1
I/O
L11N_1
GND
INPUT INPUT
I/O
GND
VREF_2 VREF_2
I/O
L20N_2
GCLK3
INPUT
I/O
L10N_1
I/O
L10P_1
I/O
L09N_1
I/O
L09P_1
VCCO_2
L26N_2
INPUT
GND
U
V
W
Y
◆
D3
SUSPEND
I/O
I/O
I/O
I/O
L30N_2
I/O
L31N_2
I/O
L33N_2
I/O
L06P_1
I/O
L06N_1
I/O
L07N_1
VCCAUX
VCCO_1
L20P_2
L26P_2
L30P_2
INIT_B
GCLK2
I/O
I/O
L02P_1
LDC1
I/O
L02N_1
LDC0
I/O
I/O
L25P_2
I/O
L31P_2
I/O
L34N_2
I/O
L33P_2
I/O
L05N_1
I/O
L07P_1
GND
L23P_2
L18P_2
GCLK14
I/O
I/O
L28N_2
D1
I/O
L01N_1
LDC2
I/O
L21N_2
I/O
L23N_2
I/O
L25N_2
I/O
L27N_2
I/O
L34P_2
I/O
L05P_1
DONE
GND
L18N_2
GCLK15
I/O
I/O
I/O
L28P_2
D2
I/O
I/O
L01P_1
HDC
A
A
I/O
L22P_2
I/O
L32N_2
I/O
L35N_2
VCCO_2
VCCO_2
GND
L19P_2
L24N_2
L36N_2
GCLK0
DOUT
CCLK
I/O
I/O
L36P_2
D0
I/O
I/O
A
B
I/O
L21P_2
I/O
L27P_2
I/O
L29P_2
I/O
L29N_2
I/O
L32P_2
I/O
L35P_2
L22N_2
MOSI
GND
L19N_2
L24P_2
GCLK1
AWAKE
CSI_B
DIN/MISO
Bank 2
DS529-4_02_012009
Figure 26:
118
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FG676: 676-ball Fine-pitch Ball Grid Array
The 676-ball fine-pitch ball grid array, FG676, supports the
XC3S1400A FPGA.
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
Ball
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L15N_0
Type
I/O
Table 87 lists all the FG676 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
A19
B19
H15
G15
C18
D18
A18
B18
B17
C17
E15
F15
C16
D17
C15
D16
A15
B15
F14
E14
J14
IO_L15P_0
I/O
IO_L16N_0
I/O
IO_L16P_0
I/O
The XC3S1400A has 17 unconnected balls, indicated as
N.C. (No Connection) in Table 87 and with the black
diamond character () in Table 87 and Figure 27.
IO_L17N_0
I/O
IO_L17P_0
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at:
IO_L18N_0
I/O
IO_L18P_0
I/O
IO_L19N_0
I/O
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L19P_0
I/O
IO_L20N_0/VREF_0
IO_L20P_0
VREF
I/O
Pinout Table
IO_L21N_0
I/O
Table 87: Spartan-3A FG676 Pinout
IO_L21P_0
I/O
FG676
Bank
0
Pin Name
IO_L01N_0
Ball
F20
G20
F19
G19
C22
D22
C23
D23
A22
B23
G17
H17
B21
C21
D21
E21
C20
D20
K16
J16
Type
I/O
IO_L22N_0
I/O
IO_L22P_0
I/O
0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L05N_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0/VREF_0
I/O
IO_L23N_0
I/O
0
I/O
IO_L23P_0
I/O
0
VREF
I/O
IO_L24N_0
I/O
0
IO_L24P_0
I/O
0
I/O
IO_L25N_0/GCLK5
IO_L25P_0/GCLK4
IO_L26N_0/GCLK7
IO_L26P_0/GCLK6
IO_L27N_0/GCLK9
IO_L27P_0/GCLK8
IO_L28N_0/GCLK11
IO_L28P_0/GCLK10
IO_L29N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
0
I/O
K14
A14
B14
G13
F13
C13
B13
B12
A12
C12
D13
F12
E12
D11
C11
B10
A10
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
IO_L29P_0
I/O
0
I/O
IO_L30N_0
I/O
0
I/O
IO_L30P_0
I/O
0
I/O
IO_L31N_0
I/O
0
I/O
IO_L31P_0
I/O
0
I/O
IO_L32N_0/VREF_0
IO_L32P_0
VREF
I/O
0
E17
F17
A20
B20
I/O
0
I/O
IO_L33N_0
I/O
0
I/O
IO_L33P_0
I/O
0
VREF
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
119
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L34N_0
Ball
D10
C10
H12
G12
B9
Type
I/O
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Pin Name
Ball
D12
D15
D19
E11
E18
E20
F10
G14
G16
H13
H18
J10
J13
J15
D7
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VREF
N.C.
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IP_0
IO_L34P_0
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L37N_0
IO_L37P_0
IO_L38N_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
IO_L40N_0
IO_L40P_0
IO_L41N_0
IO_L41P_0
IO_L42N_0
IO_L42P_0
IO_L43N_0
IO_L43P_0
IO_L44N_0
IO_L44P_0
IO_L45N_0
IO_L45P_0
IO_L46N_0
IO_L46P_0
IO_L47N_0
IO_L47P_0
IO_L48N_0
IO_L48P_0
IO_L51N_0
IO_L51P_0
IO_L52N_0/PUDC_B
IO_L52P_0/VREF_0
IP_0
I/O
I/O
I/O
I/O
A9
I/O
D9
I/O
E10
B8
I/O
I/O
A8
I/O
K12
J12
D8
I/O
I/O
I/O
C8
I/O
C6
I/O
IP_0/VREF_0
IP_0/VREF_0
IP_0/VREF_0
IP_0/VREF_0
N.C. (◆)
B6
I/O
D14
G11
J17
A24
B24
D5
C7
I/O
B7
I/O
K11
J11
D6
I/O
I/O
N.C. (◆)
N.C.
I/O
N.C. (◆)
N.C.
C5
I/O
N.C. (◆)
E9
N.C.
B4
I/O
N.C. (◆)
F18
E6
N.C.
A4
I/O
N.C. (◆)
N.C.
H10
G10
H9
I/O
N.C. (◆)
F9
N.C.
I/O
N.C. (◆)
G18
B5
N.C.
I/O
VCCO_0
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
G9
E7
I/O
VCCO_0
B11
B16
B22
E8
I/O
VCCO_0
F7
I/O
VCCO_0
B3
I/O
VCCO_0
A3
I/O
VCCO_0
E13
E19
H11
H16
Y21
Y20
AD25
AE26
AC24
G8
F8
DUAL
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VCCO_0
VCCO_0
A5
VCCO_0
IP_0
A7
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IP_0
A13
A17
A23
C4
IP_0
IP_0
IP_0
120
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Ball
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L03P_1/A0
Ball
AC23
W21
W20
AC25
AD26
AB26
AC26
AB24
AB23
V19
Type
DUAL
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L26P_1/A4
Type
DUAL
DUAL
DUAL
DUAL
DUAL
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
DUAL
DUAL
I/O
T23
R17
R18
R26
R25
P20
P21
P25
P26
N24
P23
N19
P18
M25
M26
N21
P22
M23
L24
N17
N18
K26
K25
M20
N20
J25
IO_L04N_1
IO_L04P_1
IO_L05N_1
IO_L05P_1
IO_L06N_1
IO_L06P_1
IO_L07N_1/VREF_1
IO_L07P_1
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IO_L12N_1
IO_L12P_1
IO_L13N_1
IO_L13P_1
IO_L14N_1
IO_L14P_1
IO_L15N_1
IO_L15P_1
IO_L17N_1
IO_L17P_1
IO_L18N_1
IO_L18P_1
IO_L19N_1
IO_L19P_1
IO_L21N_1
IO_L21P_1
IO_L22N_1
IO_L22P_1
IO_L23N_1/VREF_1
IO_L23P_1
IO_L25N_1/A3
IO_L25P_1/A2
IO_L26N_1/A5
IO_L27N_1/A7
IO_L27P_1/A6
IO_L29N_1/A9
IO_L29P_1/A8
IO_L30N_1/RHCLK1
IO_L30P_1/RHCLK0
IO_L31N_1/TRDY1/RHCLK3
IO_L31P_1/RHCLK2
IO_L33N_1/RHCLK5
IO_L33P_1/RHCLK4
IO_L34N_1/RHCLK7
IO_L34P_1/IRDY1/RHCLK6
IO_L35N_1/A11
IO_L35P_1/A10
IO_L37N_1
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
V18
I/O
AA23
AA22
U20
V21
I/O
I/O
I/O
I/O
AA25
AA24
U18
U19
Y23
I/O
I/O
IO_L37P_1
I/O
I/O
IO_L38N_1/A13
IO_L38P_1/A12
IO_L39N_1/A15
IO_L39P_1/A14
IO_L41N_1
DUAL
DUAL
DUAL
DUAL
I/O
I/O
I/O
Y22
I/O
T20
I/O
U21
Y25
I/O
IO_L41P_1
I/O
I/O
IO_L42N_1/A17
IO_L42P_1/A16
IO_L43N_1/A19
IO_L43P_1/A18
IO_L45N_1
DUAL
DUAL
DUAL
DUAL
I/O
Y24
I/O
T17
I/O
T18
I/O
J26
V22
I/O
M22
M21
K22
K23
M18
M19
J22
W23
V25
I/O
IO_L45P_1
I/O
I/O
IO_L46N_1
I/O
V24
I/O
IO_L46P_1
I/O
U22
V23
I/O
IO_L47N_1
I/O
I/O
IO_L47P_1
I/O
R20
R19
U24
U23
R22
R21
T24
I/O
IO_L49N_1
I/O
I/O
IO_L49P_1
J23
I/O
VREF
I/O
IO_L50N_1
K21
L22
G24
G23
K20
I/O
IO_L50P_1
I/O
DUAL
DUAL
DUAL
IO_L51N_1
I/O
IO_L51P_1
I/O
IO_L53N_1
I/O
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
121
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pin Name
IO_L53P_1
Ball
L20
F24
F25
L17
L18
F23
E24
K18
K19
G22
F22
J20
Type
I/O
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IP_L48P_1
Ball
H23
G25
G26
B25
B26
AB25
E25
H22
L19
Type
INPUT
VREF
INPUT
INPUT
VREF
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
I/O
IO_L54N_1
I/O
IP_L52N_1/VREF_1
IP_L52P_1
IP_L65N_1
IP_L65P_1/VREF_1
VCCO_1
IO_L54P_1
I/O
IO_L55N_1
I/O
IO_L55P_1
I/O
IO_L56N_1
I/O
IO_L56P_1
I/O
VCCO_1
IO_L57N_1
I/O
VCCO_1
IO_L57P_1
I/O
VCCO_1
IO_L58N_1
I/O
VCCO_1
L25
IO_L58P_1/VREF_1
IO_L59N_1
VREF
I/O
VCCO_1
N22
T19
T25
W22
AD4
AC4
AA7
Y7
VCCO_1
IO_L59P_1
J19
I/O
VCCO_1
IO_L60N_1
D26
E26
D24
D25
H21
J21
I/O
VCCO_1
IO_L60P_1
I/O
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L05N_2
IO_L05P_2
IO_L06N_2
IO_L06P_2
IO_L07N_2
IO_L07P_2
IO_L08N_2
IO_L08P_2
IO_L09N_2
IO_L09P_2
IO_L10N_2
IO_L10P_2
IO_L11N_2
IO_L11P_2
IO_L12N_2
IO_L12P_2
IO_L13N_2
IO_L13P_2
IO_L14N_2
IO_L14P_2
IO_L15N_2
IO_L15P_2
IO_L61N_1
I/O
IO_L61P_1
I/O
IO_L62N_1/A21
IO_L62P_1/A20
IO_L63N_1/A23
IO_L63P_1/A22
IO_L64N_1/A25
IO_L64P_1/A24
IP_L16N_1
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
INPUT
INPUT
VREF
INPUT
VREF
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
Y9
C25
C26
G21
H20
Y26
W25
V26
W26
U26
U25
R24
R23
N25
N26
N23
M24
L23
K24
H25
H26
H24
W9
I/O
AF3
AE3
AF4
AE4
AD6
AC6
W10
V10
AE6
AF5
AE7
AD7
AA10
Y10
U11
V11
AB7
AC8
AC9
AB9
I/O
I/O
I/O
I/O
IP_L16P_1
I/O
IP_L20N_1/VREF_1
IP_L20P_1
I/O
I/O
IP_L24N_1/VREF_1
IP_L24P_1
I/O
I/O
IP_L28N_1
I/O
IP_L28P_1/VREF_1
IP_L32N_1
I/O
I/O
IP_L32P_1
I/O
IP_L36N_1
I/O
IP_L36P_1/VREF_1
IP_L40N_1
I/O
I/O
IP_L40P_1
I/O
IP_L44N_1
I/O
IP_L44P_1/VREF_1
IP_L48N_1
I/O
I/O
122
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Ball
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L16N_2
Ball
W12
V12
Type
I/O
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
IO_L35P_2
Type
I/O
V15
AE18
AF18
AE19
AF19
AB16
AC16
AE20
AF20
AC19
AD19
AC20
AD20
U16
IO_L16P_2
I/O
IO_L36N_2/D1
IO_L36P_2/D2
IO_L37N_2
IO_L37P_2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
IO_L40N_2
IO_L40P_2
IO_L41N_2
IO_L41P_2
IO_L42N_2
IO_L42P_2
IO_L43N_2
IO_L43P_2
IO_L44N_2
IO_L44P_2
IO_L45N_2
IO_L45P_2
IO_L46N_2
IO_L46P_2
IO_L47N_2
IO_L47P_2
IO_L48N_2
IO_L48P_2
IO_L51N_2
IO_L51P_2
IO_L52N_2/CCLK
IO_L52P_2/D0/DIN/MISO
IP_2
DUAL
DUAL
I/O
IO_L17N_2/VS2
IO_L17P_2/RDWR_B
IO_L18N_2
AA12
Y12
DUAL
DUAL
I/O
AF8
I/O
IO_L18P_2
AE8
I/O
I/O
IO_L19N_2/VS0
IO_L19P_2/VS1
IO_L20N_2
AF9
DUAL
DUAL
I/O
I/O
AE9
I/O
W13
V13
I/O
IO_L20P_2
I/O
I/O
IO_L21N_2
AC12
AB12
AF10
AE10
AC11
AD11
AE12
AF12
Y13
I/O
I/O
IO_L21P_2
I/O
I/O
IO_L22N_2/D6
IO_L22P_2/D7
IO_L23N_2
DUAL
DUAL
I/O
I/O
I/O
V16
I/O
IO_L23P_2
I/O
Y17
I/O
IO_L24N_2/D4
IO_L24P_2/D5
IO_L25N_2/GCLK13
IO_L25P_2/GCLK12
IO_L26N_2/GCLK15
IO_L26P_2/GCLK14
IO_L27N_2/GCLK1
IO_L27P_2/GCLK0
IO_L28N_2/GCLK3
IO_L28P_2/GCLK2
IO_L29N_2
DUAL
DUAL
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
AA17
AD21
AE21
AC21
AD22
V17
I/O
I/O
I/O
AA13
AE13
AF13
AA14
Y14
I/O
I/O
I/O
W17
I/O
AA18
AB18
AE23
AF23
AE25
AF25
AE24
AF24
AA19
AB13
AB17
AB20
AC7
I/O
AE14
AF14
AC14
AD14
AB15
AC15
W15
V14
I/O
I/O
I/O
IO_L29P_2
I/O
I/O
IO_L30N_2/MOSI/CSI_B
IO_L30P_2
DUAL
I/O
I/O
DUAL
DUAL
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
IO_L31N_2
I/O
IO_L31P_2
I/O
IO_L32N_2/DOUT
AE15
DUAL
IP_2
PWR
MGMT
IP_2
2
IO_L32P_2/AWAKE
AD15
IP_2
2
2
2
2
2
IO_L33N_2
AD17
AE17
Y15
I/O
I/O
IP_2
IO_L33P_2
IP_2
AC13
AC17
AC18
AD9
IO_L34N_2/D3
IO_L34P_2/INIT_B
IO_L35N_2
DUAL
DUAL
I/O
IP_2
AA15
U15
IP_2
IP_2
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
123
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
Pin Name
Ball
AD10
AD16
AF2
AF7
Y11
Type
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
N.C.
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L05P_3
Ball
K9
E4
D3
F4
E3
G4
F5
H6
J7
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
IP_2
IP_2
IP_2
IP_2
IP_2
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L13N_3
IO_L13P_3
IO_L14N_3
IO_L14P_3
IO_L15N_3
IO_L15P_3
IO_L17N_3
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L25N_3
IO_L25P_3
IO_L26N_3
IO_L26P_3
IO_L27N_3
IO_L27P_3
IO_L28N_3
IO_L28P_3
IO_L29N_3/VREF_3
IO_L29P_3
IO_L30N_3
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
IP_2/VREF_2
N.C. (◆)
AA9
AA20
AB6
AB10
AC10
AD12
AF15
AF17
AF22
Y16
F2
E1
J6
K7
F3
G3
L9
AA8
AC5
AC22
AD5
Y18
N.C. (◆)
N.C.
L10
H1
H2
L7
N.C. (◆)
N.C.
N.C. (◆)
N.C.
N.C. (◆)
N.C.
N.C. (◆)
Y19
N.C.
K6
J4
N.C. (◆)
AD23
W18
Y8
N.C.
N.C. (◆)
N.C.
J5
N.C. (◆)
N.C.
M9
M10
K4
K5
K2
K3
L3
VCCO_2
AB8
AB14
AB19
AE5
AE11
AE16
AE22
W11
W16
J9
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
I/O
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
L4
VCCO_2
M7
M8
M3
M4
M6
M5
M1
M2
N4
VCCO_2
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
J8
I/O
B1
I/O
B2
I/O
H7
I/O
G6
I/O
K8
I/O
124
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Ball
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L30P_3
Ball
N5
N2
N1
N7
N6
P2
P1
P3
P4
P10
N9
R2
R1
R4
R3
T4
Type
I/O
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Pin Name
IO_L52P_3
Type
I/O
W3
Y2
IO_L31N_3
I/O
IO_L53N_3
IO_L53P_3
IO_L55N_3
IO_L55P_3
IO_L56N_3
IO_L56P_3
IO_L57N_3
IO_L57P_3
IO_L59N_3
IO_L59P_3
IO_L60N_3
IO_L60P_3
IO_L61N_3
IO_L61P_3
IO_L63N_3
IO_L63P_3
IO_L64N_3
IO_L64P_3
IO_L65N_3
IO_L65P_3
IP_L04N_3/VREF_3
IP_L04P_3
I/O
IO_L31P_3
I/O
Y1
I/O
IO_L32N_3/LHCLK1
IO_L32P_3/LHCLK0
IO_L33N_3/IRDY2/LHCLK3
IO_L33P_3/LHCLK2
IO_L34N_3/LHCLK5
IO_L34P_3/LHCLK4
IO_L35N_3/LHCLK7
IO_L35P_3/TRDY2/LHCLK6
IO_L36N_3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
AA3
AA2
U8
I/O
I/O
I/O
U7
I/O
Y6
I/O
Y5
I/O
V6
I/O
V7
I/O
AC1
AB1
V8
I/O
IO_L36P_3/VREF_3
IO_L37N_3
VREF
I/O
I/O
I/O
IO_L37P_3
I/O
U9
I/O
IO_L38N_3
I/O
W6
W7
AC3
AC2
AD2
AD1
C1
I/O
IO_L38P_3
T3
I/O
I/O
IO_L39N_3
P6
P7
R6
R5
P9
P8
U4
T5
I/O
I/O
IO_L39P_3
I/O
I/O
IO_L40N_3
I/O
I/O
IO_L40P_3
I/O
I/O
IO_L41N_3
I/O
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
INPUT
INPUT
INPUT
VREF
IO_L41P_3
I/O
C2
IO_L42N_3
I/O
IP_L08N_3
D1
IO_L42P_3
I/O
IP_L08P_3
D2
IO_L43N_3
R9
R10
U2
U1
R7
R8
V2
V1
T9
I/O
IP_L12N_3/VREF_3
IP_L12P_3
H4
IO_L43P_3/VREF_3
IO_L44N_3
VREF
I/O
G5
G1
G2
J2
IP_L16N_3
IO_L44P_3
I/O
IP_L16P_3
IO_L45N_3
I/O
IP_L20N_3/VREF_3
IP_L20P_3
IO_L45P_3
I/O
J3
IO_L47N_3
I/O
IP_L24N_3
K1
IO_L47P_3
I/O
IP_L24P_3
J1
IO_L48N_3
I/O
IP_L46N_3
V4
IO_L48P_3
T10
V5
U5
U6
T7
I/O
IP_L46P_3
U3
IO_L49N_3
I/O
IP_L50N_3/VREF_3
IP_L50P_3
W2
W1
Y4
IO_L49P_3
I/O
IO_L51N_3
I/O
IP_L54N_3
IO_L51P_3
I/O
IP_L54P_3
Y3
IO_L52N_3
W4
I/O
IP_L58N_3/VREF_3
AA5
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
125
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Bank
3
Pin Name
IP_L58P_3
Ball
AA4
AB4
AB3
AE2
AE1
AB2
E2
Type
INPUT
INPUT
INPUT
VREF
INPUT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GND
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Ball
C19
C24
F1
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
IP_L62N_3
IP_L62P_3
IP_L66N_3/VREF_3
IP_L66P_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
3
3
F6
3
F11
F16
F21
F26
H3
3
3
3
H5
3
L2
3
L8
H8
3
P5
H14
H19
J24
K10
K17
L1
3
T2
3
T8
3
W5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
GND
A6
GND
GND
A11
A16
A21
A26
AA1
AA6
AA11
AA16
AA21
AA26
AD3
AD8
AD13
AD18
AD24
AF1
AF6
AF11
AF16
AF21
AF26
C3
GND
L6
GND
GND
L11
L13
L15
L21
L26
M12
M14
M16
N3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N8
GND
GND
N11
N15
P12
P16
P19
P24
R11
R13
R15
T1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T6
GND
C9
GND
T12
T14
GND
C14
GND
126
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Table 87: Spartan-3A FG676 Pinout(Continued)
Table 87: Spartan-3A FG676 Pinout(Continued)
FG676
FG676
Ball
Bank
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin Name
Ball
T16
T21
T26
U10
U13
U17
V3
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Bank
Pin Name
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
M17
N12
N13
N14
N16
P11
P13
P14
P15
R12
R14
R16
T11
T13
T15
U12
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
W8
W14
W19
W24
PWR
MGMT
VCCAUX SUSPEND
V20
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
AB21 CONFIG
A2
A25
G7
CONFIG
JTAG
VCCAUX TDI
JTAG
VCCAUX TDO
E23
D4
JTAG
VCCAUX TMS
JTAG
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
AB5
VCCAUX
AB11 VCCAUX
AB22 VCCAUX
E5
E16
E22
J18
K13
L5
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
N10
P17
T22
U14
V9
K15
L12
L14
L16
M11
M13
M15
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
127
Pinout Descriptions
User I/Os by Bank
Table 88 indicates how the 502 available user-I/O pins are
distributed between the four I/O banks on the FG676
package. The AWAKE pin is counted as a dual-purpose I/O.
Table 88: User I/Os Per Bank for the XC3S1400A in the FG676 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
82
INPUT
20
DUAL
1
VREF
9
CLK
8
Top
0
1
2
3
120
130
120
132
502
Right
Bottom
Left
67
15
30
21
0
10
10
9
8
67
14
8
97
18
8
TOTAL
313
67
52
38
32
Footprint Migration Differences
The XC3S1400A FPGA is the only Spartan-3A device
offered in the FG676 package. However, Table 89
summarizes footprint and functionality differences between
the XC3S1400A and the XC3SD1800A in the Spartan-3A
DSP family. There are 17 unconnected balls in the
XC3S1400A that become 16 input-only pins and one I/O pin
in the XC3SD1800A. All other pins not listed in Table 89
unconditionally migrate between the Spartan-3A devices
and the Spartan-3A DSP devices available in the FG676
package. The arrows indicate the direction for easy
migration. For more details on the Spartan-3A DSP family
and pinouts, and additional differences in the FG676 pinout
for the XC3SD3400A device, see DS610.
Table 89: FG676 Footprint Differences
Pin
A24
B24
D5
Bank
XC3S1400A Migration
XC3SD1800A
INPUT
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
17
INPUT
INPUT
E6
VREF (INPUT)
INPUT
E9
F9
VREF (INPUT)
INPUT
F18
G18
W18
Y8
VREF (INPUT)
VREF (INPUT)
VREF (INPUT)
INPUT
Y18
Y19
AA8
AC5
AC22
AD5
AD23
INPUT
INPUT
INPUT
I/O
INPUT
VREF(INPUT)
DIFFERENCES
Legend:
This pin can unconditionally migrate from the device on
the left to the device on the right. Migration in the other
direction is possible depending on how the pin is
configured for the device on the right.
Æ
128
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
FG676 Footprint
Bank 0
1
2
3
4
5
6
7
8
9
10
11
12
13
Left Half of FG676
Package (Top View)
I/O
I/O
I/O
I/O
I/O
I/O
GND
INPUT
GND
INPUT
GND
INPUT
A
B
C
D
E
F
L51P_0
L45P_0
L38P_0
L36P_0
L33P_0
L29P_0
I/O
L28P_0
GCLK10
I/O
L02N_3
I/O
I/O
L51N_0
I/O
L45N_0
I/O
L41P_0
I/O
L42P_0
I/O
L38N_0
I/O
L36N_0
I/O
L33N_0
I/O
L29N_0
VCCO_0
VCCO_0
L02P_3
INPUT
L04N_3
VREF_3
I/O
L28N_0
GCLK11
INPUT
L04P_3
I/O
L44P_0
I/O
L41N_0
I/O
L42N_0
I/O
L40P_0
I/O
L34P_0
I/O
L32P_0
I/O
L30N_0
I/O: Unrestricted,
313
GND
INPUT
TMS
GND
general-purpose user I/O
I/O
L32N_0
VREF_0
N.C.
INPUT INPUT
L08N_3
I/O
L06P_3
I/O
INPUT
I/O
I/O
L37N_0
I/O
L34N_0
I/O
L30P_0
INPUT
INPUT: Unrestricted,
67
L08P_3
L44N_0 VREF_0 L40N_0
general-purpose input pin
N.C.
N.C.
N.C.
I/O
L11P_3
I/O
L07P_3
I/O
L06N_3
I/O
L48N_0
I/O
L37P_0
I/O
L31P_0
VCCO_3
VCCAUX
VCCO_0
VCCO_0
INPUT
DUAL: Configuration pins,
51
then possible user I/O
I/O
I/O
I/O
L27P_0
GCLK8
I/O
L11N_3
I/O
L14N_3
I/O
L07N_3
I/O
L09P_3
I/O
L31N_0
GND
GND
INPUT
I/O
GND
L52P_0
VREF_0
L48P_0
SUSPEND: Dedicated
I/O
L52N_0
PUDC_B
I/O
L27N_0
GCLK9
SUSPEND and
INPUT INPUT
L16N_3
I/O
L14P_3
I/O
L09N_3
INPUT
L12P_3
I/O
L03P_3
I/O
L47P_0
INPUT
I/O
L35P_0
2
TDI
G
H
J
dual-purpose AWAKE
L16P_3
L46P_0 VREF_0
Power Management pins
INPUT
L12N_3
VREF_3
I/O
L17N_3
I/O
L17P_3
I/O
L10N_3
I/O
L03N_3
I/O
L47N_0
I/O
L46N_0
I/O
L35N_0
VCCO_3
VCCO_0
GND
GND
INPUT
INPUT
VCCAUX
VREF: User I/O or input
38
voltage reference for bank
INPUT
L20N_3
VREF_3
INPUT
L24P_3
INPUT
L20P_3
I/O
L19N_3
I/O
L19P_3
I/O
L13N_3
I/O
L10P_3
I/O
L01P_3
I/O
L01N_3
I/O
INPUT
I/O
L39P_0
L43P_0
CLK: User I/O, input, or
clock buffer input
32
INPUT
L24N_3
I/O
L23N_3
I/O
L23P_3
I/O
L22N_3
I/O
L22P_3
I/O
L18P_3
I/O
L13P_3
I/O
L05N_3
I/O
L05P_3
I/O
GND
I/O
L39N_0
K
L
L43N_0
CONFIG: Dedicated
configuration pins
2
I/O
L25N_3
I/O
L25P_3
I/O
L18N_3
I/O
L15N_3
I/O
L15P_3
VCCO_3
VCCAUX
VCCO_3
GND
GND
GND VCCINT GND
VCCINT GND VCCINT
GND VCCINT VCCINT
VCCINT GND VCCINT
GND VCCINT GND
VCCINT GND VCCINT
I/O
L29N_3
VREF_3
JTAG: Dedicated JTAG
port pins
I/O
L29P_3
I/O
L27N_3
I/O
L27P_3
I/O
L28P_3
I/O
L28N_3
I/O
L26N_3
I/O
L26P_3
I/O
L21N_3
I/O
L21P_3
4
M
N
P
R
T
I/O
I/O
L32P_3
LHCLK0 LHCLK1
I/O
L32N_3
I/O
L31P_3
I/O
L31N_3
I/O
L30N_3
I/O
L30P_3
L35P_3
TRDY2
GND: Ground
VCCAUX
GND
GND
77
LHCLK6
I/O
I/O
L33P_3
LHCLK2
I/O
L34N_3
LHCLK5 LHCLK4
I/O
L34P_3
I/O
L35N_3
LHCLK7
I/O
L39N_3
I/O
L39P_3
I/O
L41P_3
I/O
L41N_3
L33N_3
IRDY2
VCCO_3
VCCO: Output voltage
supply for bank
36
LHCLK3
I/O
L36P_3
VREF_3
I/O
L43P_3
VREF_3
I/O
L36N_3
I/O
L37P_3
I/O
L37N_3
I/O
L40P_3
I/O
L40N_3
I/O
L45N_3
I/O
L45P_3
I/O
L43N_3
VCCINT: Internal core
23
supply voltage (+1.2V)
I/O
L38P_3
I/O
L38N_3
I/O
L42P_3
I/O
L51P_3
I/O
L48N_3
I/O
L48P_3
VCCO_3
VCCO_3
GND
GND
VCCAUX: Auxiliary supply
voltage
14
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCCINT GND
L13N_2
U
V
W
Y
L44P_3
L44N_3
L46P_3
L42N_3
L49P_3
L51N_3
L56P_3
L56N_3
L61P_3
N.C.: Not connected
17
◆
I/O
L47P_3
I/O
L47N_3
INPUT
L46N_3
I/O
L49N_3
I/O
L59N_3
I/O
L59P_3
I/O
L61N_3
I/O
L09P_2
I/O
L13P_2
I/O
L16P_2
I/O
L20P_2
VCCAUX
GND
INPUT
L50N_3
VREF_3
INPUT
L50P_3
I/O
L52P_3
I/O
L52N_3
I/O
L63N_3
I/O
L63P_3
I/O
L05P_2
I/O
L09N_2
I/O
L16N_2
I/O
L20N_2
VCCO_3
VCCO_2
INPUT
GND
GND
N.C.
I/O
L02P_2
M2
I/O
L17P_2
I/O
L25N_2
I/O
L53P_3
I/O
L53N_3
INPUT INPUT
L54P_3
I/O
L57P_3
I/O
L57N_3
I/O
L05N_2
I/O
L12P_2
L54N_3
RDWR_B GCLK13
INPUT
L58N_3
VREF_3
I/O
L02N_2
CSO_B
I/O
L17N_2
VS2
I/O
L25P_2
GCLK12
N.C.
A
A
I/O
L55P_3
I/O
L55N_3
INPUT
L58P_3
INPUT
VREF_2 L12N_2
I/O
GND
GND
A
B
I/O
INPUT INPUT
INPUT
I/O
I/O
INPUT
I/O
VCCO_3
VCCAUX
VCCO_2
VCCAUX
INPUT
INPUT
GND
L60P_3
L62P_3
L62N_3
VREF_2 L14N_2
L15P_2 VREF_2
L21P_2
I/O
L01P_2
M1
N.C.
A
C
I/O
L60N_3
I/O
L64P_3
I/O
L64N_3
I/O
I/O
L14P_2
I/O
INPUT
I/O
I/O
L21N_2
INPUT
L08P_2
L15N_2 VREF_2 L23N_2
I/O
L01N_2
M0
N.C.
A
D
I/O
L65P_3
I/O
L65N_3
I/O
L08N_2
I/O
L11P_2
I/O
INPUT
L23P_2 VREF_2
GND
GND
INPUT INPUT
INPUT
L66N_3
VREF_3
I/O
L19P_2
VS1
I/O
L22P_2
D7
I/O
L24N_2
D4
I/O
L26N_2
GCLK15
A
E
INPUT
L66P_3
I/O
L06P_2
I/O
L07P_2
I/O
L10N_2
I/O
L11N_2
I/O
L18P_2
VCCO_2
VCCO_2
I/O
L19N_2
VS0
I/O
L22N_2
D6
I/O
L24P_2
D5
I/O
L26P_2
GCLK14
A
F
I/O
L06N_2
I/O
L07N_2
I/O
L10P_2
I/O
L18N_2
GND
INPUT
GND
INPUT
GND
Bank 2
DS529-4_07_102506
Figure 27: FG676 Package Footprint (Top View)
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
129
Pinout Descriptions
Bank 0
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
L26N_0
GCLK7
N.C.
Right Half of FG676
Package (Top View)
I/O
I/O
I/O
I/O
I/O
GND
INPUT
GND
INPUT
TCK
GND
A
B
C
D
E
F
L23N_0
L18N_0
L15N_0
L14N_0
L07N_0
I/O
L26P_0
GCLK6
I/O
L14P_0
VREF_0
INPUT
L65P_1
VREF_1
N.C.
I/O
L23P_0
I/O
L19N_0
I/O
L18P_0
I/O
L15P_0
I/O
L09N_0
I/O
L07P_0
INPUT
L65N_1
VCCO_0
VCCO_0
I/O
L63N_1
A23
I/O
L63P_1
A22
I/O
L22N_0
I/O
L21N_0
I/O
L19P_0
I/O
L17N_0
I/O
L11N_0
I/O
L09P_0
I/O
L05N_0
I/O
L06N_0
GND
GND
INPUT
VCCO_0
GND
INPUT
VREF_0
I/O
L22P_0
I/O
L21P_0
I/O
L17P_0
I/O
L11P_0
I/O
L10N_0
I/O
L05P_0
I/O
L06P_0
I/O
L61N_1
I/O
L61P_1
I/O
L60N_1
INPUT
I/O
L20N_0
VREF_0
I/O
L24P_0
I/O
L13N_0
I/O
L10P_0
I/O
L56P_1
I/O
L60P_1
VCCAUX
GND
VCCAUX
VCCO_1
INPUT
N.C.
INPUT
TDO
I/O
L58P_1
VREF_1
I/O
L24N_0
I/O
L20P_0
I/O
L13P_0
I/O
L02N_0
I/O
L01N_0
I/O
L56N_1
I/O
L54N_1
I/O
L54P_1
GND
GND
I/O
L02P_0
VREF_0
I/O
L64N_1
A25
INPUT
L52N_1
VREF_1
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
GND
INPUT
G
H
J
L16P_0
L08N_0
L01P_0
L58N_1
L51P_1
L51N_1
L52P_1
I/O
L64P_1
A24
I/O
L62N_1
A21
INPUT
L44P_1
VREF_1
I/O
L16N_0
I/O
L08P_0
INPUT INPUT INPUT
VCCO_0
VCCO_1
INPUT
GND
L48P_1
L48N_1
L44N_1
I/O
L25N_0
GCLK5
I/O
L62P_1
A20
I/O
L43N_1
A19
I/O
L43P_1
A18
I/O
INPUT
L12P_0 VREF_0
I/O
L59P_1
I/O
L59N_1
I/O
L49N_1
I/O
L49P_1
VCCAUX
INPUT
GND
I/O
L25P_0
GCLK4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
I/O
I/O
VCCINT
GND
L12N_0
K
L
L57N_1
L57P_1
L53N_1
L50N_1
L46N_1
L46P_1
L40P_1
L41P_1
L41N_1
I/O
L38P_1
A12
I/O
L55N_1
I/O
L55P_1
I/O
L53P_1
I/O
L50P_1
INPUT
L40N_1
VCCO_1
VCCO_1
VCCINT GND VCCINT
GND
GND
I/O
L42N_1
A17
I/O
L38N_1
A13
INPUT
L36P_1
VREF_1
I/O
L35N_1
A11
I/O
L35P_1
A10
I/O
I/O
I/O
I/O
GND VCCINT GND VCCINT
I/O
M
N
P
R
T
L47N_1
L47P_1
L45P_1
L45N_1
I/O
L39P_1
A14
I/O
L34N_1
RHCLK7
I/O
L42P_1
A16
I/O
L33N_1
RHCLK5
I/O
L37N_1
INPUT
L36N_1
INPUT INPUT
L32N_1
VCCO_1
VCCINT GND VCCINT
VCCINT VCCINT GND
VCCINT GND VCCINT
GND VCCINT GND
L39N_1
A15
L32P_1
I/O
I/O
I/O
L30N_1
RHCLK1 RHCLK0
I/O
L30P_1
I/O
L33P_1
RHCLK4
I/O
L31P_1
RHCLK2
I/O
L37P_1
L34P_1
IRDY1
L31N_1
TRDY1
RHCLK3
VCCAUX
GND
GND
RHCLK6
I/O
L27N_1
A7
I/O
L27P_1
A6
I/O
I/O
L25N_1
A3
INPUT
L28P_1
VREF_1
I/O
L29P_1
A8
I/O
L29N_1
A9
I/O
L22P_1
I/O
L25P_1
L22N_1
A2
INPUT
L28N_1
I/O
L26P_1
A4
I/O
L26N_1
A5
I/O
L17N_1
I/O
L17P_1
I/O
VCCO_1
VCCAUX
VCCO_1
GND
L14N_1
GND
I/O
L23N_1
VREF_1
INPUT
L24N_1
VREF_1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
VCCAUX
GND
U
V
W
Y
L35N_2
L42N_2
L12N_1
L12P_1
L10N_1
L14P_1
L21N_1
L23P_1
L24P_1
INPUT
L20N_1
VREF_1
I/O
L31P_2
I/O
L35P_2
I/O
L42P_2
I/O
L46N_2
I/O
L08P_1
I/O
L08N_1
I/O
L10P_1
I/O
L18N_1
I/O
L21P_1
I/O
L19P_1
I/O
L19N_1
N.C.
N.C.
I/O
L31N_2
I/O
L46P_2
I/O
L04P_1
I/O
L04N_1
I/O
L18P_1
INPUT INPUT
VCCO_2
VCCO_1
GND
GND
N.C.
GND
L16P_1
L20P_1
I/O
L27P_2
GCLK0
I/O
L34N_2
D3
INPUT
2
VREF_2
I/O
L01P_1
HDC
I/O
L01N_1
LDC2
I/O
L43N_2
I/O
L13P_1
I/O
L13N_1
I/O
L15P_1
I/O
L15N_1
INPUT
L16N_1
I/O
L27N_2
GCLK1
I/O
L34P_2
INIT_B
A
A
I/O
L43P_2
I/O
L47N_2
INPUT
VREF_2
I/O
L09P_1
I/O
L09N_1
I/O
L11P_1
I/O
L11N_1
GND
INPUT
GND
GND
I/O
I/O
L07N_1
VREF_1
A
B
I/O
L38N_2
I/O
L47P_2
I/O
L07P_1
I/O
L06N_1
L30N_2
MOSI
VCCO_2
VCCO_2
VCCAUX
VCCO_1
INPUT
INPUT DONE
CSI_B
I/O
L03P_1
A0
I/O
L03N_1
A1
N.C.
A
C
I/O
L29N_2
I/O
L30P_2
I/O
L38P_2
I/O
L40N_2
I/O
L41N_2
I/O
L45N_2
I/O
L05N_1
I/O
L06P_1
INPUT INPUT
I/O
L32P_2
AWAKE
I/O
L02N_1
LDC0
N.C.
A
D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
VCCO_2
GND
GND
L33N_2
GND
L29P_2
L40P_2
L41P_2
L44N_2
L45P_2
L05P_1
I/O
L28N_2
GCLK3
I/O
L32N_2
DOUT
I/O
I/O
I/O
L52N_2
CCLK
I/O
L02P_1
LDC1
A
E
I/O
L37N_2
I/O
L39N_2
I/O
L44P_2
I/O
L48N_2
I/O
L51N_2
VCCO_2
L36N_2
L33P_2
D1
I/O
L52P_2
D0
I/O
L28P_2
GCLK2
I/O
INPUT
VREF_2
A
F
INPUT
VREF_2
I/O
L37P_2
I/O
L39P_2
INPUT
VREF_2
I/O
L48P_2
I/O
L51P_2
GND
GND
L36P_2
D2
DIN/MISO
Bank 2
DS529-4_08_012009
130
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
Pinout Descriptions
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/05/06
02/02/07
Initial release.
1.1
Promoted to Preliminary status. Added DOUT pin to DUAL-type pins in Table 57. Corrected counts for
DUAL pins and differential pairs in Table 59. Corrected minor typographical error on pin names for pin
numbers P24 and P25 in Table 66. Highlighted the differences in differential I/O pairs between the
XC3S50A and XC3S200A in the FT256 package, shown in Table 68 and added Table 74 and Table 75
to summarize the differences.
03/16/07
04/23/07
05/08/07
07/10/07
04/15/08
1.2
1.3
1.4
1.5
1.6
Corrected minor typographical error in Figure 19.
Added reference to compatible Spartan-3A DSP family.
Added note regarding banking rules.
Updated Thermal Characteristics in Table 62.
Added VQ100 for XC3S50A and XC3S200A and added FT256 for XC3S700A and XCS1400A to
Table 58, Table 59, and Table 62. Updated Thermal Characteristics with latest data in Table 62.
Corrected bank for T8 and type for U16 in Table 86. Removed VREF name on 6 unconnected N.C. pins
for XC3S1400A FG676 in Table 87 and Figure 27. These pins are noted as VREF if migrating up to the
XC3SD1800A in Table 89.
05/28/08
03/06/09
1.7
1.8
Added "Package Overview" section.
Corrected bank designation for SUSPEND to VCCAUX. Corrected bank designation for JTAG pins in
XC3S700A and XC3S1400A FT256 to VCCAUX.
08/19/10
2.0
Corrected pin 36 number in Figure 17 and Figure 18. Noted difference in FT256 P10/T10 function
between XC3S50A and larger devices in Table 68 and Table 74.
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
131
Pinout Descriptions
132
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
相关型号：
XC3S400A-4FTG256I
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 250MHz, 8064-Cell, CMOS, PBGA256, LEAD FREE, FPTBGA-256Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-4FGG400C
暂无描述Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-4FGG400I
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 280MHz, 8064-Cell, CMOS, PBGA400, 21 X 21 MM, ROHS COMPLIANT, FBGA-400Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-4FGG676I
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 667MHz, CMOS, PBGA676, ROHS COMPLIANT, FBGA-676Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-4FTG256I
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 667MHz, 8064-Cell, CMOS, PBGA256, ROHS COMPLIANT, FTBGA-256Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-4TQ144I
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 667MHz, CMOS, PQFP144, TQFP-144Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-4TQG144C
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 667MHz, CMOS, PQFP144, ROHS COMPLIANT, TQFP-144Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-5FG676C
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 770MHz, CMOS, PBGA676, FBGA-676Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S400AN-5TQ144C
Field Programmable Gate Array, 896 CLBs, 400000 Gates, 770MHz, CMOS, PQFP144, TQFP-144Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S50
Spartan-3 FPGA Family : Complete Data SheetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S50-4CP132C
Spartan-3 FPGA Family: Complete Data SheetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
XC3S50-4CP132I
Spartan-3 FPGA Family: Complete Data SheetWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
XILINX
©2020 ICPDF网 联系我们和版权申明