XC9572-15TQG100I [XILINX]
Flash PLD, 15ns, 72-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100;
| 型号： | XC9572-15TQG100I |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 15ns, 72-Cell, CMOS, PQFP100, LEAD FREE, TQFP-100 时钟 输入元件 可编程逻辑 |
| 文件： | 总9页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
0
R
XC9572 In-System
Programmable CPLD
0
5
DS065 (v5.0) May 17, 2013
Product Specification
Features
Description
•
•
•
•
•
7.5 ns pin-to-pin logic delays on all pins
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
fCNT to 125 MHz
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5V in-system programmable
-
-
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
•
•
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
90 product terms drive any or all of 18 macrocells
within Function Block
Operating current for each design can be approximated for
specific operating conditions using the following equation:
-
Global and product term clocks, output enables,
set and reset signals
I
CC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
•
•
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
•
•
•
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
Figure 1 shows a typical calculation for the XC9572 device.
•
•
•
•
3.3V or 5V I/O capability
200
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
(160)
•
Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP,
and 100-pin TQFP packages
(125)
100
(100)
(65)
0
50
100
Clock Frequency (MHz)
DS065_01_110501
Figure 1: Typical I vs. Frequency for XC9572
CC
© 1998, 2003–2006, 2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS065 (v5.0) May 17, 2013
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1
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
36
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
36
36
36
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
2
Macrocells
1 to 18
DS065_02_110101
Figure 2: XC9572 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
2
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DS065 (v5.0) May 17, 2013
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
Description
Value
Units
V
Supply voltage relative to GND
–0.5 to 7.0
V
V
V
CC
V
Input voltage relative to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Junction temperature
–0.5 to V + 0.5
CC
IN
V
–0.5 to V + 0.5
TS
CC
o
T
–65 to +150
+150
C
STG
o
T
C
J
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
Parameter
Commercial T = 0 C to 70 C
Min
4.75
4.5
4.75
4.5
3.0
0
Max
5.25
5.5
Units
o
o
V
Supply voltage for internal logic
and input buffers
V
CCINT
A
o
o
Industrial T = –40 C to +85 C
A
o
o
V
Supply voltage for output drivers
for 5V operation
Commercial T = 0 C to 70 C
5.25
5.5
V
CCIO
A
o
o
Industrial T = –40 C to +85 C
A
Supply voltage for output drivers for 3.3V operation
Low-level input voltage
3.6
V
0.80
V
V
V
IL
V
High-level input voltage
2.0
0
V
+ 0.5
CCINT
IH
V
Output voltage
V
CCIO
O
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
T
Data Retention
Program/Erase Cycles (Endurance)
-
-
Years
DR
N
10,000
Cycles
PE
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Max
-
Units
V
Output high voltage for 5V outputs
Output high voltage for 3.3V outputs
Output low voltage for 5V outputs
Output low voltage for 3.3V outputs
Input leakage current
I
I
I
I
= –4.0 mA, V = Min
2.4
V
V
OH
OH
OH
OL
OL
CC
= –3.2 mA, V = Min
2.4
-
CC
V
= 24 mA, V = Min
-
-
-
0.5
0.4
10
V
OL
CC
= 10 mA, V = Min
V
CC
I
I
V
V
= Max
CC
μA
IL
= GND or V
= Max
CC
IN
CC
CC
I/O high-Z leakage current
I/O capacitance
V
V
-
-
10
10
μA
pF
IH
= GND or V
IN
C
V
= GND
IN
IN
f = 1.0 MHz
I
Operating supply current
(low power mode, active)
V = GND, No load
f = 1.0 MHz
65 (Typical)
mA
CC
I
DS065 (v5.0) May 17, 2013
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3
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
AC Characteristics
XC9572-7
Min Max
XC9572-10
XC9572-15
Symbol
Parameter
I/O to output valid
Min
Max
Min
Max
Units
ns
T
T
-
7.5
-
-
10.0
-
8.0
0
15.0
PD
SU
I/O setup time before GCK
I/O hold time after GCK
4.5
6.0
-
-
ns
T
0
-
0
-
-
ns
H
T
GCK to output valid
-
4.5
-
-
6.0
-
8.0
ns
CO
(1)
f
16-bit counter frequency
125.0
111.1
-
95.2
55.6
4.0
4.0
-
-
MHz
MHz
ns
CNT
(2)
f
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
83.3
-
66.7
-
-
-
-
SYSTEM
T
0.5
-
2.0
PSU
T
4.0
-
4.0
-
-
ns
PH
T
-
8.5
5.5
5.5
9.5
9.5
-
-
10.0
6.0
6.0
10.0
10.0
-
12.0
11.0
11.0
14.0
14.0
-
ns
PCO
T
GTS to output valid
-
-
-
-
-
ns
OE
OD
T
GTS to output disable
-
ns
T
T
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
-
-
-
ns
POE
POD
WLH
-
-
-
ns
T
4.0
7.0
4.5
7.5
5.5
8.0
ns
T
Asynchronous preset/reset pulse width (High
or Low)
-
-
-
ns
APRPW
Notes:
1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
.
V
TEST
R
1
2
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
5.0V
3.3V
5.0V
3.3V
160Ω
260Ω
120Ω
360Ω
35 pF
35 pF
C
R
L
DS067_03_110101
Figure 3: AC Load Circuit
4
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DS065 (v5.0) May 17, 2013
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
Internal Timing Parameters
XC9572-7
Min Max
XC9572-10
XC9572-15
Symbol
Parameter
Min
Max
Min
Max
Units
Buffer Delays
T
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
-
-
-
-
-
-
2.5
1.5
4.5
5.5
2.5
0
-
-
-
-
-
-
3.5
2.5
6.0
6.0
3.0
0
-
-
-
-
-
-
4.5
3.0
7.5
11.0
4.5
0
ns
ns
ns
ns
ns
ns
IN
T
GCK
GSR
T
T
GTS
T
OUT
T
Output buffer enable/disable delay
EN
Product Term Control Delays
T
T
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
3.0
2.0
4.5
-
-
-
3.0
2.5
3.5
-
-
-
2.5
3.0
5.0
ns
ns
ns
PTCK
PTSR
T
PTTS
Internal Register and Combinatorial Delays
T
T
Combinatorial logic propagation delay
Register setup time
-
1.5
3.0
-
0.5
-
-
1.0
-
-
3.0
-
ns
ns
ns
ns
ns
ns
ns
ns
PDI
SUI
2.5
3.5
T
Register hold time
-
3.5
-
4.5
-
HI
T
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
0.5
6.5
-
-
0.5
7.0
-
-
0.5
8.0
-
COI
T
-
-
-
AOI
T
7.5
-
10.0
10.0
RAI
T
2.0
10.0
-
-
2.5
11.0
-
-
3.0
11.5
LOGI
T
Internal low power logic delay
-
LOGILP
Feedback Delays
T
FastCONNECT feedback delay
-
-
8.0
4.0
-
-
9.5
3.5
-
-
11.0
3.5
ns
ns
F
T
Function block local feedback delay
LF
Time Adders
(1)
T
Incremental product term allocator delay
Slew-rate limited delay
-
-
1.0
4.0
-
-
1.0
4.5
-
-
1.0
5.0
ns
ns
PTA
T
SLEW
Notes:
1. PTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
T
DS065 (v5.0) May 17, 2013
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5
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
XC9572 I/O Pins
Function Macro-
BScan
Order
Function Macro-
BScan
Order
Block
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
cell
PC44 PC84 PQ100 TQ100
Block
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
cell
PC44 PC84 PQ100 TQ100
1
–
1
–
–
2
3
–
4
1
18
15
20
22
16
17
27
19
16
13
18
20
14
15
25
17
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
1
–
11
–
25
17
31
32
19
34
35
21
26
40
33
41
43
36
37
45
39
–
43
34
51
52
37
55
56
39
44
62
54
63
65
57
58
67
60
61
68
66
73
74
69
78
79
70
72
83
76
84
87
80
91
88
92
81
41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
65
58
59
66
64
71
72
67
76
77
68
70
81
74
82
85
78
89
86
90
79
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
2
2
3
6
3
4
7
4
–
5
2
5
12
–
6
3
6
7
11
7
–
8
4
5
8
13
14
–
[1]
[1]
[1]
[1]
9
5
9
24
22
9
10
11
12
13
14
15
16
17
18
1
–
13
30
28
10
11
12
13
14
15
16
17
18
1
[1]
[1]
[1]
[1]
6
10
25
23
18
–
–
18
20
35
38
33
36
–
–
[1]
[1]
[1]
[1]
7
12
29
27
19
20
–
8
–
14
23
15
24
63
69
67
68
70
71
31
41
32
42
89
96
93
95
97
29
39
30
40
87
94
91
93
95
9
22
–
–
–
–
46
44
51
52
47
54
55
48
50
57
53
58
61
56
65
62
66
–
2
35
–
2
24
–
3
3
4
–
4
–
5
36
37
–
5
25
–
6
98
96
6
[2]
[2]
[2]
7
76
5
3
7
–
8
38
72
99
97
8
26
27
–
[1]
[1]
[1]
[1]
9
39
74
1
99
9
10
11
12
13
14
15
16
17
18
–
75
3
1
10
11
12
13
14
15
16
17
18
[1]
[1]
[1]
[1]
40
77
6
4
28
–
–
79
8
6
–
80
10
8
–
[3]
[3]
[3]
[3]
42
81
11
9
29
33
–
43
–
83
82
84
–
13
12
14
94
11
10
12
92
6
44
–
34
–
3
0
Notes:
1. Global control piN.
2. Global control pin GTS1 for PC84, PQ100, and TQ100.
3. Global control pin GTS1 for PC44.
6
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DS065 (v5.0) May 17, 2013
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
XC9572 Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
PC44
PC84
9
PQ100
TQ100
5
6
24
22
10
25
23
7
12
29
27
42
76
5
3
40
77
6
4
39
74
1
99
17
30
50
47
48
45
TDI
15
28
TDO
30
59
85
83
TMS
16
29
49
47
V
5V
21,41
32
38,73,78
22,64
7,59,100
28,40,53,90
5,57,98
26,38,51,88
CCINT
V
3.3V/5V
CCIO
GND
10,23,31
8,16,27,42,
49,60
2,23,33,46,64,71,
77,86
100,21,31,44,62,69,
75, 84
No Connects
-
-
4,9,21,26,36,45,48,
75, 82
2,7,19,24,34,43,46,
73, 80
DS065 (v5.0) May 17, 2013
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7
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
Device Part Marking and Ordering Combination Information
R
Device Type
Package
XC95xxx
TQ144
This line not
related to device
part number
Speed
7C
Operating Range
1
Sample package with part marking.
Speed
Device Ordering and
Part Marking Number
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range
(1)
Package Type
XC9572-7PC44C
XC9572-7PCG44C
XC9572-7PC84C
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
PC44
PCG44
PC84
44-pin
44-pin
84-pin
84-pin
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Quad Flat Pack (PQFP)
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
I
XC9572-7PCG84C
XC9572-7PQ100C
XC9572-7PQG100C
XC9572-7TQ100C
XC9572-7TQG100C
XC9572-10PC44C
XC9572-10PCG44C
XC9572-10PC84C
XC9572-10PCG84C
XC9572-10PQ100C
XC9572-10PQG100C
XC9572-10TQ100C
XC9572-10TQG100C
XC9572-10PC44I
PCG84
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Quad Flat Pack (PQFP)
PC44
PCG44
PC84
44-pin
44-pin
84-pin
84-pin
PCG84
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
PC44
PCG44
PC84
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Quad Flat Pack (PQFP)
44-pin
44-pin
84-pin
84-pin
XC9572-10PCG44I
XC9572-10PC84I
I
I
I
XC9572-10PCG84I
XC9572-10PQ100I
XC9572-10PQG100I
XC9572-10TQ100I
XC9572-10TQG100I
XC9572-15PC44C
XC9572-15PCG44C
XC9572-15PC84C
XC9572-15PCG84C
XC9572-15PQ100C
XC9572-15PQG100C
XC9572-15TQ100C
XC9572-15TQG100C
PCG84
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
PC44
PCG44
PC84
I
I
I
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Quad Flat Pack (PQFP)
I
44-pin
44-pin
84-pin
84-pin
C
C
C
C
C
C
C
C
PCG84
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
8
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DS065 (v5.0) May 17, 2013
Product Specification
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
R
XC9572 In-System Programmable CPLD
Speed
(pin-to-pin
delay)
Device Ordering and
Part Marking Number
Pkg.
Symbol
No. of
Pins
Operating
Range
(1)
Package Type
XC9572-15PC44I
XC9572-15PCG44I
XC9572-15PC84I
XC9572-15PCG84I
XC9572-15PQ100I
XC9572-15PQG100I
XC9572-15TQ100I
XC9572-15TQG100I
Notes:
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
PC44
PCG44
PC84
44-pin
44-pin
84-pin
84-pin
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
I
I
I
I
I
I
I
I
PCG84
PQ100 100-pin
PQG100 100-pin
TQ100 100-pin
TQG100 100-pin
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Revision History
The following table shows the revision history for this document.
Date
Version
3.0
Revision
Update AC characteristics and internal parameters.
Updated format.
12/04/1998
06/18/2003
08/21/2003
04/15/2005
04/03/2006
05/17/2013
4.0
4.1
Updated Package Device Marking Pin 1 orientation.
Added asynchronous preset/reset pulse width specification (T
4.2
)
APRPW
4.3
Added Warranty Disclaimer. Added Pb-Free package information.
5.0
The products listed in this data sheet are obsolete. See XCN11010 for further information.
DS065 (v5.0) May 17, 2013
www.xilinx.com
9
Product Specification
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